FET Small-Signal Analysis

Transcription

1 CHAPTER FET mall-ignal Analysis INTROUCTION Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of a high input impedance. They are also considered low-power consumption configurations with good frequency range and minimal size and weight. Both JFET and depletion MOFET devices can be used to design amplifiers having similar voltage gains. The depletion MOFET circuit, however, has a much higher input impedance than a similar JFET configuration. While a BJT device controls a large output (collector) current by means of a relatively small input (base) current, the FET device controls an output (drain) current by means of a small input (gate-voltage) voltage. In general, therefore, the BJT is a current-controlled device and the FET is a voltage-controlled device. In both cases, however, note that the output current is the controlled variable. Because of the high input characteristic of FETs, the ac equivalent model is somewhat simpler than that employed for BJTs. While the BJT had an amplification factor (beta), the FET has a transconductance factor, g m. The FET can be used as a linear amplifier or as a digital device in logic circuits. In fact, the enhancement MOFET is quite popular in digital circuitry, especially in CMO circuits that require very low power consumption. FET devices are also widely used in high-frequency applications and in buffering (interfacing) applications. Table 9.1, located at the end of the chapter, provides a summary of FET small-signal amplifier circuits and related formulas. While the common-source configuration is the most popular providing an inverted, amplified signal, one also finds common-drain (source-follower) circuits providing unity gain with no inversion and common-gate circuits providing gain with no inversion. As with BJT amplifiers, the important circuit features described in this chapter include voltage gain, input impedance, and output impedance. ue to the very high input impedance, the input current is generally assumed to be 0 A and the current gain is an undefined quantity. While the voltage gain of an FET amplifier is generally less than that obtained using a BJT amplifier, the FET amplifier provides a much higher input impedance than that of a BJT configuration. Output impedance values are comparable for both BJT and FET circuits. FET ac amplifier networks can also be analyzed using computer software. Using Ppice, one can perform a dc analysis to obtain the circuit bias conditions and an ac analysis to determine the small-signal voltage gain. Using Ppice transistor models, 401

2 one can analyze the circuit using specific transistor models. On the other hand, one can develop a program using a language such as BAIC that can perform both the dc and ac analyses and provide the results in a very special format. 9.2 FET MALL-INAL MOEL The ac analysis of an FET configuration requires that a small-signal ac model for the FET be developed. A major component of the ac model will reflect the fact that an ac voltage applied to the input gate-to-source terminals will control the level of current from drain to source. The gate-to-source voltage controls the drain-to-source (channel) current of an FET. Recall from Chapter 6 that a dc gate-to-source voltage controlled the level of dc drain current through a relationship known as hockley s equation: I I (1 V /V P ) 2. The change in collector current that will result from a change in gate-to-source voltage can be determined using the transconductance factor g m in the following manner: I g m V (9.1) The prefix trans- in the terminology applied to g m reveals that it establishes a relationship between an output and input quantity. The root word conductance was chosen because g m is determined by a voltage-to-current ratio similar to the ratio that defines the conductance of a resistor 1/R I/V. olving for g m in Eq. (9.1), we have: I g m (9.2) V raphical etermination of g m If we now examine the transfer characteristics of Fig. 9.1, we find that g m is actually the slope of the characteristics at the point of operation. That is, g m m y I (9.3) x V Following the curvature of the transfer characteristics, it is reasonably clear that the slope and, therefore, g m increase as we progress from V P to I. Or, in other words, as V approaches 0 V, the magnitude of g m increases. I I I g m V (= lope at Q-point) Q-Point I V V P 0 V Figure 9.1 efinition of g m using transfer characteristic. 402 Chapter 9 FET mall-ignal Analysis

3 Equation (9.2) reveals that g m can be determined at any Q-point on the transfer characteristics by simply choosing a finite increment in V (or in I ) about the Q-point and then finding the corresponding change in I (or V, respectively). The resulting changes in each quantity are then substituted in Eq. (9.2) to determine g m. etermine the magnitude of g m for a JFET with I 8 ma and V P 4 V at the following dc bias points: (a) V 0.5 V. (b) V 1.5 V. (c) V 2.5 V. EXAMPLE 9.1 olution The transfer characteristics are generated as Fig. 9.2 using the procedure defined in Chapter 6. Each operating point is then identified and a tangent line is drawn at each point to best reflect the slope of the transfer curve in this region. An appropriate increment is then chosen for V to reflect a variation to either side of each Q-point. Equation (9.2) is then applied to determine g m. I (a) g m 2. 1 ma 3.5 m V 0.6 V I (b) g m 1.8 ma 2.57 m V 0.7 V I (c) g m 1. 5 ma 1.5 m V 1.0 V Note the decrease in g m as V approaches V P. I (ma) 8 7 I = 8 ma ( ) 2 V 1 4 V g m at 0.5 V 0.6 V ma g m at 1.5 V 1.8 ma 3 g m at 2.5 V 0.7 V 1.5 ma V P 1.0 V 0 V (V) Figure 9.2 Calculating g m at various bias points. Mathematical efinition of g m The graphical procedure just described is limited by the accuracy of the transfer plot and the care with which the changes in each quantity can be determined. Naturally, the larger the graph the better the accuracy, but this can then become a cumbersome 9.2 FET mall-ignal Model 403

4 problem. An alternative approach to determining g m employs the approach used to find the ac resistance of a diode in Chapter 1, where it was stated that: The derivative of a function at a point is equal to the slope of the tangent line drawn at that point. If we therefore take the derivative of I with respect to V (differential calculus) using hockley s equation, an equation for g m can be derived as follows: I g m di d V Q-pt. d V Q-pt. dv I 1 V V P 2 d I dv 1 V 2I V 1 V d 2 V dv 1 V V P 2I 1 V d 1 V (1) d V dv V dv 2I 1 V V 0 1 V P P P P P P and g m 2 I V 1 V (9.4) V P P where V P denotes magnitude only to ensure a positive value for g m. It was mentioned earlier that the slope of the transfer curve is a maximum at V 0 V. Plugging in V 0 nto Eq. (9.4) will result in the following equation for the maximum value of g m for a JFET in which I and V P have been specified: g m 2 I V 1 0 V P P and g m0 2 I (9.5) V P where the added subscript 0 reminds us that it is the value of g m when V 0 V. Equation (9.4) then becomes g m g m0 1 V (9.6) V P EXAMPLE 9.2 For the JFET having the transfer characteristics of Example 9.1: (a) Find the maximum value of g m. (b) Find the value of g m at each operating point of Example 9.1 using Eq. (9.6) and compare with the graphical results. olution (a) g m0 2 I 2(8 ma) 4 m (maximum possible value of g m ) VP 4 V (b) At V 0.5 V, g m g m0 1 V V P 4 m V 3.5 m 4 V (versus 3.5 m graphically) 404 Chapter 9 FET mall-ignal Analysis

5 At V 1.5 V, g m g m0 1 V V At V 2.5 V, g m g m0 1 V V 4 m 1 P 4 m 1 P 1.5 V 4 V 2.5 m 2.5 V 4 V 1.5 m (versus 2.57 m graphically) (versus 1.5 m graphically) The results of Example 9.2 are certainly sufficiently close to validate Eq. (9.4) through (9.6) for future use when g m is required. On specification sheets, g m is provided as y fs where y indicates it is part of an admittance equivalent circuit. The f signifies forward transfer parameter, and the s reveals that it is connected to the source terminal. In equation form, g m y fs (9.7) For the JFET of Fig. 5.18, y fs ranges from 1000 to 5000 or 1 to 5 m. Plotting g m vs. V P ince the factor 1 V V of Eq. (9.6) is less than 1 for any value of V other than 0 V, the magnitude of g m will decrease as V approaches V P and the ratio V VP increases in magnitude. At V V P, g m g m0 (1 1) 0. Equation (9.6) defines a straight line with a minimum value of 0 and a maximum value of g m as shown by the plot of Fig g m () g m0 g m0 2 V P V P 2 0 V (V) Figure 9.3 Plot of g m vs. V. Figure 9.3 also reveals that when V is one-half the pinch-off value, g m will be one-half the maximum value. Plot g m vs. V for the JFET of examples 9.1 and 9.2. EXAMPLE 9.3 olution Note Fig FET mall-ignal Model 405

6 g m () 4 m 2 m 4 V 2 V 0 V (V) Figure 9.4 Plot of g m vs. V for a JFET with I 8 ma and V P 4 V. Impact of I on g m A mathematical relationship between g m and the dc bias current I can be derived by noting that hockley s equation can be written in the following form: 1 V V I I ubstituting Eq. (9.8) into Eq. (9.6) will result in P (9.8) g m g m0 1 V V g m0 I I (9.9) Using Eq. (9.9) to determine g m for a few specific values of I, the results are (a) If I I, P (b) If I I /2, (c) If I I /4, g m g m0 I I g m0 g m g m0 I / I g m0 g m g m0 I / I 4 g m0 0.5g m0 2 EXAMPLE 9.4 Plot g m vs. I for the JFET of Examples 9.1 through 9.3. olution ee Fig Chapter 9 FET mall-ignal Analysis

7 g m () 4 4 m m 2 2 m I I I (ma) I Figure 9.5 Plot of g m vs. I for a JFET with I 8 ma and V 4 V. The plots of Examples 9.3 and 9.4 clearly reveal that the highest values of g m are obtained when V approaches 0 V and I its maximum value of I. FET Input Impedance The input impedance of all commercially available FETs is sufficiently large to assume that the input terminals approximate an open circuit. In equation form, (FET) (9.10) For a JFET a practical value of 10 9 (1000 M) is typical, while a value of to is typical for MOFETs. FET Output Impedance The output impedance of FETs is similar in magnitude to that of conventional BJTs. On FET specification sheets, the output impedance will typically appear as y os with the units of. The parameter y os is a component of an admittance equivalent circuit, with the subscript o signifying an output network parameter and s the terminal (source) to which it is attached in the model. For the JFET of Fig. 5.18, y os has a range of 10 to 50 or 20 k (R 1/ 1/50 ) to 100 k (R 1/ 1/10 ). In equation form, 1 (FET) r d (9.11) y The output impedance is defined on the characteristics of Fig. 9.6 as the slope of the horizontal characteristic curve at the point of operation. The more horizontal the curve, the greater the output impedance. If perfectly horizontal, the ideal situation is on hand with the output impedance being infinite (an open circuit) an often applied approximation. In equation form, r d V (9.12) I V constant os 9.2 FET mall-ignal Model 407

8 I (ma) V = 0 V V = I r d V = constant at 1 V V Q-point V I 1 V 2 V 0 V (V) Figure 9.6 efinition of r d using FET drain characteristics. Note the requirement when applying Eq. (9.12) that the voltage V remain constant when r d is determined. This is accomplished by drawing a straight line approximating the V line at the point of operation. A V or I is then chosen and the other quantity measured off for use in the equation. EXAMPLE 9.5 etermine the output impedance for the FET of Fig. 9.7 for V 0 V and V 2 V at V 8 V. I (ma) V = 5 V V = 8 V I = 0.2 ma Figure 9.7 rain characteristics used to calculate r d in Example 9.5. V = 0 V V = 1 V V = 2 V I = 0.1 ma V = 3 V V = 4 V V (V) olution For V 0 V, a tangent line is drawn and V is chosen as 5 V, resulting in a I of 0.2 ma. ubstituting into Eq. (9.12), r d V 5 V 25 k I V 0 V 0.2 ma For V 2 V, a tangent line is drawn and V is chosen as 8 V, resulting in a I of 0.1 ma. ubstituting into Eq. (9.12), 408 Chapter 9 FET mall-ignal Analysis

9 r d V 8 V 80 k I V 2 V 0.1 ma g m revealing that r d does change from one operating region to another, with lower values typically occurring at lower levels of V (closer to 0 V). FET AC Equivalent Circuit Now that the important parameters of an ac equivalent circuit have been introduced and discussed, a model for the FET transistor in the ac domain can be constructed. The control of I d by V gs is included as a current source g m V gs connected from drain to source as shown in Fig The current source has its arrow pointing from drain to source to establish a 180 phase shift between output and input voltages as will occur in actual operation. V gs g m V gs r d Figure 9.8 FET ac equivalent circuit. The input impedance is represented by the open circuit at the input terminals and the output impedance by the resistor r d from drain to source. Note that the gate to source voltage is now represented by V gs (lower-case subscripts) to distinguish it from dc levels. In addition, take note of the fact that the source is common to both input and output circuits while the gate and drain terminals are only in touch through the controlled current source g m V gs. In situations where r d is ignored (assumed sufficiently large to other elements of the network to be approximated by an open circuit), the equivalent circuit is simply a current source whose magnitude is controlled by the signal V gs and parameter g m clearly a voltage-controlled device. iven y fs 3.8 m and y os 20, sketch the FET ac equivalent model. EXAMPLE 9.6 olution 1 1 g m y fs 3.8 m and r d 50 k y 20 resulting in the ac equivalent model of Fig os V gs V gs 50 kω Figure 9.9 FET ac equivalent model for Example FET mall-ignal Model 409

10 9.3 JFET FIXE-BIA CONFIURATION Now that the FET equivalent circuit has been defined, a number of fundamental FET small-signal configurations will be investigated. The approach will parallel the ac analysis of BJT amplifiers with a determination of the important parameters of,, and A v for each configuration. The fixed-bias configuration of Fig includes the coupling capacitors C 1 and C 2 that isolate the dc biasing arrangement from the applied signal and load; they act as short-circuit equivalents for the ac analysis. V R C 2 C 1 R V Figure 9.10 JFET fixed-bias configuration. Once the level of g m and r d are determined from the dc biasing arrangement, specification sheet, or characteristics, the ac equivalent model can be substituted between the appropriate terminals as shown in Fig Note that both capacitors have the short-circuit equivalent because the reactance X C 1/(2fC) is sufficiently small compared to other impedance levels of the network, and the dc batteries V and V are set to zero volts by a short-circuit equivalent. X C1 0 Ω X C2 0 Ω R g m V gs r d R Battery V replaced by short Battery V replaced by short Figure 9.11 ubstituting the JFET ac equivalent circuit unit into the network of Fig The network of Fig is then carefully redrawn as shown in Fig Note the defined polarity of V gs, which defines the direction of g m V gs. If V gs is negative, the direction of the current source reverses. The applied signal is represented by and the output signal across R by. : Figure 9.12 clearly reveals that R (9.13) because of the open-circuit equivalence at the input terminals of the JFET. 410 Chapter 9 FET mall-ignal Analysis

11 R Vgs g m V gs r d R Figure 9.12 Redrawn network of Fig : etting 0 V as required by the definition of will establish V gs as 0 V also. The result is g m V gs 0 ma, and the current source can be replaced by an open-circuit equivalent as shown in Fig The output impedance is R r d (9.14) If the resistance r d is sufficiently large (at least 101) compared to R, the approximation r d R R can often be applied and R r d 10R (9.15) g m V gs = 0 ma r d R Zo Figure 9.13 etermining. A v : olving for in Fig. 9.12, we find g m V gs (r d R ) but V gs and g m (r d R ) so that If r d 10R : o A v V g m (r d R ) (9.16) V i o A v V g m R V i rd10r (9.17) Phase Relationship: The negative sign in the resulting equation for A v clearly reveals a phase shift of 180 between input and output voltages. 9.3 JFET Fixed-Bias Configuration 411

12 EXAMPLE 9.7 The fixed-bias configuration of Example 6.1 had an operating point defined by V Q 2 V and I Q ma, with I 10 ma and V P 8 V. The network is redrawn as Fig with an applied signal. The value of y os is provided as 40. (a) etermine g m. (b) Find r d. (c) etermine. (d) Calculate. (e) etermine the voltage gain A v. (f) etermine A v ignoring the effects of r d. 20 V 2 kω C 1 C 2 I = 10 ma V P = 8 V 1 MΩ 2 V Figure 9.14 JFET configuration for Example 9.7. olution (a) g m0 2 I 2(1 0 ma) 2.5 m VP 8 V g m g m0 1 V Q V 2.5 m 1 ( 2 V) 1.88 m P ( 8 V) 1 1 (b) r d 25 k y os 40 (c) R 1 M (d) R r d 2 k25 k1.85 k (e) A v g m (R r d ) (1.88 m)(1.85 k) 3.48 (f) A v g m R (1.88 m)(2 k) 3.76 As demonstrated in part (f), a ratio of 25 k2 k12.51 between r d and R resulted in a difference of 8% in solution. 9.4 JFET ELF-BIA CONFIURATION Bypassed R The fixed-bias configuration has the distinct disadvantage of requiring two dc voltage sources. The self-bias configuration of Fig requires only one dc supply to establish the desired operating point. 412 Chapter 9 FET mall-ignal Analysis

13 R C 1 C 2 R R C Figure 9.15 elf-bias JFET configuration. The capacitor C across the source resistance assumes its short-circuit equivalence for dc, allowing R to define the operating point. Under ac conditions, the capacitor assumes the short-circuit state and short circuits the effects of R. If left in the ac, gain will be reduced as will be shown in the paragraphs to follow. The JFET equivalent circuit is established in Fig and carefully redrawn in Fig X C1 0 Ω X C2 0 Ω g m V gs r d R R R bypassed by X C V Figure 9.16 Network of Fig following the substitution of the JFET ac equivalent circuit. R Vgs g m V gs r d R Figure 9.17 Redrawn network of Fig ince the resulting configuration is the same as appearing in Fig. 9.12, the resulting equations,, and A v will be the same. : R (9.18) 9.4 JFET elf-bias Configuration 413

14 : r d R (9.19) If r d 10R, R rd10r (9.20) A v : A v g m (r d R ) (9.21) If r d 10R, A v g m R r d 10R (9.22) Phase relationship: The negative sign in the solutions for A v again indicates a phase shift of 180 between and. Unbypassed R If C is removed from Fig 9.15, the resistor R will be part of the ac equivalent circuit as shown in Fig In this case, there is no obvious way to reduce the network to lower its level of complexity. In determining the levels of,, and A v, one must simply be very careful with notation and defined polarities and direction. Initially, the resistance r d will be left out of the analysis to form a basis for comparison. V gs R g m V gs I Zo R R I o Figure 9.18 elf-bias JFET configuration including the effects of R with r d. : ue to the open-circuit condition between the gate and output network, the input remains the following: R (9.23) : The output impedance is defined by V I o o 0 etting 0 n Fig will result in the gate terminal being at ground potential (0 V). The voltage across R is then 0 V, and R has been effectively shorted out of the picture. 414 Chapter 9 FET mall-ignal Analysis

15 Applying Kirchhoff s current law will result in: I o I g m V g with so that R V gs g m V gs V gs (I o I )R I o I g m (I o I )R g m I o R g m I R or I o [1 g m R ] I [1 g m R ] and I o I (the controlled current source g m V gs 0 A for the applied conditions) ince I R then and (I o )R I o R V I o o R r d a I I r d If r d is included in the network, the equivalent will appear as shown in Fig R I o (9.24) ince R I o I V o I R I o 0 V Io we should try to find an expression for I o in terms of I. Applying Kirchhoff s current law: I o Figure 9.19 Including the effects of r d in the self-bias JFET configuration. but and I o g m V gs I rd I V rd V gs I o g m V gs r d V gs I 1 or I o g m V gs I R I using I R r r Now, d d V gs (I I o ) R 1 so that I o g m r (I I o ) R I R I r with the result that or I o d d I o 1 g mr s R r d I 1 g mr R r d R r d I 1 g mr R r d R r d 1 g m R R r d 9.4 JFET elf-bias Configuration 415

16 and V I o o I R I 1 g mr s R r d s R r d 1 g m R R r d 1 g mr R r d 1 g mr R R r d r d and finally, R (9.25a) For r d 10 R, 1 g mr R r R and 1 g m R R R d r d r d r d 1 g m R R and r d R (9.25b) r d 10R A v : For the network of Fig. 9.19, an application of Kirchhoff s voltage law on the input circuit will result in V gs V R 0 V gs I R The voltage across r d using Kirchhoff s voltage law is V R and I V R rd so that an application of Kirchhoff s current law will result in V R I g m V gs rd ubstituting for V gs from above and substituting for and V R we have I g m [ I R ] (I R ) (I R ) r d so that I 1 g mr R r g m d R or g m I 1 g m R R R rd The output voltage is then g m R I R 1 g m R R R r d and A v g m R (9.26) Vi 1 g m R R R r d 416 Chapter 9 FET mall-ignal Analysis

17 Again, if r d 10(R R ), A v g m R V 1 g i mr r d 10(R R ) (9.27) Phase Relationship: The negative sign in Eq. (9.26) again reveals that a 180 phase shift will exist between and. The self-bias configuration of Example 6.2 has an operating point defined by V Q 2.6 V and I Q 2.6 ma, with I 8 ma and V P 6 V. The network is redrawn as Fig with an applied signal. The value of y os is given as 20. (a) etermine g m. (b) Find r d. (c) Find. (d) Calculate with and without the effects of r d. Compare the results. (e) Calculate A v with and without the effects of r d. Compare the results. 20 V EXAMPLE kω C 2 C 1 I = 10 ma V P = 6 V 1 MΩ 1 kω Figure 9.20 Network for Example 9.8. olution (a) g m0 2 I 2(8 ma) 2.67 m VP 6 V g m g m0 1 V Q V 2.67 m 1 ( 2.6 V) P (6 V) 1.51 m 1 1 (b) r d 50 k y os 20 (c) R 1 M (d) With r d : r d 50 k10 R 33 k Therefore, R 3.3 k If r d R 3.3 k (e) With r d : g A v m R (1.51 m)(3.3 k) 1 (1.51 m)(1 k) 3.3 k 1k 1 g m R R R 5 rd 0 k JFET elf-bias Configuration 417

18 Without r d : g m R A v 1 g m R (1.51 m)(3.3 k) 1 (1.51 m)(1 k) 1.98 As above, the effect of r d was minimal because the condition r d 10(R R ) was satisfied. Note also that the typical gain of a JFET amplifier is less than that generally encountered for BJTs of similar configurations. Keep in mind, however, that is magnitudes greater than the typical of a BJT, which will have a very positive effect on the overall gain of a system. 9.5 JFET VOLTAE-IVIER CONFIURATION The popular voltage-divider configuration for BJTs can also be applied to JFETs as demonstrated in Fig V R 1 R C 2 C 1 R 2 R C Figure 9.21 JFET voltage-divider configuration. ubstituting the ac equivalent model for the JFET will result in the configuration of Fig Replacing the dc supply V by a short-circuit equivalent has grounded one end of R 1 and R. ince each network has a common ground, R 1 can be brought down in parallel with R 2 as shown in Fig R can also be brought down to ground but in the output circuit across r d. The resulting ac equivalent network now has the basic format of some of the networks already analyzed. R 1 R R 2 V gs g m V gs R R 1 R 2 V gs g m V gs r d R Figure 9.22 Network of Fig under ac conditions. Figure 9.23 Redrawn network of Fig Chapter 9 FET mall-ignal Analysis

19 : R 1 and R 2 are in parallel with the open-circuit equivalence of the JFET resulting in R 1 R 2 (9.28) : etting 0 V will set V gs and g m V gs to zero and r d R (9.29) For r d 10R, A v : R r d 10R (9.30) V gs and g m V gs (r d R ) so that A v g mvgs( r d R ) V V i gs and If r d 10R, o A v V g m (r d R ) (9.31) V i o i A v V g m R V r d 10R (9.32) Note that the equations for and A v are the same as obtained for the fixed-bias and self-bias (with bypassed R ) configurations. The only difference is the equation for, which is now sensitive to the parallel combination of R 1 and R JFET OURCE-FOLLOWER (COMMON-RAIN) CONFIURATION The JFET equivalent of the BJT emitter-follower configuration is the source-follower configuration of Fig Note that the output is taken off the source terminal and, when the dc supply is replaced by its short-circuit equivalent, the drain is grounded (hence, the terminology common-drain). V C 1 C 2 R R Figure 9.24 JFET source-follower configuration. 9.6 JFET ource-follower (Common-rain) Configuration 419

20 ubstituting the JFET equivalent circuit will result in the configuration of Fig The controlled source and internal output impedance of the JFET are tied to ground at one end and R on the other, with across R. ince g m V gs, r d, and R are connected to the same terminal and ground, they can all be placed in parallel as shown in Fig The current source reversed direction but V gs is still defined between the gate and source terminals. V gs g m V gs r d R I o V gs R R g m V gs r d R Figure 9.25 Network of Fig following the substitution of the JFET ac equivalent model. Figure 9.26 Network of Fig redrawn. : Figure 9.26 clearly reveals that is defined by R (9.33) : etting 0 V will result in the gate terminal being connected directly to ground as shown in Fig The fact that V gs and are across the same parallel network results in V gs. V gs I o g m V gs r d R Figure 9.27 etermining for the network of Fig Applying Kirchhoff s current law at node s, I o g m V gs I rd I R The result is o V o V r d R I o 1 1 r g mv gs R d 1 1 r g m[ ] R d 1 1 g m r R d 420 Chapter 9 FET mall-ignal Analysis

21 and Vo 1 1 I o V o 1 1 g m g r m d R r d R r d R 1/ g m which has the same format as the total resistance of three parallel resistors. Therefore, g m r d R 1/g m (9.34) For r d 10R, R 1/g m rd10r (9.35) A v : The output voltage is determined by g m V gs (r d R ) and applying Kirchhoff s voltage law around the perimeter of the network of Fig will result in V gs and V gs so that g m ( )(r d R ) or g m (r d R ) g m (r d R ) and [1 g m (r d R )] g m (r d R ) so that A v g m (rdr) (9.36) Vi 1 gm( rdr) In the absence of r d or if r d 10R, A v g m R (9.37) Vi 1 gmr r d10r ince the bottom of Eq. (9.36) is larger than the numerator by a factor of one, the gain can never be equal to or greater than one (as encountered for the emitter-follower BJT network). Phase Relationship: ince A v of Eq. (9.36) is a positive quantity, and are in phase for the JFET source-follower configuration. A dc analysis of the source-follower network of Fig will result in V Q 2.86 V and I Q 4.56 ma. (a) etermining g m. (b) Find r d. (c) etermine. (d) Calculate with and without r d. Compare results. (e) etermine A v with and without r d. Compare results. 9 V I = 16 ma V P = 4 V y os = 25 µ EXAMPLE µ F 1 MΩ 0.05 µ F 2.2 kω Figure 9.28 Network to be analyzed in Example JFET ource-follower (Common-rain) Configuration 421

22 olution (a) g m0 2 I 2(1 6 ma) 8 m VP 4 V g m g m0 1 V Q V 8 m 1 ( V) P (4 V) 2.28 m 1 1 (b) r d 40 k y os 25 (c) R 1 M (d) With r d : r d R 1/g m 40 k2.2 k1/2.28 m 40 k2.2 k revealing that is often relatively small and determined primarily by 1/g m. Without r d : R 1/g m 2.2 k revealing that r d typically has little impact on. (e) With r d : g A v m (rdr) (2.28 m)(40 k2.2 k) 1 gm( rdr) 1 (2.28 m)(40 k2.2 k) (2.28 m)(2.09 k) (2.28 m)(2.09 k) which is less than 1 as predicted above. Without r d : g A v m R (2.28 m)(2.2 k) 1 gmr 1 (2.28 m)(2.2 k) revealing that r d usually has little impact on the gain of the configuration. 9.7 JFET COMMON-ATE CONFIURATION The last JFET configuration to be analyzed in detail is the common-gate configuration of Fig. 9.29, which parallels the common-base configuration employed with BJT transistors. ubstituting the JFET equivalent circuit will result in Fig Note the continuing requirement that the controlled source g m V gs be connected from drain to source with r d in parallel. The isolation between input and output circuits has obviously been lost since the gate terminal is now connected to the common ground of the network. In addition, the resistor connected between input terminals is no longer R but the resistor R connected from source to ground. Note also the location of the controlling voltage V gs and the fact that it appears directly across the resistor R. 422 Chapter 9 FET mall-ignal Analysis

23 r d C 1 R Z' i C 2 R V C 1 R a V gs g m V gs Z' o b R C 2 Figure 9.29 JFET common-gate configuration. Figure 9.30 Network of Fig following substitution of JFET ac equivalent model. : The resistor R is directly across the terminals defining. Let us therefore find the impedance of Fig. 9.29, which will simply be in parallel with R when is defined. The network of interest is redrawn as Fig The voltage VV gs. Applying Kirchhoff s voltage law around the output perimeter of the network will result in VV rd V R 0 and V rd VV R VIR I' I' Z' i a I rd g m V gs r d V rd V gs I' R V R Figure 9.31 etermining for the network of Fig Applying Kirchhoff s current law at node a results in Ig m V gs I rd and II rd g m V gs (V r d IR ) g m V gs or so that and or I V IR g m [V] r d r I 1 R r d V r d 1 g m d 1 R r d V (9.38) I 1 g m r V r d R I 1 gmrd d 9.7 JFET Common-ate Configuration 423

24 and Zi RZi r results in R d R 1 (9.39) gmrd If r d 10R, Eq. (9.38) permits the following approximation since R /r d 1 and 1/r d g m : 1 1 g m g m r and R 1/g m r d 10R (9.40) : ubstituting 0 n Fig will short-out the effects of R and set V gs to 0 V. The result is g m V gs 0, and r d will be in parallel with R. Therefore, For r d 10R, 1 R r d d R r d (9.41) R r d 10R (9.42) A v : Figure 9.30 reveals that and V gs I R The voltage across r d is and V rd I rd V i r d Applying Kirchhoff s current law at node b in Fig results in and so that and I rd I g m V gs 0 I I rd g m V gs V i r g m[ ] d I r d gm I R r d gm R R R g m r r d 1 R r d R r d g m R d 424 Chapter 9 FET mall-ignal Analysis

25 with A v (9.43) V i g mr R r d 1 R r d For r d 10R, the factor R /r d of Eq. (9.43) can be dropped as a good approximation and A v g m R r d 10R (9.44) Phase Relationship: The fact that A v is a positive number will result in an inphase relationship between and for the common-gate configuration. Although the network of Fig may not initially appear to be of the common-gate variety, a close examination will reveal that it has all the characteristics of Fig If V Q 2.2 V and I Q 2.03 ma: (a) etermine g m. (b) Find r d. (c) Calculate with and without r d. Compare results. (d) Find with and without r d. Compare results. (e) etermine with and without r d. Compare results. EXAMPLE V 3.6 kω 10 µ F I = 10 ma V P = 4 V y os = 50 µ Figure 9.32 Network for Example = 40 mv 10 µ F 1.1 kω olution (a) g m0 2 I 2(1 0 ma) 5 m VP 4 V g m g m0 1 V Q V 5 m 1 ( 2.2 V) P (4 V) 2.25 m 1 1 (b) r d 20 k y os 50 (c) With r d : r R d R 1 gmr 1.1 k 20 k3.6 k d 1 (2.25 ms)(20 k) 1.1 k0.51 k0.35 k 9.7 JFET Common-ate Configuration 425

26 Without r d : R 1/g m 1.1 k1/2.25 ms 1.1 k0.44 k 0.31 k Even though the condition, r d 10R 20 k10(3.6 k) 20 k36 k is not satisfied, both equations result in essentially the same level of impedance. In this case, 1/g m was the predominant factor. (d) With r d : R r d 3.6 k20 k3.05 k Without r d : R 3.6 k Again the condition r d 10R is not satisfied, but both results are reasonably close. R is certainly the predominant factor in this example. (e) With r d : A v g mr R r d 1 R r d (2.25 m)(3.6 k) 3. 6 k 20 k k 20 k o and A v V A v (7.02)(40 mv) mv Vi Without r d : A v g m R (2.25 m)(3.6 k) 8.1 with A v (8.1)(40 mv) 324 mv In this case, the difference is a little more noticeable but not dramatically so. Example 9.10 demonstrates that even though the condition r d 10R was not satisfied, the results for the parameters given were not significantly different using the exact and approximate equations. In fact, in most cases, the approximate equations can be used to find a reasonable idea of particular levels with a reduced amount of effort. 9.8 EPLETION-TYPE MOFETs The fact that hockley s equation is also applicable to depletion-type MOFETs results in the same equation for g m. In fact, the ac equivalent model for -MOFETs is exactly the same as that employed for JFETs as shown in Fig The only difference offered by -MOFETs is that V Q can be positive for n-channel devices and negative for p-channel units. The result is that g m can be greater than g m0 as demonstrated by the example to follow. The range of r d is very similar to that encountered for JFETs. 426 Chapter 9 FET mall-ignal Analysis

27 V gs g m V gs r d Figure MOFET ac equivalent model. The network of Fig was analyzed as Example 6.8, resulting in V Q 0.35 V and I Q 7.6 ma. (a) etermine g m and compare to g m0. (b) Find r d. (c) ketch the ac equivalent network for Fig (d) Find. 18 V (e) Calculate. (f) Find A v. EXAMPLE kω 110 MΩ C 2 C 1 I = 6 ma V P = 3 V y os = 10 µ 10 MΩ 150 Ω Figure 9.34 Network for Example olution (a) g m0 2 I 2(6 ma) 4 m VP 3 V g m g m0 1 V Q V 4 m 1 ( V) P ( 3 V) 4 m( ) 4.47 m 1 1 (b) r d 100 k y os 10 (c) ee Fig Note the similarities with the network of Fig Equations (9.28) through (9.32) are therefore applicable. 10 MΩ 110 MΩ V gs V gs 100 kω 1.8 kω Figure 9.35 AC equivalent circuit for Fig epletion-type MOFETs 427

28 (d) Eq. (9.28): R 1 R 2 10 M110 M9.17 M (e) Eq. (9.29): r d R 100 k1.8 k1.77 k R 1.8 k (f) r d 10R 100 k18 k Eq. (9.32): A v g m R (4.47 m)(1.8 k) ENHANCEMENT-TYPE MOFETs The enhancement-type MOFET can be either an n-channel (nmo) or p-channel (pmo) device, as shown in Fig The ac small-signal equivalent circuit of either device is shown in Fig. 9.36, revealing an open-circuit between gate and drainsource channel and a current source from drain to source having a magnitude dependent on the gate-to-source voltage. There is an output impedance from drain to source r d, which is usually provided on specification sheets as an admittance y os. The device transconductance, g m, is provided on specification sheets as the forward transfer admittance, y fs. pmo g m V gs r d nmo V gs g m = y fs, r d = 1 y os Figure 9.36 Enhancement MOFET ac small-signal model. In our analysis of JFETs, an equation for g m was derived from hockley s equation. For E-MOFETs, the relationship between output current and controlling voltage is defined by I k(v V (Th) ) 2 ince g m is still defined by I g m V we can take the derivative of the transfer equation to determine g m as an operating point. That is, di d g m k(v V (Th) ) 2 d k (V V (Th) ) 2 d V dv dv d 2k(V V (Th) ) (V V (Th) ) 2k(V V (Th) )(1 0) dv and g m 2k(V Q V (Th) ) (9.45) 428 Chapter 9 FET mall-ignal Analysis

29 Recall that the constant k can be determined from a given typical operating point on a specification sheet. In every other respect, the ac analysis is the same as that employed for JFETs or -MOFETs. Be aware, however, that the characteristics of an E-MOFET are such that the biasing arrangements are somewhat limited E-MOFET RAIN-FEEBACK CONFIURATION The E-MOFET drain-feedback configuration appears in Fig Recall from dc calculations that R could be replaced by a short-circuit equivalent since I 0 A and therefore V R 0 V. However, for ac situations it provides an important high impedance between and. Otherwise, the input and output terminals would be connected directly and. V C 2 R F C 1 R F R I i I i V gs g m V gs r d R Figure 9.37 E-MOFET drain-feedback configuration. Figure 9.38 AC equivalent of the network of Fig ubstituting the ac equivalent model for the device will result in the network of Fig Note that R F is not within the shaded area defining the equivalent model of the device but does provide a direct connection between input and output circuits. : Applying Kirchhoff s current law to the output circuit (at node in Fig. 9.38) results in Vo I i g m V gs rd R and V gs so that Vo I i g m rd R or Vo I i g m rd R Therefore, (r d R )(I i g m ) with I i (r d R )(I i g m ) R RF F and I i R F (r d R )I i (r d R )g m so that [1 g m (r d R )] I i [R F r d R ] and finally, V R i F r d R I i 1 gm (r d R ) (9.46) 9.10 E-MOFET rain-feedback Configuration 429

30 Typically, R F r d R, so that For r d 10R, RF 1 gm ( r d R ) RF (9.47) 1 gmr RFr d R, r d 10R : ubstituting 0 V will result in V gs 0 V and g m V gs 0, with a shortcircuit path from gate to ground as shown in Fig R F, r d, and R are then in parallel and R F r d R (9.48) R F = V gs = 0 V g m V gs = 0 ma r d R Figure 9.39 etermining for the network of Fig Normally, R F is so much larger than r d R that and with r d 10R, r d R R R F r d R, r d 10R (9.49) A v : but so that and so that and Applying Kirchhoff s current law at node of Fig will result in Vo I i g m V gs rd R V gs and I i R F V o gm R rd R F Vi Vo Vo g m R R rd R F F 1 r d 1R R F 1 g m R F 1 g m R A v V F o 1 Vi rd 1R R F 430 Chapter 9 FET mall-ignal Analysis

31 but 1 1 rd 1R R F RF rdr and 1 g m R F g m so that A v g m (R F r d R ) (9.50) ince R F is usually r d R and if r d 10R, A v g m R R F r d R, r d 10R (9.51) Phase Relationship: phase by 180. The negative sign for A v reveals that and are out of The E-MOFET of Fig was analyzed in Example 6.11, with the result that k A/V 2, V Q 6.4 V, and I Q 2.75 ma. (a) etermine g m. (b) Find r d. (c) Calculate with and without r d. Compare results. (d) Find with and without r d. Compare results. (e) Find A v with and without r d. Compare results. EXAMPLE V 2 kω 1 µf 10 MΩ 1 µf I ( on) = 6 ma V (on) = 8 V V (Th) = 3 V y os = 20 µ Figure 9.40 rain-feedback amplifier from Example olution (a) g m 2k(V Q V (Th) ) 2( A/V 2 )(6.4 V 3 V) 1.63 m 1 1 (b) r d 50 k y os 20 (c) With r d : RF rdr 10 M50 k2 k 1 gm( rdr) 1 (1.63 m)(50 k2 k) 10 M 1.92k 2.42 M E-MOFET rain-feedback Configuration 431

32 Without r d : RF 10 M 2.53 M 1 gmr 1 (1.63 m)(2 k) revealing that since the condition r d 10R 50 k40 k is satisfied, the results for with or without r d will be quite close. (d) With r d : R F r d R 10 M50 k2 k49.75 k2 k 1.92 k Without r d : R 2 k again providing very close results. (e) With r d : A v g m (R F r d R ) (1.63 m)(10 M50 k2 k) (1.63 m)(1.92 k) 3.21 Without r d : A v g m R (1.63 m)(2 k) 3.26 which is very close to the above result E-MOFET VOLTAE-IVIER CONFIURATION V The last E-MOFET configuration to be examined in detail is the voltage-divider network of Fig The format is exactly the same as appearing in a number of earlier discussions. ubstituting the ac equivalent network for the E-MOFET will result in the configuration of Fig. 9.42, which is exactly the same as Fig The result is that Eqs. (9.28) through (9.32) are applicable as listed below for the E-MOFET. R R 1 C 1 R 2 R C R 1 R 2 V gs g m V gs r d R Figure 9.41 E-MOFET voltage-divider configuration. Figure 9.42 AC equivalent network for the configuration of Fig Chapter 9 FET mall-ignal Analysis

33 : R 1 R 2 (9.52) : r d R (9.53) For r d 10R, R r d 10R (9.54) A v : o A v V g m (r R ) (9.55) V i and if r d 10R, o A v V g m R (9.56) V i 9.12 EININ FET AMPLIFIER NETWORK esign problems at this stage are limited to obtaining a desired dc bias condition or ac voltage gain. In most cases, the various equations developed are used in reverse to define the parameters necessary to obtain the desired gain, input impedance, or output impedance. To avoid unnecessary complexity during the initial stages of the design, the approximate equations are often employed because some variation will occur when calculated resistors are replaced by standard values. Once the initial design is completed, the results can be tested and refinements made using the complete equations. Throughout the design procedure be aware that although superposition permits a separate analysis and design of the network from a dc and an ac viewpoint, a parameter chosen in the dc environment will often play an important role in the ac response. In particular, recall that the resistance R could be replaced by a short-circuit equivalent in the feedback configuration because I 0 A for dc conditions, but for the ac analysis, it presents an important high impedance path between and. In addition, recall that g m is larger for operating points closer to the I axis (V 0 V), requiring that R be relatively small. In the unbypassed R network, a small R will also contribute to a higher gain, but for the source-follower, the gain is reduced from its maximum value of 1. In total, simply keep in mind that network parameters can affect the dc and ac levels in different ways. Often a balance must be made between a particular operating point and its impact on the ac response. In most situations, the available dc supply voltage is known, the FET to be employed has been determined, and the capacitors to be employed at the chosen frequency are defined. It is then necessary to determine the resistive elements necessary to establish the desired gain or impedance level. The next three examples will determine the required parameters for a specific gain esigning FET Amplifier Networks 433

34 EXAMPLE 9.13 esign the fixed-bias network of Fig to have an ac gain of 10. That is, determine the value of R. V (30 V) R C µ F R 10 MΩ I = 10 ma V P = 4 V y os = 20 µ Figure 9.43 Circuit for desired voltage gain in Example olution ince V Q 0 V, the level of g m is g m0. The gain is therefore determined by A v g m (R r d ) g m0 (R r d ) with g m0 2 I 2(1 0 ma) 5 m VP 4 V The result is 10 5 m(r r d ) 10 and R r d 2 k 5 m From the device specifications, 1 1 r d y os k ubstituting, we find R r d R 50 k2 k R(50 k) and 2 k R 50 k or 50R 2(R 50 k) 2R 100 k with 48R 100 k and R 100 k 2.08 k 48 The closest standard value is 2 k (Appendix C), which would be employed for this design. The resulting level of V Q would then be determined as follows: V Q V I Q R 30 V (10 ma)(2 k) 10 V The levels of and are set by the levels of R and R, respectively. That is, R 10 M R r d 2 k50 k1.92 k R 2 k. 434 Chapter 9 FET mall-ignal Analysis

35 Choose the values of R and R for the network of Fig that will result in a gain of 8 using a relatively high level of g m for this device defined at V Q 1 4 V P. EXAMPLE 9.14 V 20 V R C 2 C µ F 0 V 0.1 µ F R L 10 MΩ R 10 MΩ R I = 10 ma C V P = 4 V 40 µ F y os = 20 µ gm0 = 5 m Figure 9.44 Network for desired voltage gain in Example olution The operating point is defined by V Q 1 4 V P 1 (4 V) 1 V 4 and I I 1 V Q 10 ma VP 2 1 ( 1 V) ma ( 4 V) 2 etermining g m, g m g m0 1 V Q VP 5 m 1 ( 1 V) ( 4 V) 3.75 m The magnitude of the ac voltage gain is determined by A v g m (R r d ) ubstituting known values will result in 8 (3.75 m)(r r d ) 8 so that R r d 2.13 k 3.75 m The level of r d is defined by 1 1 r d 50 k y os 20 and R 50 k2.13 k with the result that R 2.2 k which is a standard value esigning FET Amplifier Networks 435

36 The level of R is determined by the dc operating conditions as follows: V Q I R 1 V (5.625 ma)r 1 V and R ma The closest standard value is 180. In this example, R does not appear in the ac design because of the shorting effect of C. In the next example, R is unbypassed and the design becomes a bit more complicated. EXAMPLE 9.15 etermine R and R for the network of Fig to establish a gain of 8 if the bypass capacitor C is removed. olution V Q and I Q are still 1 V and ma, and since the equation V I R has not changed, R continues to equal the standard value of 180 obtained in Example The gain of an unbypassed self-bias configuration is g A v m R 1 g mr For the moment it is assumed that r d 10(R R ). Using the full equation for A v at this stage of the design would simply complicate the process unnecessarily. ubstituting (for the specified magnitude of 8 for the gain), and (3.75 m)r 8 (3 1 (3.75 m)(180 ) 1 8( ) (3.75 m)r.75m)r so that R k m with the closest standard value at 3.6 k. We can now test the condition: r d 10(R R ) 50 k10(3.6 k0.18 k) 10(3.78 k) and 50 k37.8 k which is satisfied the solution stands! 9.13 UMMARY TABLE In an effort to provide a quick comparison between configurations and offer a listing that can be helpful for a variety of reasons, Table 9.1 was developed. The exact and approximate equation for each important parameter are provided with a typical range of values for each. Although all the possible configurations are not present, the majority of the most frequently encountered are included. In fact, any configuration not 436 Chapter 9 FET mall-ignal Analysis

37 TABLE 9.1, Z 0, and A v for various FET configurations Fixed-bias [JFET or -MOFET] Configuration A v V V o i C 1 V R C 2 High (10 M) R Medium (2 k) R r d Medium (10) g m (r d R ) R R (r d 10 R ) g m R (rd 10 R ) V elf-bias bypassed R s [JFET or -MOFET] V Medium (2 k) Medium (10) C 1 R C 2 High (10 M) R R r d R (r d 10 R ) g m (r d R ) g m R (r d 10 R ) R R C elf-bias unbypassed R [JFET or -MOFET] Low (2) C 1 R V R R C 2 High (10 M) R 1 g mr R r d R 1 g mr R r d R r d R rd10 R or r d g m R 1 g m R s R R r g m R 1 g mr d [r d 10(R d R )] Voltage-divider bias [JFET or -MOFET] V Medium (2 k) Medium (10) C 1 R 1 R C 2 High (10 M) R r g m (r d R ) R 1 R 2 R 2 R C R (r d 10 R ) g m R (r d 10 R ) 9.13 ummary Table 437

38 TABLE 9.1 (Continued) Configuration A v V i ource-follower [JFET or -MOFET] C 1 R V R C 2 High (10 M) R Low (100 k) r d R 1/g m R 1/g m (r d 10 R ) Low ( 1) g m (rdr) 1 gm( rdr) g m R 1 g mr (r d 10 R ) Common-gate [JFET or -MOFET] C1 Q 1 V R C 2 Low (1 k) r R d R 1 gmrd Medium (2 k) R r d R (rd 10 R ) Medium (10) g m R R r d 1 R r d Zi R R C 1 R g m (r d 10 R ) g m R (rd 10 R ) rain-feedback bias E-MOFET V R R C F 2 Vo Medium (1 M) RF rdr 1 gm( rdr) Medium (2 k) R F r d R Medium (10) g m (R F r d R ) C 1 RF 1 gmr (r d 10 R ) R (R F, r d 10 R ) g m R (R F, r d 10 R ) Voltage-divider bias E-MOFET V R 1 R C 2 Medium (1 M) Medium (2 k) R r d Medium (10) g m (r d R ) C 1 R 1 R 2 R (R d 10 R ) g m R (r d 10 R ) R 2 R 438 Chapter 9 FET mall-ignal Analysis

39 listed will probably be some variation of those appearing in the table, so at the very least, the listing will provide some insight as to what expected levels should be and which path will probably generate the desired equations. The format chosen was designed to permit a duplication of the entire table on the front and back of one by 11 inch page TROUBLEHOOTIN As mentioned before, troubleshooting a circuit is a combination of knowing the theory and having experience using meters and an oscilloscope to check the operation of the circuit. A good troubleshooter has a nose for finding the trouble in a circuit this ability to see what is happening being greatly developed through building, testing, and repairing many different circuits. For an FET small-signal amplifier, one could go about troubleshooting a circuit by performing a number of basic steps: 1. Look at the circuit board to see if any obvious problems can be seen: an area charred by excess heating of a component; a component that feels or seems too hot to touch; what appears to be a poor solder joint; any connection that appears to have come loose. 2. Use a dc meter: make some measurements as marked in a repair manual containing the circuit schematic diagram and a listing of test dc voltages. 3. Apply a test ac signal: measure the ac voltages starting at the input and working along toward the output. 4. If the problem is identified at a particular stage, the ac signal at various points should be checked using an oscilloscope to see the waveform, its polarity, amplitude, and frequency, as well as any unusual waveform glitches that may be present. In particular, observe that the signal is present for the full signal cycle. Possible ymptoms and Actions If there is no output ac voltage: 1. Check if the supply voltage is present. 2. Check if the output voltage at V is between 0 V and V. 3. Check if there is any input ac signal at the gate terminal. 4. Check the ac voltage at each side of the coupling capacitor terminals. When building and testing a FET amplifier circuit in the laboratory: 1. Check the color code of resistor values to be sure that they are correct. Even better, measure the resistor value as components used repeatedly may get overheated when used incorrectly, causing the nominal value to change. 2. Check that all dc voltages are present at the component terminals. Be sure that all ground connections are made common. 3. Measure the ac input signal to be sure the expected value is provided to the circuit PPICE WINOW JFET Fixed-Bias Configuration The first JFET configuration to be analyzed using Ppice Windows is the fixed-bias configuration of Fig. 9.45, which has a JFET with V P 4 V and I 10 ma. The 10-M resistor was added to act as a path to ground for the capacitor 9.15 Ppice Windows 439

40 but is essentially an open-circuit as a load. The J2N3819 n-channel JFET from the EVAL.slb library will be used, and the ac voltage will be determined at four different points for comparison and review. Figure 9.45 Fixed-bias JFET configuration with an ac source. The constant Beta is determined by I Beta 2 10 ma ma/v 2 Vp 4 and inserted as a Model Parameter using the sequence Edit-Model-Edit Instance Model (Text). Vto must also be changed to 4 V. The remaining elements of the network are set as described for the transistor in Chapter 8. An analysis of the network will result in the printout of Fig The chematics Netlist reveals the nodes assigned to each parameter and defines the nodes for which the ac voltage is to be printed. In this case, note that Vi is set at 10 mv at a frequency of 10kHz from node 2 to 0. In the list of Junction FET MOEL PARAMETER, VTO is 4 V and BETA is 625E-6 as entered. The MALL- INAL BIA OLUTION reveals that the voltage at both ends of R is 1.5 V, resulting in V 1.5 V. The voltage from drain to source (ground) is 12 V, leaving a drop of 8 V across R. The AC ANALYI at the end of the listing reveals that the voltage at the source (node 2) is 10 mv as set, but the voltage at the other end of the capacitor is 3 V less due to the impedance of the capacitor at 10 khz certainly a drop to be ignored. The choice of 0.02 F for this frequency was obviously a good one. The voltages before and after the capacitor on the output side are exactly the same (to three places), revealing that the larger the capacitor, the closer the characteristics to a short circuit. The output of 6.275E mv reflects a gain of The OPERATIN POINT INFORMATION reveals that I is 4 ma and g m is 3.2 m. Calculating the value of g m from: g m 2 I V P 1 V V Q P 2(1 0 4 ma) V 1 ( 1.5 V) ( 4 V) confirming our analysis m 440 Chapter 9 FET mall-ignal Analysis