# Lecture 140 Simple Op Amps (2/11/02) Page 140-1

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1 Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM , , AH ) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and CMOS op amps 2.) Prepare for the design of BJT and CMOS op amps Outline Simple CMOS Op Amps Twostage Foldedcascode Simple BJT Op Amps Twostage Foldedcascode Summary ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 40 Simple Op Amps (2//02) Page 402 SIMPLE TWOSTAGE CMOS OP AMPS TwoStage CMOS Op Amp Circuit: DC Conditions: = I bias, I = I 2 = 0.5 = 0.5I bias, = I 6 = ni Bias V icm (max) = V SG3 V T V icm (min) = V DS5 (sat) V GS V out (max) = V SD6 (sat) V out (min) = V DS7 (sat) Notice that the output stage is class A M8 I Bias M M2 I sink = and I source = K N W 6 2L 6 ( V T )2 I 3 I V SG4 M4 I 4 I 42 V SG6 I 6 Fig. 400 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

2 Lecture 40 Simple Op Amps (2//02) Page 403 DC Balance Conditions for the TwoStage Op Amp For best performance, keep all transistors in saturation. M4 is the only transistor that cannot be forced into saturation by internal connections or external voltages. Therefore, we develop conditions to force M4 to be in saturation..) First assume that V SG4 = V SG6. This will cause proper mirroring in the M4 mirror. Also, the gate and drain of M4 are at the same potential so that M4 is guaranteed to be in saturation. W i S 6 2.) Let S i L i, if V SG4 = V SG6, then I 6 = S 4 I 4 S 7 S 7 3.) However, = S 5 = S 5 2I 4 4.) For balance, I 6 must equal I S 6 7 S 4 = 2S 7 S 5 which is called the balance conditions 5.) So if the balance conditions are satisfied, then V DG4 = 0 and M4 is saturated. ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 M4 M M2 V SG4 I 4 V SG6 I 6 Fig Lecture 40 Simple Op Amps (2//02) Page 404 SmallSignal Performance of the TwoStage CMOS Op Amp M8 V SG4 V SG6 I Bias I 3 M4 I 4 I 6 I I 42 M M2 x x xn v v2 g m 2 g m r ds r ds3 C M g m3 2 g m4 v g m3 > g ds2 g ds4 C rds2 r ds4 g m6 v 2 r ds6 r ds7 g m3 C M > GB v 2 g m CI rds2 r ds4 g m6 v C 2 II rds6 r ds7 Fig ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

3 Lecture 40 Simple Op Amps (2//02) Page 405 SmallSignal Performance of the TwoStage CMOS Op Amp Summary of the small signal performance: Midband performance A o = g mi g mii R I R II g m g m6 (r ds2 r ds4 )(r ds6 r ds7 ), R out = r ds6 r ds7, R in = Roots Zero = g mii = g m6 Poles at p g mii R I R II = (g ds2g ds4 )(g ds6 g ds7 ) g m6 and p g mii m6 2 C II Assume that g m = 00µS, g m6 = ms, r ds2 = r ds4 = 2MΩ r ds6 = r ds7 = 0.5MΩ, = 5pF and = 0pF: A o = (00µS)(MΩ)(000µS)(0.25MΩ) = 25,000V/V, R in =, R out = 250kΩ Zero = 000µS/5pF = 2x08 rads/sec or 3.83MHz, jω p = (ms)(mω)(0.25mω)(5pf) 8x02 = 800 rads/sec or 27.3Hz, GB = 3.78MHz and p 2 = (000µS/0pF) = 08 rads/sec or 5.95MHz 08 2x08 Fig ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 σ Lecture 40 Simple Op Amps (2//02) Page 406 Slew Rate of a TwoStage CMOS Op Amp Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as I lim = C dv C dt where v C is the voltage across the capacitor C. >>0 M M4 M2 Positive Slew Rate I5 Assume a virtural ground I 6 I CL <<0 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 M M4 M2 Assume a virtural ground I 6 =0 ICL Negative Slew Rate Fig SR = min I 5, I 6 = Cc because I 6 >> SR = min, = Cc if >>. Therefore, if is not too large and if is significantly greater than, then the slew rate of the twostage op amp should be, SR =

4 Lecture 40 Simple Op Amps (2//02) Page 407 Folded Cascode, CMOS Op Amp Circuit: M4 M4 I 4 A B R A R B Comments: The bias currents, I 4 and, should be designed so that I 6 and never become zero (i.e. =I 6 =.5I 3 ) This amplifier is nearly balanced (would be exactly if R A was equal to R B ) M M2 I I 2 Self compensating Poor noise performance, the gain occurs at the output so all intermediate transistors contribute to the noise along with the input transistors. (Some first stage gain can be achieved if R A and R B are greater than g m or g m2. ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 I 3 R R 2 M8 M2 M0 I 6 M9 I7 M Fig Lecture 40 Simple Op Amps (2//02) Page 408 SmallSignal Analysis of the Folded Cascode Op Amp Model: g m6 v gs6 Recalling what we R A learned about the i 0 resistance looking into g m r 2 r the source of the ds r v gs6 ds6 ds4 R 2 g m0 cascode transistor; R B g m7 v gs7 g m2 r 2 r ds2 r v gs7 ds7 ds5 i 0 i 7 R II Fig R A = r ds6r 2 (/g m0 ) g m6 r gs6 g and R m6 B = r ds7 R II R II g m7 r ds7 g m7 r where R ds7 II g m9 r ds9 r ds The smallsignal voltage transfer function can be found as follows. The current i 0 is written as i 0 = g m(r ds r ds4 ) g m 2[R A (r ds r ds4 )] 2 and the current i 7 can be expressed as g m2 (r ds2 r ds5 ) g m2 g m2 i 7 = 2 R = II g m7 r (r ds7 ds2 r ds5 ) 2 R II(g ds2 g ds5 ) = 2(k) where k = R II(g ds2 g ds4 ) g m7 r ds7 g m7 r ds7 The output voltage,, is equal to the sum of i 7 and i 0 flowing through R out. Thus, = g m 2 g m2 2(k) R out = 2k 22k g mir out ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

5 Lecture 40 Simple Op Amps (2//02) Page 409 Frequency Response of the Folded Cascode Op Amp The frequency response of the folded cascode op amp is determined primarily by the output pole which is given as p out = R out C out where C out is all the capacitance connected from the output of the op amp to ground. All other poles must be greater than GB = g m /C out. The approximate expressions for each pole is.) Pole at node A: p A /R A C A 2.) Pole at node B: p B /R B C B 3.) Pole at drain of : p 6 (R 2 /g m0 )C 6 4.) Pole at source of M8: p 8 g m8 /C 8 5.) Pole at source of M9: p 9 g m9 /C 9 6.) Pole at gate of M0: p 0 g m0 /C 0 where the approximate expressions are found by the reciprocal product of the resistance and parasitic capacitance seen to ground from a given node. One might feel that because R B is approximately r ds that this pole might be too small. However, at frequencies where this pole has influence, C out, causes R out to be much smaller making p B also nondominant. ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 40 Simple Op Amps (2//02) Page 400 Example Folded Cascode, CMOS Op Amp Assume that all g mn = g mp = 00µS, r dsn = 2MΩ, r dsp = MΩ, and = 0pF. Find all of the smallsignal performance values for the foldedcascode op amp. R II = 0.4GΩ, R A = 0kΩ, and R B = 4MΩ k = 0.4x0 9(0.3x06) 00 = v = in 22.2 (00)(57.43) = 4,354V/V R out = R II [g m7 r ds7 (r ds5 r ds2 )] = 400MΩ [(00)(0.667MΩ)] = 57.43MΩ p out = R out C = out 57.43MΩ 0pF =,750 rads/sec. 278Hz GB =.2MHz Comments on the Folded Cascode, CMOS Op Amp: Good PSRR Good ICMR Self compensated Can cascade an output stage to get extremely high gain with lower output resistance (use Miller compensation in this case) Need first stage gain for good noise performance Widely used in telecommunication circuits where large dynamic range is required ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

6 Lecture 40 Simple Op Amps (2//02) Page 40 SIMPLE TWOSTAGE BJT OP AMPS BJT TwoStage Op Amp Circuit: DC Conditions: = I bias, Q8 I 3 I 4 Q6 I Bias Q3 Q4 I 6 I I 2 v OUT Q Q2 v IN I Q5 7 x x xn Fig I = I 2 = 0.5 = 0.5I bias, = I 6 = ni Bias V icm (max) = V EB3 V CE (sat) V BE V icm (min) = V CE5 (sat) V BE V out (max) = V EC6 (sat) V out (min) = V CE7 (sat) Notice that the output stage is class A I sink = and I source = β F ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 40 Simple Op Amps (2//02) Page 402 TwoStage BJT Op Amp Continued Small Signal Performance: Assuming differential mode operation, we can write the smallsignal model as, where, R = g m 2 R C v g m2 2 g m4 v R 2 C v2 R 3 C 3 2 gm6 v 2 Fig g m3 r π3 r π4 r o3 g m3 R 2 = r π6 r o2 r o4 r π6 and R 3 = r o6 r o7 C = C π3 C π4 s s3 C 2 = C π6 s2 s4 and C 3 = s6 s7 Note that we have ignored the basecollector capacitors, C µ, except for, which is called. Assuming the pole due to C is much greater than the poles due to C 2 and C 3 gives g m R 2 C v2 R 3 C 3 2 gm6 v 2 Fig. 400 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

7 Lecture 40 Simple Op Amps (2//02) Page 403 TwoStage BJT Op Amp Continued Summary of the small signal performance: Midband performance A o = g mi g mii R I R II g m g m6 r π6 (r o6 r o7 ) = g m βf6(r o6 r o7 ), R out = r o6 r o7, R in = 2r π Roots Zero = g mii = g m6 Poles at p g mii R I R II C = c g m6 r π6 (r o6 r o7 )C = g m c A o C and p g mii g m6 c 2 C II Assume that βf =00, g m =ms, g m6 =0mS, r o6 =r o7 =0.5MΩ, =5pF and =0pF: A o =(ms)(00)( 250kΩ)=25,000V/V, R in 2(βF/g m )2(00kΩ)=200kΩ, R out =250kΩ Zero = 0mS 5pF = 2x0 9 rads/sec jω or 38.3MHz, 8x03 ms p = (25,000)5pF = 2x0 8 σ 09 2x09 Fig ,000 = 8000 rads/sec or 273Hz, and p 2 = 0mS/0pF = 09 rads/sec or 59.5MHz ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 40 Simple Op Amps (2//02) Page 404 Slew Rate of the TwoStage BJT Op Amp Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as I lim = C dv C dt where v C is the voltage across the capacitor C. >>0 Q3 Q Q4 Q5 Q2 Positive Slew Rate I5 Assume a virtural ground Q6 I 6 I CL <<0 Fig. 402 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Q3 Q Q4 Q5 Q2 Negative Slew Rate Assume a virtural ground Q6 I 6 =0 ICL SR = min I 5 C, I 6 c C = L C because I c 6 >> SR = min C, c C = L C if I c 7 >>. Therefore, if is not too large and if is significantly greater than, then the slew rate of the twostage op amp should be, SR =

8 Lecture 40 Simple Op Amps (2//02) Page 405 FoldedCascode BJT Op Amp Circuit Q3 V Bias I C3 i C0 Q0 Q i C V BE V CE (sat) i C0 Q0 Q i C Q Q2 Q8 i C i C2 Q6 V Bias Q9 i out Q8 Q6 Q9 i out Fig. 403 V Bias I C4 Q4 Q5 Simplified circuit I C5 V BE V CE (sat) Biasing details of the output DC Conditions: I 3 = I bias, I = I 2 = 0.5 = 0.5I bias, I 4 = = ki Bias, I 0 = I = ki Bias 0.5I bias (k>) V icm (max) = V CE3 (sat)v EB V icm (min) = V CE4 (sat)v EC (sat)v BE V out (max) = V EC9 (sat)v EC (sat) V out (min) = V CE5 (sat)v CE7 (sat) Notice that the output stage is pushpull I sink and I source are limited by the base current. ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 V BE Q4 R A I C4 Q5 RB I C5 Lecture 40 Simple Op Amps (2//02) Page 406 FoldedCascode BJT Op Amp Continued SmallSignal Analysis: R A g m6 v be6 g m 2 r r π6 r o6 o r v be6 o4 g m0 R B g m7 v be7 i 0 g m2 v r o7 2 be7 r o2 r o5 r π7 where R A /g m6 and R B r o7βpr o /2 g m7 r o7 r π7 2 if r o7 r o i g mr π6 g m 0 2(r π6 R A ) 2 i g m2r π7 g m2 r π7 7 2(r π7 R B ) 2(r π7 0.5r π7 ) = g m2 3 = (i 7 i 0 )βpr out = 5 6 (g mβpr out ) if g m = g m2 i 0 i 7 v βr out o Fig. 404 = 5 6 (g mβpr out ) R out = βpr o [β Ν (r o5 r o2 )] and R in = 2r π Assume that βfn =00, βfp =50, g m = g m2 =ms, r on = MΩ, and r op = 0. 5MΩ: = 4,285V/V R out = MΩ and R in = 00kΩ ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

9 Lecture 40 Simple Op Amps (2//02) Page 407 FoldedCascode BJT Op Amp Continued Frequency response includes only dominant pole at the output (selfcompensation), p = R out There are other poles but we shall assume that they are less than GB If = 25pF, then p = 2800 rads/sec. or 446Hz GB = 6.37 MHz Checking some of the nondominant poles gives: p A = R A C A = g m6 C A 59MHz if C A = pf (the capacitance to ac ground at the emitter of Q6) 2 p B = R B C B = r π7 C B 6.37MHz if C B = pf (the capacitance to ac ground at the emitter of ) This indicates that for small capacitive 60 loads, this op amp will suffer from 40 higher poles with respect to phase 20 margin. Capacitive loads greater than 0 25pF, will have better stability (and less 20 GB). 40 VdB(3) Frequency (Hz) Fig. 405 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 40 Simple Op Amps (2//02) Page 408 SUMMARY Two stage op amp gives reasonably robust performance as an onchip op amp DC balance conditions insure proper mirroring and all transistors in saturation Slew rate of the twostage op amp is / Folded cascode op amp offers wider input common voltage range Folded cascode op amp is a selfcompensated op amp because the dominant pole at the output and proportional to the load capacitor ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

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