Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1

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1 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 322 AUTOZEROING Principle of Autozeroing Use the comparator as an op amp to sample the dc input offset voltage and cancel the offset during operation. V OS Ideal Comparator V OS Ideal Comparator C AZ V OS V OS V OS C AZ Ideal Comparator Model of Comparator. Autozero Cycle Comparison Cycle Fig Comments: The comparator must be stable in the unitygain mode (selfcompensating comparators are ideal, the twostage comparator would require compensation to be switched in during the autozero cycle.) Complete offset cancellation is limited by charge injection

2 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 323 Differential Implementation of Autozeroed Comparators Ideal V v Comparator OS OUT = V OS φ 2 V OS Comparator during phase φ V 2 OS C AZ v IN V OS V OS Differential Autozeroed Comparator Comparator during φ 2 phase Fig Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 324 SingleEnded Autozeroed Comparators Noninverting: φ 2 φ 2 C AZ Inverting: Fig C AZ φ 2 Fig Comment on autozeroing: Need to be careful about noise that gets sampled onto the autozeroing capacitor and is present on the comparison phase of the process.

3 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 325 HYSTERESIS Influence of Input Noise on the Comparator Comparator without hysteresis: Comparator threshold v in t v out t Comparator with hysteresis: V TRP V TRP v in Fig. 8.46A t v out Fig. 8.46B t Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 326 Use of Hysteresis for Comparators in a Noisy Environment Transfer curve of a comparator with hysteresis: V TRP V TRP V TRP R 1 (V R OH ) V TRP 2 Counterclockwise Bistable Clockwise Bistable Fig Hysteresis is achieved by the use of positive feedback Externally Internally

4 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 327 Noninverting Comparator using External Positive Feedback Circuit: Upper Trip Point: Fig Assume that =, the upper trip point occurs when, = R 1 R 1 R 1 V TRP V TRP = R 1 Lower Trip Point: Assume that =, the lower trip point occurs when, = R 1 R 1 R 1 R 1 (V R 1 R OH ) v 2 OUT R 1 V OH R 1 V TRP V TRP = R 1 Width of the bistable characteristic: Vin = VTRP VTRP = R1 VOHVOL R2 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 328 Inverting Comparator using External Positive Feedback Circuit: R 1 R 1 R 1 R 1 (V R 1 R OH ) 2 R 1 R 1 Upper Trip Point: Fig R 1 = V TRP = R 1 Lower Trip Point: R 1 = V TRP = R 1 Width of the bistable characteristic: Vin = VTRP VTRP = R1 R1R2 VOHVOL

5 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 329 Horizontal Shifting of the CCW Bistable Characteristic Circuit: Upper Trip Point: V REF = R 1 R 1 R 1 V TRP V TRP = R 1 V REF R 1 Lower Trip Point: V REF = R 1 R 1 R V 2 OH R 1 R V 2 TRP V TRP = R 1 R V 2 REF R 1 R V 2 OH Shifting Factor: ± R 1 V REF R 1 (V V R OH ) 2 R OH 2 R R 1 1 R V REF 2 R 1 V REF R 1 R V 2 OL Fig Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 Horizontal Shifting of the CW Bistable Characteristic Circuit: Upper Trip Point: V REF R 1 R 1 = V TRP = R 1 R 1 V REF Lower Trip Point: = V TRP = R 1 R 1 V REF Shifting Factor: ± R 1 V REF R 1 R 1 ( ) R R 1 R VREF 2 R 1 R 1 R R R 1 Fig. 8.41

6 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3211 Example 321 Design of an Inverting Comparator with Hysteresis Use the inverting bistable to design a highgain, openloop comparator having an upper trip point of 1V and a lower trip point of V if = 2V and = 2V. Solution Putting the values of this example into the above relationships gives and 1 = R 1 R 1 2 = R 1 R 1 (2) R 1 V REF R 1 V REF Solving these two equations gives 3R 1 = and V REF = (2/3)V. Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3212 Hysteresis using Internal Positive Feedback Simple comparator with internal positive feedback: I Bias M3 M6 M7 M4 v o1 v o2 v i1 v i2 M8 V SS Fig

7 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3213 Internal Positive Feedback Upper Trip Point Assume that the gate of is on ground and the input to is much smaller than zero. The resulting circuit is: on, off M3 on, M6 on (active), M4 and M7 off. v o2 is high. M6 wants to source the current i 6 = W 6/L 6 W 3 /L 3 i 1 As v in begins to increase towards the trip point, the I 5 current flow through increases. When i 2 = i 6, Fig A the upper trip point will occur. V SS i 5 = i 1 i 2 = i 3 i 6 = i 3 W 6 /L 6 W 3 /L 3 i 3 = i 3 1 W 6/L 6 i 5 W 3 /L 3 i 1 = i 3 = 1[(W 6 /L 6 )/(W 3 /L 3 )] Also, i 2 = i 5 i 1 = i 5 i 3 Knowing i 1 and i 2 allows the calculation of v GS1 and v GS2 which gives 2i 2 2i 1 V TRP = v GS2 v GS1 = 2 V T2 1 V T1 v o1 M3 M6 i 1 = i 3 M7 M4 i 2 = i 6 vo2 v in Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3214 Internal Positive Feedback Lower Trip Point Assume that the gate of is on ground and the input to is much greater than zero. The resulting circuit is: on, off M4 and M7 on, M3 and M6 off. v o1 is high. M7 wants to source the current i 7 = W 7/L 7 W 4 /L 4 i 2 v o1 M3 M6 M7 M4 v i1 i 1 = i 7 i 2 = i 4 vo2 v i1 v i As v in begins to decrease towards the trip point, the current flow through increases. When i 1 = i 7, the V Fig B SS lower trip point will occur. i 5 = i 1 i 2 = i 7 i 4 = W 7 /L 7 W 4 /L 4 i 4 i 4 = i 4 1 W 7/L 7 i 5 W 4 /L i 4 2 = i 4 = 1[(W 7 /L 7 )/(W 4 /L 4 )] Also, i 1 = i 5 i 2 = i 5 i 4 Knowing i 1 and i 2 allows the calculation of v GS1 and v GS2 which gives 2i 2 V TRP = v GS2 v GS1 = 2 V 2i 1 T2 1 V T1 I 5

8 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3215 Example 322 Calculation of Trip Voltages for a Comparator with Hysteresis Consider the circuit shown. If K N = 11μA/V 2, K P = 5μA/V2, and V TN = V TP =.7V, calculate the positive and negative threshold points if the device lengths are all 1 μm and the widths are given as: W 1 = W 2 = W 6 = W 7 = 1 μm and W 3 = W 4 = 2 μm. The gate of is tied to ground and the input is the gate of. The current, i 5 = 2 μa Solution To calculate the positive trip point, assume that the input has been negative and is heading positive. i 6 = (W/L) 6 (W/L) 3 i 3 = (5/1)(i 3 ) i 3 = i 2 = i 5 i 1 = = μa v GS1 = 2i 1 v GS2 = 2i 2 1/2 2 VT2 = /2 (5)11.7 =.946V V TRP v GS2 v GS1 = =.136V I Bias M3 M6 M7 M4 v o1 v o2 i 5 1[(W/L) 6 /(W/L) 3 ] = i 2μA 1 = 15 = 3.33 μa /2 1 VT1 = (5)11 1/2.7 =.81V M8 v i1 V SS v i2 Fig Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3216 Example 322 Continued Determining the negative trip point, similar analysis yields i 4 = 3.33 μa i 1 = μa v GS2 =.81V v GS1 =.946V V TRP v GS2 v GS1 = =.136V PSPICE simulation results of this circuit are shown below v o2 1.8 (volts) v in (volts) Fig

9 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3217 Complete Comparator with Internal Hysteresis I Bias M3 M6 M7 M4 M9 M8 v i1 vi2 v out 1 M8 V SS Fig Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3218 Schmitt Trigger The Schmitt trigger is a circuit that has better defined switching points. Consider the following circuit: v in M4 M3 M6 v out Fig How does this circuit work? Assume the input voltage, v in, is low and the output voltage, v out, is high. M3, M4 and are on and, and M6 are off. When v in is increased from zero, starts to turn on causing M3 to start turning off. Positive feedback causes to turn on further and eventually both and are on and the output is at zero. The upper switching point, V TRP is found as follows: When v in is low, the voltage at the source of (M3) is v S2 = V TN3 V TRP = v in when turns on given as V TRP = V TN2 v S2 V TRP occurs when the input voltage causes the currents in M3 and to be equal.

10 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3219 Schmitt Trigger Continued Thus, i D1 = 1 ( V TRP V TN1 ) 2 = 3 ( v S2 V TN3 ) 2 = i D3 which can be written as, assuming that V TN2 = V TN3, 1 ( V TRP V TN1 ) 2 = 3 ( V TRP ) 2 V TRP = V TN1 3 / / 1 The switching point, V TRP is found in a similar manner and is: 5 ( V TRP V TP5 ) 2 = 6 ( V TRP ) 2 V TRP = The bistable characteristic is, v out 5 / 6 ( V TP5 ) 1 5 / 6 v in V TRP V TRP Fig Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 322 SIMPLE LATCHES Regenerative Comparators Regenerative comparators use positive feedback to accomplish the comparison of two signals. es can have a faster switching speed than the previous comparators. NMOS and PMOS latch: I 1 I 2 v o1 vo2 v o1 vo2 I 1 I 2 NMOS latch PMOS latch Fig. 8.53

11 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3221 Operating Modes of the The latch has two modes of operation enable or latch and Enable (enable_bar) or (latch_bar). 1.) During the Enable_bar, the latch is turned off (currents are removed) and the unknown inputs are applied to it. The parasitic capacitance at the latch nodes hold the unknown voltage. 2.) During Enable, the latch is turned on, and the positive feedback acts on the applied inputs and causes one side of the latch to go high and the other side to go low. Enable_bar: I 1 I 2 Enable V o1ʼ Enable V o2ʼ V Enable Enable o1ʼ V o2ʼ I 1 I 2 NMOS latch PMOS latch The inputs are initially applied to the outputs of the latch. V o1 = initial input applied to v o Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3222 Step Response of a (Enable) Circuit: R i and C i are the resistance and capacitance seen to ground from the ith transistor. I 1 I 2 v o2 C 1 v o1 Vo2 V g o1 ' m1v o2 R 1 s Nodal equations: g m1 V o2 G 1 V o1 sc 1 V o1 V o1 s = g m1 V o2 G 1 V o1 sc 1 V o1 C 1 V o1 = g m2 V o1 G 2 V o2 sc 2 V o2 V o2 s = g m2 V o1 G 2 V o2 sc 2 V o2 C 2 V o2 = Solving for V o1 and V o2 gives, V o1 g m2 V o1 C 2 V o2 ' s V o2 Fig V o1 = R 1 C 1 sr 1 C 1 1 V o1 g m1r 1 sr 1 C 1 1 V 1 o2 = s 1 1 V o1 g m1r 1 s 1 1 V o2 C 2 V o2 = s C 2 1 V o2 g m2 s C 2 1 V 2 o1 = s 2 1 V o2 g m2 s 2 1 V o1 Defining the output, V o, and input, V i, as V o = V o2 V o1 and V i = V o2 V o1

12 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3223 Step Response of the Continued Solving for V o gives, V o = V o2 V o1 = s1 V i g mr s1 V o or V i V i V o = s(1g m R) = 1g m R V i s = 1g m R 1 s 1 where = 1g m R Taking the inverse Laplace transform gives v o (t) = V i e t/ = V i e t(1g mr) / e g mrt/v i, if g m R >>1. Define the latch time constant as if C C gs. L = g m R = C g m =.67WLC ox 2K (W/L)I =.67C ox WL 3 2K I Vout(t) = e t/ L Vi Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3224 Step Response of a Continued Normalize the output voltage by ( ) to get V out (t) V i V = e t/ L OL which is plotted as, The propagation delay time is t p = L ln 2V i ΔV i V.5 OH.6 ΔV out Note that the larger the V i, the faster the response. 1 2 t τ L Fig. 8.55

13 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3225 Example 323 Time Domain Characteristics of a. Find the propagation time delay for the NMOS if the W/L of the latch transistors is 5μm/.5μm and the latch dc current is 1μA when V i =.1( ) and V i =.1( ). Solution The transconductance of the latch transistors is g m = = 155μS The output conductance is.6μs which gives g m R of 93V/V. Since g m R is greater than 1, we can use the above results. Therefore the latch time constant is found as L =.67C ox WL3 2K I =.67(6.6x1 4) (5.5)x x16 1x16 =.131ns Since the propagation time delay is the time when the output is.5( ), then using the above results or Fig we find for V i =.1( ) that t p = 3.91 L =.512ns and for V i =.1( ) that t p = 1.61 L =.211ns. Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3226 Comparator using a with a BuiltIn Reference How does it operate? 1.) Devices in shaded region operate in the triode region. /Reset 2.) When the latch/reset goes high, the upper crosscoupled inverterlatch regenerates. The drain currents of and M6 are steered to obtain a final state determined by the mismatch between the R 1 and resistances. 1 R 1 = K N W 1 L (v in V T ) W 2 L (V REF V T ) and 1 = K N W 1 L (v in V T ) W 2 L (V REF V T ) 3.) The input voltage which causes R 1 = is v in (threshold) = (W 2 /W 1 )V REF W 2 /W 1 = 1/4 generates a threshold of ±.25V REF. Performance 2Ms/s & 2μW M9 M7 M8 M6 /Rese M3 v out v out M4 R 1 v in v in V REF V REF φ1 Fig T.B. Cho and P.R. Gray, A 1b, 2Msamples/s, 35mW pipeline A/D Converter, IEEE J. SolidState Circuits, vol. 3, no. 3, pp , March 1995.

14 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3227 Simple, Low Power ed Comparator M9 M7 M8 M6 φ1 M3 v out v out M4 v in v in Dissipated 5μW when clocked at 2MHz. Selfreferenced Fig A. Coban, 1.5V, 1mW, 98dB DeltaSigma ADC, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3228 TailReferenced The previous two latches experience poor input offset voltage characteristics because the input devices are working in the linear region during the latch phase. The latch below keeps the input devices in the saturation region. The resulting larger gain of the input devices reduces the input offset voltage as shown. The input offset voltage of the tail referenced latch is compared between two latches with the referenced latch for 1 samples. The xaxis is the deviation from the mean of the first latch and the y axis is the deviation of the mean of the second latch. v out v in V ref V ref v out v in All transistors are 3.5μm/.4μm excep and

15 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3229 CMOS Circuit: φ M6 M8 V REF M3 M4 v out v in M7 vout φ Input offset voltage distribution: Number of Samples Fig ;;; ; ;;; σ = 5.65 L = 1.2μm (.6μm Process) Input offset voltage (mv) Fig Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 323 CMOS with Different Inputs and Outputs Inputs _bar M6 M7 Outputs M3 M When _bar is high,, M6 and M7 are off and the latch is disabled and the outputs are shorted together. When _bar is low, the input voltages stored at the sources of and will cause one of the latch outputs to be high and the other to be low. The source of and that is higher will have a larger sourcegate voltage resulting in a larger transconductance and more gain than the other transistor.

16 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3231 Metastability Metastability is the condition where the latch cannot make a decision in the time allocated. Normally due to the fact that the input is small (within the input resolution range). Metastability can be improved (reduced) by increasing the gain of the comparator by preceding it with an amplifier to keep the signal input to the latch as large as possible under all conditions. The preamplifier also reduced the input offset voltage. _bar Inputs Comparator Inputs Outputs V NB1 Preamplifier Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 3232 SUMMARY Discretetime comparators must work with clocks Switched capacitor comparators use op amps to transfer charge and autozero Regenerative comparators (latches) use positive feedback The propagation delay of the regenerative comparator is slow at the beginning and speeds up rapidly as time increases The highest speed comparators will use a combination of openloop comparators and latches