Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
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1 Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace the NMOS symbol in Fig. 4. with the one for an NMOS transistor in Fig. 3. of pp. 73 with the bulk connected to ground (assumed to be the lowest potential). 7 Fig. 4.5, replace symbol with the NMOS symbol on pp Fig. 4.6, replace symbol with the NMOS symbol on pp Fig. 4.3, replace symbol with the NMOS symbol on pp Eq. (4.3), no / sign in numerators 33 Solution part to Example 4.33: delete in when calculating W/L 33 Solution part to Example 4.33: when calculating W/L 34 Line 3 from the bottom, delete is greater thanv T 34 Eq. (4.4): v DS v DS 38 Line of Example 4.4: Change the values from W 5 ± 0.05μm and W 0 ± 0.05μm W 5 ± 0.μm and W 0 ± 0.μm 38 Second and fourth lines of the solution: W 5 ± 0.05μm W 5 ± 0.μm and W 0 ± 0.05μm W 0 ± 0.μm 38 Solution part to Example 4.4, line 6: W W 5 ± 0.06 W 0 0. W 5 ± 0. 4 ± (0./5) 4 ± 0. 0 ± ± 0. 0 ± (±0.03) 38 Last line of Ex. 4.4: ratio error is.5% ratio error is 0.75% 46 Eq. (4.50): V REF V GS R R V REF V GS R R 55 Eq. (4.60): V BE V G0 T 0 ( )k q V BE0 V G0 T ( )k 0 q 56 Eq. (4.6): V BE V BE 7 Eq. (5.5): C out C bd C bd C gs C L C out C bd C bd C gs C L 7 Line 3: voltage gain is.9 V/V. voltage gain is.098 V/V. 75 Eq. For v OUT (min): " " 78 Eq. (5.3): e out e eq 88 Fig. 5.8(a): The VCCS in parallel with r ds should be g m v gs instead of
2 Errata nd Ed. (0/9/07) Page g m v gs. 88 Fig. 5.8(b): The VCCS in parallel with the i 3 VCCS should be g m v gs instead of g m v gs. 97 Last line: P 0.5V P 0.05V 98 First eq. in step 5.): Should be V DS (sat) V IC (min) V SS V GS μA 0μA/V (8.4) Last eq. on page: Should be W 5 I 5 L 5 K N ' V DS (sat) rd line from bottom: giving a smaller W 5 /L 5. to allow for a variation in V TN. 98 nd line from bottom: W /L (W /L ) 5, which gives W 5 /L 5.3. W /L (W /L ) 40, which gives W 5 /L Last line:. V/V 47.4 V/V First eq. on this page: 50A V 50A V Line between st and nd eqs.: V DS (sat) 0.7 V. V DS (sat) 0.5 V Second eq. on this page: " " Third eq. on this page: 0.8 V 0.7 V.0 V 0.5 V 5 Fig. 5.57(a): The bulk VCCS for M should be g m v bs instead of g m v gs. 5 Fig. 5.57(a): The VCCS for M, g m v gs should be pointing upward. 5 Fig. 5.57(a): The bulk VCCS for M should be g m v bs instead of g m v gs. 5 Fig. 5.57(b): The fourth VCCS from the left should be g m v in instead of g m v in. 56 Fig. 6.6: Replace GB with 0dB frequency 66 Fig. 6.6(a): M4 M. 68 Fig. 6.8(c): Corrected figure is shown. A is replaced by A. V i. 68 Eq. (6.56) should be: V out (s) V in (s) AC c C c C II s g mii /AC c s /[R II (C c C II )] A C c g mii V i 74 Table 6.3, last line: The downward arrrow should be upward. 74 Table 6.3, entry 3.): Delete the equation I 5 0 DD V SS T s C II R II Vout
3 Errata nd Ed. (0/9/07) Page 3 74 Last line: S S g m K 'I 5 S S g m K 'I 5 88 Fig. 6.4c: Replace g ds V dd of the leftmost controlled source with g ds V dd g m V out Eq. (6.5): R A r ds6 R g m6 r gs6 g m0 g m6 r ds6 r ds6 R g R m6 A g m6 g m v in g m v in Eq. (6.56): R 9 (g ds g ds5 g m7 r R 9 (g ds g ds5 ) ds7 g m7 r ds7 Eq. (6.57): k R 9 (g ds g ds4 ) R 9 (g ds g ds5 ) g m7 r k ds7 g m7 r ds7 Eq. (6.53): p 6 p 6 R g C m0 6 R g C m Line 9 from the bottom: Figure 6.58 Figure I 5 8I 7 Table 6.53, Step 3, third column: S 5 V, S 7 SD5 V SD S 5 I 5 V SD5, S 7 I 7 V SD7 V DD V out (min) V DD V out (max) Table 6.53, Step 3, fourth column: Table 6.53, Step 4: S 8I K N V DS, S 9 8I 9 K N V DS9 S I K N V DS, S 9 I 9 K N V DS9 307 Table 6.53, Step 5: V SD4 (sat)/i 4 V SD3 (sat)/i 307 I 4 I 4 Table 6.53: Step 8: (V DD V in (max)v T ) (V DD V in (max)v T ) μA Third Eq: S 6 S 7 S 3 50μA/V (0.5V) μA S 6 S 7 S 3 50μA/V (0.5V) x0 6 Sixth Eq: 0x
4 Errata nd Ed. (0/9/07) Page x0 6 0x Last Eq: S 4 S 5 I 4 [V DD V in (max)v T ] S 4 S 5 I 4 [V DD V in (max)v T ] 33 Fig. 6.67(b): The polarity of the upper V cm source should be reversed. 33 Fig. 6.67(b): Replace the lower controlled source designation of ±A c V cm with ± A c (V V ) 30 Fourth line of Table 6.63: 6.0 U should be 6.0U 3 Caption of Fig. 6.67: Input commonnode should be Input common mode 343 Prob. 6.30, 5 th line: Delete positive and 343 Fig. P6.30: Change the power supplies to ±.5V and increase the W/L value of M6 to 00/. 344 Prob. 6.30: Add sentence Assume the parameters of the MOSFETs are given in Table Eq. (7.8): R out (g ds6 g ds7 ) g m g (g m4 m6 g m8 )R o R out (g ds6 g ds7 ) g m g (g m4 m6 g m8 )R o 36 Eq. (7.): Replace with 363 First line:..that R L is smaller than r ds...that the load reflected from the emitter to base of Q0 is negligible with respect to r Last line: 469μS 300μS 364 g m9 N st Eq.: g mbs F V BS μS g mbs9 g m9 N F V BS μS μS nd Eq.: A MOS 469μS57.μS4μS5μS V/V 300μS A MOS 300μS36.5μS4μS5μS V/V th Eq.: A vd (0) (7777)(0.8765)(0.95) 6483 V/V
5 Errata nd Ed. (0/9/07) Page 5 A vd (0) (7777)(0.8683)(0.95) 64 V/V 387 st complete paragraph: Replace this entire paragraph with the following: The input common mode range of the differentialout op amps may appear to be better because of the current source loads (M3 and M4 of Fig. 7.33). However, the upper input common mode range becomes restricted by M6 and M7 of Fig For example, in Fig. 7.33, the upper input common mode range is V DD V T where it is V DD V T. for the foldedcascode differential output op amp of Fig Eq. (7.34): (v sg v gs4 ) (v gs v sg4 ) 394 Line after Eq. (7.45): g m /C g m /C c Eq. (7.46): GB I D (n kt/q)c GB I D (n kt/q)c c Eq. (7.47): SR I D5 C I D C SR I D5 C c I D C c rd line from bottom: Figure 7.74 Figure Line : M5 to M4 M6 to M4 and M7 equals M6 M7 equals M9 399 I I st Eq.: V ds (sat) K N (W /L ) V ds (sat) K N (W /L ) 404 Eq. (7.53): g m6 R II g m6 R II 405 Line following Eq. (7.58): Fig. 7.4 Fig Line 7 including eqs.: 0.0 μ(v rms ) 0.0 μ(v rms ) 40 Line 3 ( lines after Eq. 7.60): above V onn should be above V onp 434 Prob. 7.0, 3 rd line: Example 7. Example Prob. 7.0: Add the sentence, Assume C 0 pf and C μ pf. 434 Prob. 7.0: Replace Example 7. with Example Prob. 7.4, nd and 3 rd line: all transistor widths are transistors M through M widths are 436 Prob. 7.4, 5 th line:..the correct bias voltage for M0 and M the W/L values of M through M5 436 Prob. 7.4, last line: n p.5 and n n.5. n p.5, n n.5 and V t 6mV. 436 Prob. 7.55, nd line: of a over a 44 Fig. 8.5, st line after Fig: V OH for (v P v N ) > 0 V OH for (v P v N ) > V IH 44 Fig. 8.5, 3 rd line after Fig: V OL for (v P v N ) < 0 V OL for (v P v N ) > V IL 444 Next to last line:.5v should be.5v. 446 (g ds g ds4 ) Eq. (8.4a): p C I (g ds g ds4 ) p C I 446 Eq. (8.4a): p C II (g ds g ds4 ) p (g ds6 g ds7 ) C II
6 Errata nd Ed. (0/9/07) Page A v (0) A v (0) Eq. (8.5): A v (s) s p s p A v (s) s p s p g ds g ds4 st eq.: p C 5x06 ( ) I 0.x0 6.75x0 6 (.074MHz) g ds g ds4 p C 5x06 ( ) I 0.x0 6.75x0 6 (.074MHz) g ds6 g ds7 nd eq: p C 95x06 ( ) II 5x0.7x0 6 (0.670MHz) g ds6 g ds7 p C 95x06 ( ) II 5x0.7x0 6 (0.670MHz) Eq. (8.6): v out (t) A v (0)V in p e tp p p p e tp p p v out (t) A v (0)V in p e tp p p p e tp p p Eq. (8.): t n tp t t n tp t Eq. (8.): v out (t n ) p e t n n p e t n e t n t n e t n v out (t n ) e tp tp e tp e t n t n e t n 448 Line after Eq. (8.): Delete where p is assumed to be unity. 448 Fig. 8.: Normalized Time (t n tp t/ ) Normalized Time (t n tp ) 454 Eq. at bottom of page: V V 455 Line : V TRP V V TRP V 455 Line 3: V.5 V.465 V V SG6.035 V. V.5 V.304 V V SG6.96 V. 455 Line 5: t fo 0.pF.035V 30μA 6.9 ns t fo 0.pF.96V 30μA 8 ns 455 Line 9:.465 V.304 V 455 Line 3:.465 V.304 V 455 Line 4: 0.3 V. 0.5 V and.7 V.348 V Line 5: I 6 (V SG6 V TP ) (.7 0.7),34μA 6 I 6 (V SG6 V TP ) ( ),580μA
7 Errata nd Ed. (0/9/07) Page Line 9: t rout 5pF.5V,34μA 5.3ns t rout 5pF.5V,580μA34μA 5.3ns 455 Line :. ns 3.3 ns 455 Last line: t ro 0.pF.465V(.5) 30μA 6.43ns t ro 0.pF.304V(.000) 30μA 5.4ns 456 Line 3: ns ns. 456 Line 5: about ns. about 4 ns. 456 Fig. 8.7: V TRP6.465V V TRP6.304V Also, lower the dashed line. 457 V OH V OL V OH V OL Table 8., step 5: A v (0) V in (min) A v (0) V in (min) 459 Tab;e 8.3, step 6: A v (0) V OH V OL V in (min) A v (0) V OH V OL V in (min) 465 Fig. 8.4(b): The polarity of the voltage on C AZ should be reversed. 468 Fig. 8.47: V TRP R V OL R and V TRP R V OH R Fig. 8.48: R R R V REF R R R V REF Eq. (8.40): V TRP R R R R V REF R V OL 470 V TRP R R R R V REF R V OL Eq. (8.4): V TRP R R R R V REF R V OH V TRP R R R R V REF R V OH 470 First line after Eq. (8.4): (R R )/R (R R )/R 470 Eq. (8.43) and Eq. (8.44): R R V REF R R V REF 470 First line after Eq. (8.44): R /(R R ) R /(R R ) 470 R R Fig. 8.40: R R V REF R R V REF 47 st and nd equations: R R R R V REF R R V REF 47 Last line of Ex. 8.4: V REF V V REF V
8 Errata nd Ed. (0/9/07) Page Eq. (8.55): sc V o V o s sc V o V o s 480 Ex. 8.5, line 3: V i 0.0V in (min) and V i 0.V in (min). V i 0.0(V OH V OL ) and V i 0.(V OH V OL ) rd line from bottom: given a latch gain of 59. V/V. gives a latch gain of 370 V/V. 48 Last eq. on page should be: L 0.67C ox WL 3 K'I 0.67(4.7x04 ) (0 )x0 4 0x0 6 0x ns 48 First line: t 4.6 L 496 ns t 4.6 L 0.55 ns 48 Second line: that t.3 L 84 ns. that t.3 L 0.58 ns. 48 Third line: and is 74 ns and 4 ns and is ns and 0.80 ns 485 Fig. 8.64: The pins FB and Reset associated with M should be reversed. 486 Fig Disconnect the line connecting the gatedrains of M3 and M4 489 Prob. 8.3,3 rd line: what is the propagation what is the slew rate limited propagation 50 Eq. (9.34): v(n n o )T z not V(z) v(n n o )T z no V(z) 50 Eq. (9.36): V (z) o C C z C C z V(z) o V (z) o C C z C C z V(z) o 543 Line 9: EODD EVEN 543 Line 0: EVEN EODD 549 Line : Eq. (9.5) Eq. (9.5) 55 Line 3: Eq. (9.64) Eq. (9.63) 554 Ex. 9.6, nd line of solution: /3.83. / Ex. 9.6, nd line of solution: /5.9. / PB SB Eq. (9.74): n SB n PB 564 Caption for Fig. 9.73: for. for. 565 Title for Table 9.7: for. for rd and 4 th line after Eq. (9.79): ( 0.033) ( 0.56) 57 nd line: T PB n f c PB T n f c Last line: T n PB f c
9 Errata nd Ed. (0/9/07) Page PB T n f c Line : Eq. (9.74): n SW BW SB SB BP PB n SW BW SB SB PB PB 587 Fig. 9.78: The upper input capacitor should be labeled C 607 Prob. 9.74, st line following eq.: to 000 Hz to be 000 Hz 63 Eq. (0.3): v OUT KV REF b b b b N N v OUT KV REF b b b b N N 68 Eq. (0.5): Differential nonlinearity (DNL) cx V s V 00% V cx s V LSBs s Differential nonlinearity (DNL) (V cx V s ) V cx V s V V s s V cx V LSBs s 6 Line 4: ±LSB ±0.5LSB 69 v step (actual) v step (ideal) v step (actual) Eq. (0.5): DNL v step (ideal) v step (ideal) DNL v step (actual) v step (ideal) v step (actual) v step (ideal) v step (ideal) v step (ideal) v step (actual) v step (ideal) LSBs 630 Last line of solution: DNL ± ±0.64 LSBs DNL ± 00 LSBs ± 0.0 LSBs 64 Eq. 0.3 The summation should be i0 through 7 not bi V REF bi V i REF i i0 i0 644 Fig. 0.39: C M C C M C, C M C C M C and C M C C M C th line below Eq. (0.37): K. M.
10 Errata nd Ed. (0/9/07) Page M R Eq. (0.34): INL INL(R) INL(C) R C N C LSBs INL INL(R) INL(C) R K R C N C LSBs rd line after Eq. (0.35): of K of M 646 nd sentence in Ex. 0.34: To minimize the capacitor element spread and the number of resistors, choose M 5 and K 7. To emphasize the accuracy of the capacitors, choose M 7 and K Lines and of Ex. 0.34, Solution: increase the value of M and decrease decrease the value of M and increase 647 Line 3 of Ex. 0.34, Solution: choose K 5 and M 7 choose M 5 and K Eq. (0.64): N out N REF v * in V REF N out N REF v * in V REF 67 Line : than then 675 Eq. (0.78): b b 70 Fig The sign of the output of the integrator (v[nt s ]) returned to the summing junction in the left shaded box should be and not. 70 The correct Fig is shown: x[nt s ] Integrator Delay Integrator Delay Quantizer y[nt s ] Figure 0.96 Sampleddate model of a secondorder ΔΣ modulator. 704 Eq. (0.9): 3 L L M L B 3 L L M L ( B ) 79 Prob. 0.3: if the divisor is 3 and 6. if the divisor is 3 and Fig. P0.37: The vertical resistor connected to the right of the resistor R x, should have the value of R rather than 4R and the 4R between the horizontal resistors R x and 4R should be deleted. 70 Fig. P0.38: The subscripts of the bits, b i, should all be decreased by. I.e. b b 0, b b, etc. 70 Fig. P0.30: The subscripts for b should increase from right to left and not left to right. In addition, a vertical line should be drawn from the left most switch terminal labeled b 0 (old labeling) to the V REF battery. 73 Prob. 0.44, lines 46: If the attenuation factors of 0.5 become 0.55, at what bit does the converter create an error? What is the analog output for this case? Replace with If the attenuation factors of 0.5 become 0.55, what is the analog output for this case?
11 Errata nd Ed. (0/9/07) Page 73 Prob. 0.47, st line: ADC DAC 74 Prob. 0.6, st line: Give a switched For Fig. 0.6, give a switched 75 Prob. 0.7, last line: in part (a)? in part (a) if V REF V. 79 Fig. P0.99: f s f o f s 4f o 753 Ex. B.4, st line of Solution: Eq. (B.40), Eq. (B.34),
Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)
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