Systematic Design of Operational Amplifiers

Transcription

1 Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium Willy Sansen

2 Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other specs: Input range, output range, SR,... Ref.: Sansen : Analog design essentials, Springer 2006 Willy Sansen

3 Single-stage CMOS OTA : GBW M7 V DD A v = r o g m1 2 I B v- 2 M1 3 M2 1 v + v OUT C L BW = if r o2 = r o4 = r o 1 r 2π o (C L +C n1 ) 2 M3 M4 V SS GBW = g m1 2π (C L +C n1 ) Willy Sansen

4 CMOS OTA : Maximum GBW GBW = g m1 g m1 = I B 2π C L V GS1 -V T I B v- v C L + C L GBW max = I B V GS1 -V T 1 2π C L v OUT+ v OUT- 0.2 V I B = 10 µa C L = 1 pf GBW max 10 MHz FOM = GBW.C L = 1000 I B [8] [800] MHzpF/mA Willy Sansen

5 Single stage CMOS OTA : f nd M7 V DD GBW = g m1 2π (C L +C n1 ) I B v- M1 3 M2 v + v OUT f nd = g m3 2π C n2 C n2 2C GS3 + C DB3 + C DB1 2 1 C L 4 C GS3 M3 M4 V SS f nd f T3 4 Willy Sansen

6 Simple CMOS OTA : f nd M5 A v 2x - M1 3 M2 + 0 o 2x f f v OUT -90 o C n2 2 1 M3 M4 f = g m3 nd 2π C n2 f nd 2f nd GBW GBW PM = 90 o - arctan + arctan 85 2 f o nd f nd Willy Sansen

7 Single stage CMOS OTA : Design 1 GBW = 100 MHz for C L = 2 pf Techno: L min = 0.35 µm; K n = 60 µa/v 2 & K p = 30 µa/v 2 I DS? W? L? gm = GBW 2π CL = 1.2 ms VGS-VT = 0.2 V IDS = gm V GS-VT 2 = g m 10 = 0.12 ma W L = IDS K'(VGS-VT)2 =100 Lp =Ln =1 µm GAIN! Wp = 100 µm; Wn = 50 µm Willy Sansen

8 Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other specs: Input range, output range, SR,... Willy Sansen

9 Miller CMOS OTA 5 M7 1 : B M5 V DD Two nodes 1 4 v C c M1 M2 v 4 v OUT with high Impedance 2 1 M6 R L C L cause two poles M3 M4 C n1 split by C c V SS Willy Sansen

10 Miller CMOS OTA : small-signal v - 2 M3 M1 3 M2 1 M4 v + C c C n1 4 v OUT M6 Z L GBW= 1MHz C L = 10 pf R L = 10 kω g m1 = 7.5 µs g o24 = 0.03 µs 1 C c 4 C n1 = 0.37 pf C c = 1 pf g m6 = 246 µs g Lo6 = 20 µs g m1 g o24 C n1 g m6 g Lo6 C Ln4 = 10.2 pf I DS1 = 1.1 µa I DS6 = 25 µa Willy Sansen

11 Miller CMOS OTA : GBW 5 M7 1 : B M5 g m1 A v1 = go24 A v2 = g m6 glo6 v C c M1 M2 v 4 v OUT BW = g o24 2π A v2 C c R L C L g m1 2 M3 1 M4 C n1 M6 f nd GBW = 2π C c g m6 2π C Ln C n1 C c Willy Sansen

12 Miller CMOS OTA : poles and zero C c 1pF 0.1pF 10fF A v C ct f d f C ct 20 ff 1k 1M Hz A A v2 v0 but is sufficient C c = 0 for C c = 1pF BW C c = 1pF 1k GBW 1M f nd f z f Pole splitting starts at f z = C n1 g m6 2π C c Willy Sansen

13 Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other specs: Input range, output range, SR,... Willy Sansen

14 Miller CMOS OTA: Design plan GBW = g m1 2π C c GBW = 100 MHz and C L = 2 pf f nd g m6 1 2π C Ln4 1+ C n1 C c Two equations for Three variables g m1, g m6 and C c?!? Solution : choose g m1 or g m6 or C c!!! Willy Sansen

15 What is wrong with choosing C c = 1 pf? Willy Sansen

16 Miller CMOS OTA: Design vs C c Choose C c 3 C n1 GBW = g m1 2π C c g m6 4 C L g m1 C c 3GBW g m6 2π C Ln GBW = 100 MHz and C L = 2 pf Choose C n1 < C c < C L Choice C c = 1 pf gives g m1 = 0.63 ms and g m6 = 5.0 ms Willy Sansen

17 Miller CMOS OTA: Design vs C c g m g m6 g m6min = 3 GBW (2π C L ) g m1 g m6min C c C copt 4 C L Willy Sansen

18 1 MHz Miller CMOS OTA: Design vs C c ms GBW = 1 MHz C n1 ct g mtot 2g m1 C L = 10 pf C n1 =0.4 pf 1 K = 20 µa/v 2 C n1 ~ g m V GS -V T = 0.2 V L = 10 µm 0.2 g m pf C c C n1 = 0.4 pf Willy Sansen

19 Miller CMOS OTA : Design vs I DS6 Area g m6min = Area C c 3 GBW (2π C L ) Area M6 g m6 g m6min g m6opt 1.3 g m6min + 30 % Willy Sansen

20 Miller CMOS OTA : Design vs I DS1 Area Area M6?!? Area C c C L g m1 Willy Sansen

21 Optimum design for high speed Miller OTA - 1 GBW = g m1 C L = α C c α 2 f nd = 2π C c g m6 2π C L Cn1 /Cc C c = β C n1 = β C GS6 β 3 f nd = γ GBW γ 2 C GS = kw k= F/cm GBW = f nd γ = g m6 2π C L 1 γ (1 + 1/ β) C L = α C c = α β C n1 = α β C GS6 = α β kw 6 W 6 if C L Willy Sansen

22 Optimum design Miller for high speed OTA - 2 Elimination of C L yields GBW = g m6 2π kw 6 1 α β γ (1 + 1/ β) g m = W L L /V GST f T6 W, L in cm GBW = 1 2π L 6 1 α β γ (1 + 1/ β) L 6 / V GST6 L in cm GBW is not determined by C L, only by L (and V GST )!! f T is also determined by L!!! Willy Sansen

23 Optimum design Miller for high speed OTA - 3 Substitution for f T yields f T = g m 2πC GS GBW = f T6 α β γ (1 + 1/ β) GBW is not determined by C L, only by f T f T is determined by L (and V GST )!!! 1.35 f T = 1 L L / V GST L in cm f T in MHz If V GST = 0.2 V, v sat takes over for L < 65 nm (If 0.5 V for L < 0.15 µm) Willy Sansen

24 Maximum GBW versus channel length L GBW GHz 10 1 V GS -V T 0.2 V v sat α 2 β 3 γ 2 or 16 x K nm 100 nm L 1 µm GBW f T6 16 Willy Sansen

25 Design optimization for high speed Miller OTA Choose α β γ Find minimum f T6 for specified GBW Choose maximum channel length L 6 (max. gain) for a chosen V GS6 -V T W 6 is calculated from C L, and determines I DS6 C c is calculated from C L through α g m1 and I DS1 are calculated from C c Noise is determined by g m1 or C c Willy Sansen

26 Design Ex. for GBW = 0.4 GHz & CL = 5 pf Choose α β γ Minimum f T6 for GBW = 0.4 GHz f T6 = 6.4 GHz Maximum channel length L 6 L 6 = 0.5 µm for a chosen V GS6 -V T = 0.2 V L 6 is taken to be the minimum L W 6 is calculated from C L, W 6 = 417 µm and determines I DS6 (K n = 70 µa/v2 ) I DS6 = 2.3 ma and determines C n1 (k = 2 ff/µm) C n1 = 0.83 pf C c is calculated from C L through α C c = 2.5 pf g m1 and I DS1 are calculated from C I c DS1 = 0.63 ma Willy Sansen

27 Optimum design Miller for low speed OTA GBW = f T6 α β γ (1 + 1/ β) f T = f TH i (1 - e - i ) i for small i f TH = 2 µ kt/q 2π L 2 GBW is not determined by C L, only by f T f T is determined by L and i!!! Willy Sansen

28 Design optimization for low speed Miller OTA Choose α β γ Find minimum f T6 for specified GBW Choose channel length L 6 (max. gain), which gives f TH6 Calculate i 6 W 6 is calculated from C L, and determines I DST6 and I DS6 C c is calculated from C L through α g m1 and I DS1 are calculated from C c Noise is determined by g m1 or C c Willy Sansen

29 Design Ex. for GBW = 1 MHz & CL = 5 pf Choose α β γ Minimum f T6 for GBW = 1 MHz f T6 = 16 MHz Maximum channel length L 6 L 6 = 0.5 µm gives f TH6 f TH6 = 2 GHz Inversion coefficient i is i = W 6 is calculated from C L, W 6 = 417 µm and determines I DST6 (K n = 70 µa/v2 ) I DST6 = 0.33 ma and determines I DS6 I DS6 = 2.7 µa and determines C n1 (k = 2 ff/µm) C n1 = 0.83 pf C c is calculated from C L through α C c = 2.5 pf g m1 and I DS1 are calculated from C I c DS1 = 1.6 µa Willy Sansen

30 Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other : SR, Output Impedance, Noise,... Willy Sansen

31 Miller CMOS OTA: Specifications 1 1. Introductory analysis 1.1 DC currents and voltages on all nodes 1.2 Small-signal parameters of all transistors 2. DC analysis 2.1 Common-mode input voltage range vs supply Voltage 2.2 Output voltage range vs supply Voltage 2.3 Maximum output current (sink and source) Willy Sansen

32 Miller CMOS OTA: Specifications 2 3. AC and transient analysis 3.1 AC resistance and capacitance on all nodes 3.2 Gain versus frequency : GBW, 3.3 Gainbandwidth versus biasing current 3.4 Slew rate versus load capacitance 3.5 Output voltage range versus frequency 3.6 Settling time 3.7 Input impedance vs frequency (open & closed loop) 3.8 Output impedance vs frequency (open & closed loop) Willy Sansen

33 Miller CMOS OTA: Specifications 3 4. Specifications related to offset and noise 4.1 Offset voltage versus common-mode input Voltage 4.2 CMRR versus frequency 4.3 Input bias current and offset 4.4 Equivalent input noise voltage versus frequency 4.5 Equivalent input noise current versus frequency 4.6 Noise optimization for capacitive/inductive sources 4.7 PSRR versus frequency 4.8 Distortion Willy Sansen

34 Miller CMOS OTA: Specifications 4 5. Other second-order effects 5.1 Stability for inductive loads 5.2 Switching the biasing transistors 5.3 Switching or ramping the supply voltages 5.4 Different supply voltages, temperatures,... Willy Sansen

35 M C O : Other specifications o Common-mode input voltage range o Output voltage range o Slew Rate o Output impedance o Noise Willy Sansen

36 Miller CMOS OTA 5 M7 1 : B M5 V DD GBW = 1 MHz C L = 10 pf R L = 10 kω v C c M1 M2 v 4 v OUT g m1 = 7.5 µs I DS1 = 1 µa R L C L g o24 = 0.03 µs 2 M3 1 M4 M6 V SS g m6 = 246 µs I DS6 = 25 µa C c = 1 pf Willy Sansen

37 Miller CMOS OTA : CM Input Voltage Range 3V V ICM 2V V DD 1V V ICMmax 0V -1V V ICM -2V -3V V SS V ICMmin 0 1V 2V ±2.5V 3V 4V V DD = V SS Willy Sansen

38 Miller CMOS OTA : Output Voltage Range 3V V OUT Rail-to-rail output if no R L V DD 2V V DD V OUTmax M5 1V 0V 4 v OUT -1V V OUT R L C L -2V -3V V SS V OUTmin 0 1V 2V ±2.5V 3V 4V V DD = V SS Willy Sansen

39 Miller CMOS OTA : Slew Rate - 1 v 5 3 M1 M7 1 : B I B1 I B1 - C c M5 4 V DD v OUT Switch input : v + > 1 v - > M6 R L C L SR = V OUT t M3 M4 V SS SR = I B1 C c Willy Sansen

40 Miller CMOS OTA : Slew Rate - 2 v IN v IN t t v OUT v OUT SR SR t SR SR V OUTmax t SR V OUTmax f max 4 V OUTmax SR 4 fmax SR T max 4 Willy Sansen

41 Miller CMOS OTA : Slew Rate - 3 V p 2 V OUT V OUTmax SR 4 fmax SR = 2.2 V/µs M 0.4M 0.6M 0.8M 1MHz f Willy Sansen

42 Design for GBW or SR? SR GBW = 4π I DS1 g m1 I DS1 V = GS1 -V T g m1 2 I DS1 g m1 = nkt q V for MOST (si) x mv for MOST (wi) I CE1 kt g m1 = q 26 mv for Bipolar trans. I CE1 g m1 = (1 + g m1 R E ) kt q V with R E Solomon, JSSC Dec 74, Willy Sansen

43 High SR by g m reduction V DD I B I B SR v- n : 1 M3 M1 M2 1 : n M4 v+ 2π GBW = x (n+1) v OUT C L M5 M6 V SS Ref. Schmoock, JSSC Dec.75, Willy Sansen

44 External vs internal Slew Rate V DD M5 I DS5 SR int = I B C c I B C c 4 v OUT I DS5 SR ext = is larger! C L 1 M6 C L g m6 = 4 CL g m1 C c = I DS5 I DS1 M4 V SS I DS5 C L 2 2I DS1 C c Willy Sansen

45 Slew Rate and settling v IN t t TOT = t Slew + t 0.1 v OUT V OUT 0.1 % t Slew = V OUT SR SR t t 0.1 = 7 2π BW t Slew t 0.1 ln (1000) 7 Willy Sansen

46 Miller CMOS OTA Output Impedance M7 1 : B M5 V DD GBW = 1 MHz C L = 10 pf 5 v C c M1 M2 2 1 M3 M4 v 4 Z OUT M6 V SS g m1 = 7.5 µs R L I DS1 = 1 µa C L Z OUTCL g o24 = 0.03 µs g m6 = 246 µs I DS6 = 25 µa C c = 1 pf Willy Sansen

47 Miller CMOS OTA : Output impedance Z OUT Z OUT 1/g o MΩ A v20 open loop 1/g m6 4 kω f z = g o24 2πC c f z 4.8 khz A v10 A v with C L closed loop f f d f z GBW f nd Willy Sansen

48 Miller CMOS OTA : Noise density 1 dv in1 2 dv in2 2 C c 1 4 v OUT v in v n1 g o24 C n1 g Lo6 C L v neq g m1 v in g m6 v n1 dv 2 4/3 in1 4kT df dv 2 in2 g m1 2/3 4kT g df m6 Willy Sansen

49 Miller CMOS OTA : Noise density 2 dv eq 2 dv in1 2 A v10 2 Dominant on linear frequency scale! 4kT df 2/3 g m6 dv neq2 2 = dv neq2 2 A v10 = go24 dv in2 2 A v1 2 g m1 f z GBW f nd f f z = g o24 2πC c Willy Sansen

50 Miller CMOS OTA : Integrated Noise A 1 GBW f GBW n π = 2 GBW v nieq 2 = 0 dv nieq (f/ GBW) 2 0 v 2 4/3 nieq = 4kT GBW π 2 g m1 dx 1 + x 2 = π 2 C c = 1pF v Rs = 74.5 µv RMS v 2 4 nieq = 3 kt C c Willy Sansen

51 Noise density vs integrated noise A dv ni 2 4/3 = 4kT df g m BW BW n f v ni 2 = dv ni (f/ BW) 2 = 4kT 3C c Noise density (V 2 /Hz) ~ 1/g m (or R S ) Integrated noise (V RMS ) ~ 1/C c Willy Sansen

52 CMOS Miller OTA layout V SS IN+ IN- GBW = 1 MHz C L = 10 pf SR = 2.2 V/µs V DD = 5 V I TOT = 27 µa OUT I B 370 MHzpF/mA V DD Willy Sansen

53 Miller CMOS OTA : Exercise GBW = 50 MHz for C L = 2 pf : use min. I DS6! Techno: L min = 0.5 µm; K n = 50 µa/v 2 & K p = 25 µa/v 2 C GS = kw (= C ox WL) and k = 2 ff/ µm V GS -V T = 0.2 V Find g m6 I DS6 W 6 C n1 = C GS6 C c g m1 I DS1 dv ineq 2 v inrms Willy Sansen

54 Conclusion : Table of contents Design of Single-stage OTA Design of Miller CMOS OTA Design for GBW and Phase Margin Other specs: Input range, output range, SR,... Willy Sansen