Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen

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1 Lecture 20 Compensation of Op AmpsI (/30/02) Page 20 LECTURE 20 COMPENSATION OF OP AMPS I (READING: GHLM and , AH ) INTRODUCTION The objective of this presentation is to present the principles of compensating twostage op amps. Outline Compensation of Op Amps General principles Miller, Nulling Miller Selfcompensation Feedforward Summary ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 20 Compensation of Op AmpsI (/30/02) Page 202 GENERAL PRINCIPLES OF OP AMP COMPENSATION Objective Objective of compensation is to achieve stable operation when negative feedback is applied around the op amp. Types of Compensation. Miller Use of a capacitor feeding back around a highgain, inverting stage. Miller capacitor only Miller capacitor with an unitygain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. 2. Feedforward Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity. 3. Self compensating Load capacitor compensates the op amp. ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

2 Lecture 20 Compensation of Op AmpsI (/30/02) Page 203 SingleLoop, Negative Feedback Systems Block diagram: A(s) = differentialmode voltage gain of the op amp F(s) = feedback transfer function from the output of op amp back to the input. Definitions: Openloop gain = L(s) = A(s)F(s) Closedloop gain = V out(s) V in (s) = A(s) A(s)F(s) V in (s) Stability Requirements: The requirements for stability for a singleloop, negative feedback system is, A(jω 0 )F(jω 0 ) = L(jω 0 ) < where ω 0 is defined as Arg[ A(jω 0 )F(jω 0 )] = Arg[L(jω 0 )] = 0 Another convenient way to express this requirement is Arg[ A(jω 0dB )F(jω 0dB )] = Arg[L(jω 0dB )] > 0 where ω 0dB is defined as A(jω0dB)F(jω0dB) = L(jω0dB) = Σ F(s) A(s) V out (s) Fig. 200 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 20 Compensation of Op AmpsI (/30/02) Page 204 Illustration of the Stability Requirement using Bode Plots A(jω)F(jω) Arg[A(jω)F(jω)] 0dB dB/decade Φ M ω 0dB Frequency (rads/sec.) ω 40dB/decade ω Fig. Fig A measure of stability is given by the phase when A(jω)F(jω) =. This phase is called phase margin. Phase margin = Φ M = Arg[A(jω 0dB )F(jω 0dB )] = Arg[L(jω 0dB )] ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

3 Lecture 20 Compensation of Op AmpsI (/30/02) Page 205 Why Do We Want Good Stability? Consider the step response of secondorder system which closely models the closedloop gain of the op amp. (t) A v ω o t = ω n t (sec.) Fig A good step response is one that quickly reaches its final value. Therefore, we see that phase margin should be at least and preferably 60 or larger. (A rule of thumb for satisfactory stability is that there should be less than three rings.) ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 20 Compensation of Op AmpsI (/30/02) Page 206 Uncompensated Frequency Response of TwoStage Op Amps TwoStage Op Amps: V CC M3 M4 Q3 Q4 Q6 M M2 Q Q2 VBias SmallSignal Model: M5 V SS M7 VBias Q5 V EE Q7 Fig g m 2 D, D3 (C, C3) D2, D4 (C2, C4) D6, D7 (C6, C7) R C v g m2 2 g m4 v R 2 C v2 R 3 C 3 2 gm6 v 2 Fig Note that this model neglects the basecollector and gatedrain capacitances for purposes of simplification. ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

4 Lecture 20 Compensation of Op AmpsI (/30/02) Page 207 Uncompensated Frequency Response of TwoStage Op Amps Continued For the MOS twostage op amp: R g r m3 ds3 r ds g R m3 2 = r ds2 r ds4 and R 3 = r ds6 r ds7 C = C gs3 C gs4 C bd C bd3 C 2 = C gs6 C bd2 C bd4 and C 3 = C L C bd6 C bd7 For the BJT twostage op amp: R = g m3 r π3 r π4 r o3 g m3 R 2 = r π6 r o2 r o4 r π6 and R 3 = r o6 r o7 C = C π3 C π4 s s3 C 2 = C π6 s2 s4 and C 3 = C L s6 s7 Assuming the pole due to C is much greater than the poles due to C 2 and C 3 gives, g m R 2 C v2 R 3 C 3 2 gm6 v 2 g m V in V V out R I C I R II I gmii V I Fig The locations for the two poles are given by the following equations p = R I C I and p 2 = R II where R I (R II ) is the resistance to ground seen from the output of the first (second) stage and C I ( ) is the capacitance to ground seen from the output of the first (second) stage. ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 20 Compensation of Op AmpsI (/30/02) Page 208 Uncompensated Frequency Response of an Op Amp A vd (0) db 20dB/decade A(jω) Arg[A(jω)] 0dB Phase Shift /decade p ' log 0 (ω) ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 GB /decade 40dB/decade log 0 (ω) p 2 ' ω 0dB Fig If we assume that F(s) = (this is the worst case for stability considerations), then the above plot is the same as the loop gain. Note that the phase margin is much less than. Therefore, the op amp must be compensated before using it in a closedloop configuration.

5 Lecture 20 Compensation of Op AmpsI (/30/02) Page 209 TwoStage Op Amp MILLER COMPENSATION V CC M3 M M2 VBias C M M5 M4 V SS C I M7 Q3 Q4 C M Q Q2 VBias The various capacitors are: = accomplishes the Miller compensation C M = capacitance associated with the firststage mirror (mirror pole) C I = output capacitance to ground of the firststage = output capacitance to ground of the secondstage Q5 V EE C I Q6 Q7 Fig ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 20 Compensation of Op AmpsI (/30/02) Page 200 Compensated TwoStage, SmallSignal Frequency Response Model Simplified Use the CMOS op amp to illustrate:.) Assume that g m3 >> g ds3 g ds 2.) Assume that g m3 C M >> GB Therefore, v v2 g m 2 g m2 r ds r ds3 C M g m3 2 g m4 v C rds2 r ds4 g m6 v 2 r ds6 r ds7 C L v 2 g m CI rds2 r ds4 g m6 v C 2 II rds6 r ds7 Fig Same circuit holds for the BJT op amp with different component relationships. ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

6 Lecture 20 Compensation of Op AmpsI (/30/02) Page 20 General TwoStage Frequency Response Analysis V in g mi V in C I RI gmii V 2 R II where g mi = g m = gm2, R I = r ds2 r ds4, C I = C and g mii = g m6, R II = r ds6 r ds7, = C 2 = C L Nodal Equations: g mi V in = [G I s(c I )]V 2 [s ]V out and 0 = [g mii s ]V 2 [G II s s ]V out Solving using Cramer s rule gives, V out (s) V in (s) = g mi (g mii s ) G I G II s [G II (C I )G I ( )g mii ]s 2 [C I C I ] A o [ s ( /g mii )] = s [R I (C I )R II (C 2 )g mii R R II ]s 2 [R I R II (C I C I )] where, A o = g mi g mii R I R II In general, D(s) = s p s p = s 2 p p s2 2 p p D(s) s 2 p s2 p p, if p 2 >> p 2 p = V 2 R I (C I )R II ( )g mii R R II p 2 = [R I(C I )R II ( )g mii R R II ] R I R II (C I C I ) V out Fig.200 g mii R R II, z = g mii g mii C I C I g mii, > > C I ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 20 Compensation of Op AmpsI (/30/02) Page 202 Summary of Results for Miller Compensation of the TwoStage Op Amp There are three roots of importance:.) Righthalf plane zero: z = g mii = g m6 This root is very undesirable it boosts the magnitude while decreasing the phase. 2.) Dominant lefthalf plane pole (the Miller pole): p g mii R I R II = (g ds2g ds4 )(g ds6 g ds7 ) g m6 This root accomplishes the desired compensation. 3.) Lefthalf plane output pole: p 2 g mii g m6 C L This pole must be unitygainbandwidth or the phase margin will not be satisfied. Root locus plot of the Miller compensation: Closedloop poles, 0 Openloop poles =0 jω σ p 2 p 2 ' p ' p z Fig. 20 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

7 Lecture 20 Compensation of Op AmpsI (/30/02) Page 203 Compensated OpenLoop Frequency Response of the TwoStage Op Amp A(jω)F(jω) A vd (0) db Compensated Uncompensated 20dB/decade Arg[A(jω)F(jω) Note that the unitygainbandwidth, GB, is GB 0dB log 0 (ω) Phase Shift Uncompensated 40dB/decade /decade 90 /decade Compensated Phase No phase margin Margin 0 log 0 (ω) p p ' p 2 ' p 2 Fig. 202 GB = A vd (0) p = (g mi g mii R I R II ) g mii R I R II C = g mi c C = g m c C = g m2 c ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 20 Compensation of Op AmpsI (/30/02) Page 204 Conceptually, where do these roots come from?.) The Miller pole: p R I (g m6 R II ) R I R II v I g m6 R II Fig ) The lefthalf plane output pole: R II RII p 2 g m6 GB C 0 c 3.) Righthalf plane zero (Zeros always arise from multiple paths from the input to output): g v R R m6 II II sc c R II /s v = R II /s v g = m6 R II (/s ) R II /s where v = v = v. v'' v' Fig. 204 R II Fig. 205 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

8 Lecture 20 Compensation of Op AmpsI (/30/02) Page 205 Influence of the Mirror Pole Up to this point, we have neglected the influence of the pole, p 3, associated with the current mirror of the input stage. A smallsignal model for the input stage that includes C 3 is shown below: gmv in 2 rds rds3 i 3 gm2v in i gm3 C3 2 3 rds2 rds4 Fig. 206 The transfer function from the input to the output voltage of the first stage, V o (s), can be written as V o (s) V in (s) = g m g 2(g ds2 g ds4 ) m3 g ds g ds3 g m sc g m3 g ds g ds3 sc 3 2(g ds2 g ds4 ) 3 2g m3 sc 3 g m3 We see that there is a pole and a zero given as p 3 = g m3 C 3 and z 3 = 2g m3 C 3 V o ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002 Lecture 20 Compensation of Op AmpsI (/30/02) Page 206 Influence of the Mirror Pole Continued Fortunately, the presence of the zero tends to negate the effect of the pole. Generally, the pole and zero due to C 3 is greater than GB and will have very little influence on the stability of the twostage op amp. The plot shown illustrates the case where these roots are less than GB and even then they have little effect on stability. In fact, they actually increase the phase margin slightly because GB is decreased. A vd (0) db 0dB Phase Shift F = 0 = 0 Magnitude influence of C 3 = 0 /decade = 0 Phase margin due to C 3 6dB/octave p p 3 z 3 p 2 GB log 0 (ω) 2dB/octave 0 /decade Phase margi ignoring C 3 log 0 (ω) Fig. 207 ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002

9 Lecture 20 Compensation of Op AmpsI (/30/02) Page 207 SUMMARY Compensation Designed so that the op amp with unity gain feedback (buffer) is stable Types Miller Miller with nulling resistors Self Compensating Feedforward ECE 642 Analog Integrated Circuit Design II P.E. Allen 2002