NMOS (N-Channel Metal Oxide Semiconductor) Transistor. NMOS Transistor in Equilibrium

Size: px
Start display at page:

Download "NMOS (N-Channel Metal Oxide Semiconductor) Transistor. NMOS Transistor in Equilibrium"

Transcription

1 NMOS (N-Cannel Metal Oxide Semiconductor) Transistor e e e oxide insulator e e e NMOS Transistor in Equilibrium oxide insulator Wen te transistor is left alone, some electrons from te wells diffuse into te material to fill oles. Tis creates negative ions in te material and positive ions are left beind in te material.

2 NMOS Transistor in Cutoff V GS > 0 oxide insulator _ Wen a small, positive V GS is applied, oles move away from te. Electrons from complete atoms elsewere in te material move to fill oles near te instead. NMOS Transistor Cannel V GS > V TH(N) oxide insulator e e _ e e e Wen V GS is larger tan a tresold voltage V TH(N), te attraction to te is so great tat free electrons collect tere. Tus te applied V GS creates an induced cannel under te (an area wit free electrons).

3 NMOS Transistor rain Current V GS > V TH(N) oxide insulator e e _ e e e V S > 0 Wen a positive V S is applied, te free electrons flow from te to te. (Positive current flows from to ). Te amount of current depends on V S, as well as te number of electrons in te cannel, cannel dimensions, and material. NMOS Transistor V S V GS I G oxide insulator I G I G V GS _ I S - V S

4 NMOS I-V CHARACTERISTIC G I G V GS _ I S - V S Since te transistor is a 3-terminal device, tere is no single I-V caracteristic. Note tat because of te insulator, I G = 0 A. We typically define te MOS I-V caracteristic as I vs. V S for a fixed V GS. MOES OF OPERATION For small values of V GS, V GS V TH(N), te cannel is not formed. No current flows. Tis is cutoff mode. Wen V GS > V TH(N), current I may flow from to, and te following modes of current flow are possible. Te mode of current flow depends on te propelling voltage, V S, and te cannel-inducing voltage, V GS V TH(N). Wen V S < V GS V TH(N), current is starting to flow. I increases rapidly wit increased V S. Tis is triode mode. Wen V S V GS V TH(N), current is reacing its maximum value. I does not increase muc wit increased V S. Tis is called saturation mode.

5 NMOS I-V CHARACTERISTIC Cutoff Mode Occurs wen V GS V TH(N) I = 0 Triode Mode Occurs wen V GS > V TH(N) and V S < V GS -V TH(N) I = W µ n C L OX ( V GS V TH(N) ( V S /2)) V S Saturation Mode Occurs wen V GS > V TH(N) and V S V GS -V TH(N) 2 ( V V ) ( 1 λ V ) W 1 I = µ ncox GS TH(N) L 2 n S NMOS I-V CHARACTERISTICS I triode mode saturation mode V GS = 3 V V S = V GS -V TH(N) V GS = 2 V V GS = 1 V V S cutoff mode

6 PMOS (P-Cannel Metal Oxide Semiconductor) Transistor oxide insulator Same as NMOS, only and switced PMOS Transistor Cannel V GS < V TH(P) < 0 oxide insulator e e e e e e e e e e Wen V GS is more negative tan a tresold voltage V TH(P), te attracts many positive ions and oles (repels electrons) Tus te applied V GS creates an induced cannel under te (an area wit positive ions).

7 PMOS Transistor rain Current V GS < V TH(P) < 0 V S < 0 oxide insulator e e e e e e e e e e Wen a negative V S is applied, te positive ions flow from te to te. (Positive current flows from to ). Te amount of current depends on V S, as well as te number of ions in te cannel, cannel dimensions, and material. PMOS TRANSISTOR G I G V GS _ I S - V S Symbol as dot at. NMOS does not. I, V GS, V S, and V TH(P) are all negative. Tese values are positive for NMOS. Cannel formed wen V GS < V TH(P). Opposite for NMOS. Saturation occurs wen V S V GS V TH(P). Opposite for NMOS.

8 PMOS I-V CHARACTERISTIC Cutoff Mode Occurs wen V GS V TH(P) I = 0 Triode Mode Occurs wen V GS < V TH(P) and V S > V GS -V TH(P) I W = µ p C L OX ( V GS V TH(P) ( V S /2)) V S Saturation Mode Occurs wen V GS < V TH(P) and V S V GS -V TH(P) 2 ( V V ) ( 1 λ V ) W 1 I = µ pcox GS TH(P) L 2 p S PMOS I-V CHARACTERISTICS V S cutoff mode V GS = -1 V V GS = -2 V V S = V GS -V TH(P) V GS = -3 V I saturation mode triode mode

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

Microelectronics Part 1: Main CMOS circuits design rules

Microelectronics Part 1: Main CMOS circuits design rules GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics. ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "

More information

Charge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )

Charge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn ) The Inverted MO Capacitor (V > V Tn ) We consider the surface potential as Þxed (ÒpinnedÓ) at φ s,max = - φ p φ(x).5 V. V V ox Charge torage in the MO tructure Three regions of operation: Accumulation:

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

3 Minority carrier profiles (the hyperbolic functions) Consider a

3 Minority carrier profiles (the hyperbolic functions) Consider a Microelectronic Devices and Circuits October 9, 013 - Homework #3 Due Nov 9, 013 1 Te pn junction Consider an abrupt Si pn + junction tat as 10 15 acceptors cm -3 on te p-side and 10 19 donors on te n-side.

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

The Gradual Channel Approximation for the MOSFET:

The Gradual Channel Approximation for the MOSFET: 6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

Lecture XVII. Abstract We introduce the concept of directional derivative of a scalar function and discuss its relation with the gradient operator.

Lecture XVII. Abstract We introduce the concept of directional derivative of a scalar function and discuss its relation with the gradient operator. Lecture XVII Abstract We introduce te concept of directional derivative of a scalar function and discuss its relation wit te gradient operator. Directional derivative and gradient Te directional derivative

More information

On my honor as a student, I have neither given nor received unauthorized assistance on this exam.

On my honor as a student, I have neither given nor received unauthorized assistance on this exam. HW2 (Overview of Transport) (Print name above) On my onor as a student, I ave neiter given nor received unautorized assistance on tis exam. (sign name above) 1 Figure 1: Band-diagram before and after application

More information

! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)

! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions.  Resistive.  Saturation.  Subthreshold (next class) ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating

More information

FIELD-EFFECT TRANSISTORS

FIELD-EFFECT TRANSISTORS FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

More information

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Lecture 28 Field-Effect Transistors

Lecture 28 Field-Effect Transistors Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

Numerical Analysis MTH603. dy dt = = (0) , y n+1. We obtain yn. Therefore. and. Copyright Virtual University of Pakistan 1

Numerical Analysis MTH603. dy dt = = (0) , y n+1. We obtain yn. Therefore. and. Copyright Virtual University of Pakistan 1 Numerical Analysis MTH60 PREDICTOR CORRECTOR METHOD Te metods presented so far are called single-step metods, were we ave seen tat te computation of y at t n+ tat is y n+ requires te knowledge of y n only.

More information

Chapter 2 MOS Transistor theory

Chapter 2 MOS Transistor theory Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the

More information

Field-Effect (FET) transistors

Field-Effect (FET) transistors Field-Effect (FET) transistors References: Barbow (Chapter 8), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and, therefore, its current-carrying

More information

Design of Analog Integrated Circuits

Design of Analog Integrated Circuits Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

Higher Derivatives. Differentiable Functions

Higher Derivatives. Differentiable Functions Calculus 1 Lia Vas Higer Derivatives. Differentiable Functions Te second derivative. Te derivative itself can be considered as a function. Te instantaneous rate of cange of tis function is te second derivative.

More information

LIMITATIONS OF EULER S METHOD FOR NUMERICAL INTEGRATION

LIMITATIONS OF EULER S METHOD FOR NUMERICAL INTEGRATION LIMITATIONS OF EULER S METHOD FOR NUMERICAL INTEGRATION LAURA EVANS.. Introduction Not all differential equations can be explicitly solved for y. Tis can be problematic if we need to know te value of y

More information

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

More information

Stepped-Impedance Low-Pass Filters

Stepped-Impedance Low-Pass Filters 4/23/27 Stepped Impedance Low Pass Filters 1/14 Stepped-Impedance Low-Pass Filters Say we know te impedance matrix of a symmetric two-port device: 11 21 = 21 11 Regardless of te construction of tis two

More information

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

Andrei Vladimirescu Homework #6 EECS141 Due Friday, April 1 st, Cory. X A B C D E F G using complementary

Andrei Vladimirescu Homework #6 EECS141 Due Friday, April 1 st, Cory. X A B C D E F G using complementary UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on Marc 15 t, 2005 by Cris Baker (crbaker@eecs) Andrei Vladimirescu Homework #6

More information

P-MOS Device and CMOS Inverters

P-MOS Device and CMOS Inverters Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Chapter 9 - Solved Problems

Chapter 9 - Solved Problems Capter 9 - Solved Problems Solved Problem 9.. Consider an internally stable feedback loop wit S o (s) = s(s + ) s + 4s + Determine weter Lemma 9. or Lemma 9. of te book applies to tis system. Solutions

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

4. The slope of the line 2x 7y = 8 is (a) 2/7 (b) 7/2 (c) 2 (d) 2/7 (e) None of these.

4. The slope of the line 2x 7y = 8 is (a) 2/7 (b) 7/2 (c) 2 (d) 2/7 (e) None of these. Mat 11. Test Form N Fall 016 Name. Instructions. Te first eleven problems are wort points eac. Te last six problems are wort 5 points eac. For te last six problems, you must use relevant metods of algebra

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects

More information

Chapters 19 & 20 Heat and the First Law of Thermodynamics

Chapters 19 & 20 Heat and the First Law of Thermodynamics Capters 19 & 20 Heat and te First Law of Termodynamics Te Zerot Law of Termodynamics Te First Law of Termodynamics Termal Processes Te Second Law of Termodynamics Heat Engines and te Carnot Cycle Refrigerators,

More information

MOS Capacitors ECE 2204

MOS Capacitors ECE 2204 MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field

More information

Part 4: Heterojunctions - MOS Devices. MOSFET Current Voltage Characteristics

Part 4: Heterojunctions - MOS Devices. MOSFET Current Voltage Characteristics MOS Device Uses: Part 4: Heterojunctions - MOS Devices MOSCAP capacitor: storing charge, charge-coupled device (CCD), etc. MOSFET transistor: switch, current amplifier, dynamic random access memory (DRAM-volatile),

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Solution for the Homework 4

Solution for the Homework 4 Solution for te Homework 4 Problem 6.5: In tis section we computed te single-particle translational partition function, tr, by summing over all definite-energy wavefunctions. An alternative approac, owever,

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

Lecture 10 - Carrier Flow (cont.) February 28, 2007

Lecture 10 - Carrier Flow (cont.) February 28, 2007 6.720J/3.43J Integrated Microelectronic Devices - Spring 2007 Lecture 10-1 Lecture 10 - Carrier Flow (cont.) February 28, 2007 Contents: 1. Minority-carrier type situations Reading assignment: del Alamo,

More information

Homework Assignment No. 1 - Solutions

Homework Assignment No. 1 - Solutions Homework Assignment o. 1 - Solutions Problem P1.7 This question is as easy as it looks, no tricks here. a. The delay from a to b is simply the delay of an inverter times the number of inverters which would

More information

Last lecture (#4): J vortex. J tr

Last lecture (#4): J vortex. J tr Last lecture (#4): We completed te discussion of te B-T pase diagram of type- and type- superconductors. n contrast to type-, te type- state as finite resistance unless vortices are pinned by defects.

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

EE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS

EE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS EE 240B Spring 2018 Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models Elad Alon Dept. of EECS Square Law Model? Assumptions made to come up with this model: Charge density determined

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

ECE315 / ECE515 Lecture 11 Date:

ECE315 / ECE515 Lecture 11 Date: ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)

More information

ECE 342 Electronic Circuits. Lecture 34 CMOS Logic

ECE 342 Electronic Circuits. Lecture 34 CMOS Logic ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic - Generalization ABC... ABC...

More information

ECE315 / ECE515 Lecture-2 Date:

ECE315 / ECE515 Lecture-2 Date: Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

More information

EE 560 MOS TRANSISTOR THEORY

EE 560 MOS TRANSISTOR THEORY 1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

More information

Section 2.1 The Definition of the Derivative. We are interested in finding the slope of the tangent line at a specific point.

Section 2.1 The Definition of the Derivative. We are interested in finding the slope of the tangent line at a specific point. Popper 6: Review of skills: Find tis difference quotient. f ( x ) f ( x) if f ( x) x Answer coices given in audio on te video. Section.1 Te Definition of te Derivative We are interested in finding te slope

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with

More information

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems

More information

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

Dual Nature of matter and radiation: m v 1 c

Dual Nature of matter and radiation: m v 1 c Dual Nature of matter and radiation: Potons: Electromagnetic radiation travels in space in te form discrete packets of energy called potons. Tese potons travel in straigt line wit te speed of ligt. Important

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues

EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

Chapter 1 Functions and Graphs. Section 1.5 = = = 4. Check Point Exercises The slope of the line y = 3x+ 1 is 3.

Chapter 1 Functions and Graphs. Section 1.5 = = = 4. Check Point Exercises The slope of the line y = 3x+ 1 is 3. Capter Functions and Graps Section. Ceck Point Exercises. Te slope of te line y x+ is. y y m( x x y ( x ( y ( x+ point-slope y x+ 6 y x+ slope-intercept. a. Write te equation in slope-intercept form: x+

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

The transistor is not in the cutoff region. the transistor is in the saturation region. To see this, recognize that in a long-channel transistor ifv

The transistor is not in the cutoff region. the transistor is in the saturation region. To see this, recognize that in a long-channel transistor ifv ECE 440 Spring 005 Page 1 Homework Assignment No. Solutions P.4 For each transistor, first determine if the transistor is in cutoff by checking to see if GS is less than or greater than. may have to be

More information

Math 102 TEST CHAPTERS 3 & 4 Solutions & Comments Fall 2006

Math 102 TEST CHAPTERS 3 & 4 Solutions & Comments Fall 2006 Mat 102 TEST CHAPTERS 3 & 4 Solutions & Comments Fall 2006 f(x+) f(x) 10 1. For f(x) = x 2 + 2x 5, find ))))))))) and simplify completely. NOTE: **f(x+) is NOT f(x)+! f(x+) f(x) (x+) 2 + 2(x+) 5 ( x 2

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

f a h f a h h lim lim

f a h f a h h lim lim Te Derivative Te derivative of a function f at a (denoted f a) is f a if tis it exists. An alternative way of defining f a is f a x a fa fa fx fa x a Note tat te tangent line to te grap of f at te point

More information

Derivatives of Exponentials

Derivatives of Exponentials mat 0 more on derivatives: day 0 Derivatives of Eponentials Recall tat DEFINITION... An eponential function as te form f () =a, were te base is a real number a > 0. Te domain of an eponential function

More information

ECE321 Electronics I

ECE321 Electronics I EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

More information

ELECTRONICS IA 2017 SCHEME

ELECTRONICS IA 2017 SCHEME ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8

More information