ECE315 / ECE515 Lecture 11 Date:


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1 ecture 11 Date: MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis
2 MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!) ensures M 1 and M in saturation Variation of input CM level regulates the bias currents of M 1 and M Undesired!!! Solution?? Current source is ideal: constant current, infinite output impedance To overcome the issues emanating from nonideal CM level
3 MOS Differential Pair Qualitative Analysis differential input et us check the effect of V in1 V in variation from  to V in1 is much more ve than V in then: M 1 if OFF and M is ON I D = I SS V out1 = V DD and V out = V DD I SS R D V in1 is brought closer to V in then: M 1 gradually turns ON and M is ON Draws a fraction of I SS and lowers V out1 I D decreases and V out rises V in1 = V in V out1 = V out = V DD  I SS R D /
4 MOS Differential Pair ECE315 / ECE515 Qualitative Analysis differential input et us check the effect of V in1 V in variation from  to V in1 becomes more +ve than V in then: M 1 if ON and M is ON M 1 carries greater I SS than M For sufficiently large V in1 V in : All of the I SS goes through M 1 M is OFF V out1 = V DD I SS R D and V out = V DD
5 MOS Differential Pair Plotting V out1 V out versus V in1 V in ECE315 / ECE515 Qualitative Analysis differential input Minimum Slope Minimum Gain Maximum Slope Maximum Gain The maximum and minimum levels at the output are well defined and is independent of input CM level (V in,cm ) The circuit becomes more nonlinear as the input voltage swing increases (i.e., V in1 V in increases) at V in1 = V in, the circuit is said to be in equilibrium
6 MOS Differential Pair Qualitative Analysis common mode input Now let us consider the common mode behavior of the circuit As mentioned, the tail current source is used to suppress the effect of input CM level variation (V in,cm ) Does this enable us to set any arbitrary level of input CM (V in,cm ) To understand this: Set V in1 = V in = V in,cm Then vary V in,cm from 0 to V DD Also implement I SS with an NFET ower bound of V in,cm : V P should be sufficiently high in order for M 3 to act as a current source. Upper bound of V in, cm : M 1 and M need to remain in saturation.
7 MOS Differential Pair ECE315 / ECE515 Qualitative Analysis common mode input hat happens when V in,cm = 0? M 1 and M will be OFF and M 3 can be in triode for high enough V b I D1 = I D = 0 circuit is incapable of amplification Now suppose V in,cm becomes more +ve M 1 and M will turn ON if V in,cm exceeds V T I D1 and I D will continue to rise with the increase in V in,cm V P will track V in,cm as M 1 and M work like a source follower For high enough V in,cm, M 3 will be in saturation as well If V in,cm rises further M 1 and M will remain in saturation if: SS Vin, CM VT Vout 1 V I, V R V in CM DD D T
8 MOS Differential Pair ECE315 / ECE515 Qualitative Analysis common mode input For M 1 and M to remain in saturation: I I SS SS VGS 1, VT V V DS1, in, CM VT VDD R V D in, CM VT VDD RD ISS ( Vin, CM ) max VT VDD RD The lowest value of V in,cm is Vin, CM VGS 1, VGS 3 VT determined by the need to keep the constant current source operational: Vin, CM VGS 1, ( VGS 3 VT 3) I V ( V V ) V min V R V, V SS GS1, GS 3 T in, CM DD D T DD
9 MOS Differential Pair Thus, V in,cm is bounded as: ECE315 / ECE515 Qualitative Analysis common mode input Summary: I V ( V V ) V min V R V, V SS GS1, GS 3 T in, CM DD D T DD M 1 =M =Off M 3 =inear M 1 =M =On M 1 =M =Off M 3 =inear M 1 =M =On M 1 =M =Off M 3 =inear M 1 =M =On
10 MOS Differential Pair ECE315 / ECE515 Qualitative Analysis common mode input How large can the output voltage swings of a differential pair be? V out,max V DD V V V out,min in, CM T The higher the input CM level, the smaller the allowable output swings.
11 MOS Differential Pair Quantitative Analysis differential input For +ve V in1 V GS1 is greater than V GS I D1 will be greater than I D P V ( V I R ) V ( V I R ) out DD D D out1 DD D1 D For +ve V in V GS is greater than V GS1 I D will be greater than I D1 V ( V I R ) V ( V I R ) out1 DD D1 D out DD D D It is thus apparent that the differential pair respond to differentialmode signals by providing differential output signal between the two drains
12 Differential Pair arge Signal Analysis Quantitative Analysis differential input P The idea is to define I D1 and I D in terms of input differential signal V in1 V in The circuit doesn t include connection details considering that these drain current equations do not depend on the external circuitries Assumptions: M 1 and M are always in saturation; differential pair is perfectly matched; channel length modulation is not present
13 Differential Pair arge Signal Analysis Quantitative Analysis differential input V V V V V P in1 GS1 in GS V V V V in1 in GS1 GS Therefore: P e also know: I VGS VT C D Squaring n ox I D VGS V ncox T V I I C C D1 D in1vin V in1 Vin I D1 I D I D1I D n ox n ox n C ox
14 Differential Pair arge Signal Analysis Quantitative Analysis differential input V in1 Vin I D1 I D I D1I D C n ox I SS ncox V in1 Vin ISS I D1I D Squaring 1 C V V I I I n ox in1 in SS D1 D 1 4 C V V I I C V V 4I I 4 n ox in1 in SS SS n ox in1 in D1 D 1 C V V I I C V V I I I I 4 4 n ox in1 in SS SS n ox in1 in D1 D D1 D
15 Differential Pair arge Signal Analysis Quantitative Analysis differential input 1 4 I I C V V I C V V 4 D1 D n ox in1 in SS n ox in1 in 1 4I I I C V V V V ncox SS D1 D n ox in1 in in1 in Observations I D1 I D falls to zero for V in1 = V in and I D1 I D increases with increase in V in1 V in Therefore, I D1 I D is an odd function of V in1 V in Its important to notice that I D1 and I D are even functions of their respective gatesource voltage
16 Differential Pair arge Signal Analysis Quantitative Analysis differential input Equivalent G m of M 1 and M its effectively the slope of the characteristics ets denote: I I I D1 D D V V V in1 in in 1 4I I C V V ncox SS D n ox in in For V in = 0: Furthermore: 1 I G C I D m n ox SS Vin V V R I R G V out out D D m in 4ISS V I 1 n ox D C ncox Vin 4ISS V ncox Vout Vout A C I R in in 1 v n ox SS D Vin
17 Differential Pair arge Signal Analysis Quantitative Analysis differential input 4ISS V 1 ncox Gm ncox 4ISS V ncox in in G m falls to zero for V in I SS C n V in1 ox V in1 represents the maximum differential signal a differential pair can handle. Beyond V in1, only one transistor is ON and therefore draws all of the I SS
18 Differential Pair arge Signal Analysis Quantitative Analysis differential input I SS Constant Reduce V in1 by increasing / inearity Improves / Constant Increase V in1 by increasing I SS inearity Improves inearity of a differential pair can be improved by decreasing / and/or increasing I SS
19 MOS Differential Pair small signal analysis Quantitative Analysis differential input From large signal analysis we achieved: Vout Vout A g R 1 v m D Vin Vout Vout A C I R 1 v n ox SS D Vin At equilibrium, this is g m How to arrive at this result using small signal analysis? Two techniques Superposition method Halfcircuit concept e apply small signals to V in1 and V in and assume M 1 and M are already operating in saturation.
20 MOS Differential Pair small signal analysis MethodI: Superposition technique the idea is to see the effect of V in1 and V in on the output and then combine to get the differential small signal voltage gain First set, V in = 0 Then let us calculate V X /V in1 Simplified Circuit CSstage This is open for small signal analysis Input impedance of M Provides degeneration resistance to CSstage of M 1 1 g m1 + 1 g m V V X in1 RD 1 1 g g m1 m V V X in1 RD g g m1 m
21 MOS Differential Pair small signal analysis Superposition technique Now calculate V Y /V in1 Simplified Circuit V T = V in1 R T = 1 g m1 Replace M 1 by its Thevenin Equivalent Circuit This is open for small signal analysis V V Y in1 RD 1 1 g g m m1 CGStage combine the expressions to calculate VX VY due _ to _ V RD V 1 1 in1 g g in1 small signal voltage only due to V in1 m1 m
22 MOS Differential Pair small signal analysis V V g R V For matched transistors: in1 Similarly: in Superposition gives: X Y due _ to _ V m D in1 V V g R V X Y due _ to _ V m D in A V V g R X Y total v m D Vin Vin 1 The magnitude of differential gain is g m R D regardless of how the inputs are applied The gain will be halved if single ended output is considered Half Circuit Approach If a fully symmetric differential pair senses differential inputs (i.e, the two inputs change by equal and opposite amounts from the equilibrium condition), then the concept of half circuit can be applied. Change this by V T R T1 = R T Potential at node P will remain unchanged Node is said to be acgrounded Change this by  V T
23 MOS Differential Pair small signal analysis Half Circuit Approach Ac grounding of node P leads to V in1 and V in1 are the change in input voltage at each side e can write: V X m D V g R in1 V Y m D V g R in1 Therefore the differential output can be expressed as: VX VY V in1 gmrd Thus the small signal voltage given is: A V V g R X Y v m D V in1
24 MOS Differential Pair small signal analysis How does the gain of a differential amplifier compare with a CS stage? For a given total bias current I SS, the value of equivalent g m of a differential pair is 1 times that of g m of a single transistor biased at the I SS with the same dimensions. Thus the total gain is proportionally less. Equivalently, for given device dimensions and load impedance, a differential pair achieves the same gain as a CS stage at the cost of twice the bias current. hat is the advantage of differential stage then? Definitely the noise suppression capability. Right?
25 MOS Differential Pair small signal analysis How is gain affected if channel length modulation is considered? Effect of r 0 on the gain V X V Y the circuit is still symmetric the voltage at node P will be zero V in1 M1 M V in1 No current through R SS P R SS plays no role in differential gain Finite output resistance of current source
26 MOS Differential Pair small signal analysis The virtual ground on the source allows division of two identical CS amplifiers: differential half circuits 1 V g V R r X m in D o VX Vin1 V in 1 M1 M I SS VY 1 V g V R r Y m in D o V V g V R r X Y m in1 D o V V A g R r X Y v m D o V in1
27 Small signal analysis asymmetric inputs Transform the inputs as Simplify Differential Inputs Simplified Circuit Common Mode Inputs
28 Small signal analysis asymmetric inputs Circuit for Differential Mode V V g R r V V X Y m D o in1 in Circuit for Common Mode If the circuit is fully symmetric and I SS is ideal current source, then M 1 and M draws half of I SS and is independent of V in,cm. The V X and V Y experience no change as V in,cm varies. In essence, the circuit simply amplifies the difference between V in1 and V in while eliminating the effect of V in,cm.
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