UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences PROBLEM SET #3 (SOLUTION)

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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences R. W. Brodersen EECS 140 Fall 2004 PROBLEM SET #3 (SOLUTION) 3) In the above circuit, use V DD =1.8 V, I SS =14 µa, R D =100 kω, W=10 µm, L=1 µm. a) Calculate V of the two transistors by hand, with V ic =0.9 V, V id =0 V, and verify with SPICE. V S V ISS R 2 I SS = W k L o1 = Vo 2 = VDD D = 2I VAT = W k L = V V V ic = V ic = 0.9 = 0.3 T AT 1.1V = 0.1V ( VT 0 + γ ( 2φ + VS 2φ ) V ( ( VS 0.6 ) 0.5( V 0.6) S AT 0.1 Solving iteratively, we find V = 0.231V, and therefore, V = 0.87 V. S

2 b) Plot V od =(V o1 -V o2 ) vs. V id, with V ic =0.9 V over the range 1.8 < V id < +1.8 V. * hw3, 1: diff pair w/ ideal tail current V V od 1.2 M1 off, M2 on 1000m 800m 600m 400m 200m Voltages (lin) -200m 0 ~ -0.1 V ~ 0.1 V -400m -600m -800m M2 off, M1 on V m 0 500m Voltage X (lin) (VOLTS) V id W The slope around V id =0 V is A 2 dm = gmrout gmrd = k I RD = 14. L The curves limit when all of the current is switched to one side of the differential pair. When this happens, the differential voltage is I = 1.4 V. SS R D The voltage that this occurs at can be approximated by I SS RD V id = = 0.1V. g R m D It is also correct to find the exact point where one transistor turns off and the other takes 2ISS all of the current. This occurs for Vid = = 0.14 V. W k L

3 c) Plot V oc =(V o1 +V o2 )/2 vs. V ic, with V id =0 V over the range 0 < V ic < +1.8 V. V oc Voltages (lin) * hw3, 1: diff pair w/ ideal tail current This is an artifact of the ideal current source dropping the source voltage below ground. You do not have to worry about calculating this exact shape. V DD -(I SS R D )/2 = 1.1 V 200m 400m 600m 800m Voltage X (lin) (VOLTS) 1.8 V ic There are no breakpoints in this curve. The strange behavior near V oc =0 V is only an artifact of the ideal current source pulling the source voltage below ground. When V S <0 V, the source-bulk junction diode begins to be forward biased and starts to conduct current. This will not happen with any real implementation, and you do not have to worry about calculating this. d) Calculate A dm with V ic =0.9 V, V id =0 V. Over what range of V id will the gain remain high? Why does the gain drop off? A dm = gm( RD ro ) gmrd = = ( 140 V )( 10)( 70 )( 100 k) As calculated in part (b), the gain is high over the range of 0.1 V < V id < 0.1 V. The gain drops off because one of the transistors goes into cutoff.

4 e) Calculate A cm with V ic =0.9 V, V id =0 V. A cm gmrd 1+ ( 1+ χ ) g ( 2r ) m o =, and therefore the common- For an ideal current source, the output resistance is mode gain is, A = 0. cm r o f) Calculate R od with V ic =0.9 V, V id =0 V. R od 2( R r ) = 2( 100 k 1.4 M) = D o = 187 k Verify (d)-(f) with SPICE using the.tf analysis option.

5 * hw3, 3: diff pair w/ ideal tail current.model nch nmos level=1 tox=25 vto=0.5 kp=140e-6 lambda=0.1 gamma=0.5 phi=0.6 vdd vdd * set up common mode and differential inputs vic vic vid vid 0 0 e1 vi1 vic vid e2 vi2 vic vid * set up to measure output common mode e3 voc1 0 vo e4 voc voc1 vo rcm voc 0 1 rd1 rd2 m1 m2 iss vdd vo1 100k vdd vo2 100k vo1 vi1 s 0 nch w=10u l=1u vo2 vi2 s 0 nch w=10u l=1u s 0 14u.options post=2 nomod.probe dc vod=v(vo1,vo2) voc=v(voc).op.dc vid dc vic tf.alter.tf v(vo1,vo2) vid v(voc) vic.end **** mosfets subckt element 0:m1 0:m2 model 0:nch 0:nch id u u vgs m m vds m m Vds vth m m vdsat m m **** small-signal transfer characteristics v(vo1,vo2)/vid = Adm input resistance at vid = 1.000e+20 output resistance at v(vo1,vo2) = k Rod **** small-signal transfer characteristics v(voc)/vic = n Acm input resistance at vic = 1.000e+20 output resistance at v(voc) = 0.

6 The schematic for the circuit used in Problem is: vdd rd1 R od rd2 vo1 vo2 vi1 m m vi2 e1 vic s e2 vic iss voc e4 vid voc1 rcm vid e3

7 replace the I SS current source with a resistor which results in the same I currents when V ic =0.9 V and V id =0 V. VS V a) To get the same current, R SS = = = 16.5 k I 14 SS Since the current and source voltage are the same, V is also the same. V = 0.87 V b) Plot V od vs. V id with V ic =0.9 V over the range 1.8 < V id < 1.8 V. 1.6 * hw3, 2: diff pair w/ tail resistor V od M1 off, M2 on 1.4 V 1000m 800m 600m 400m Voltages (lin) 200m 0-200m ~ -0.1 V ~ 0.1 V -400m -600m -800m V M2 off, M1 on m 0 500m Voltage X (lin) (VOLTS) V id Differentially, this circuit behaves the same way as the circuit with an ideal current source. Therefore the breakpoints are the same as before: V id = ± 0.1V, V = ± 1.4 V od When V id is increased beyond this range, the current increases causing a small slope in the transfer function. This can be approximated by a flat line and the exact shape is not important.

8 c) Plot V oc vs. V ic with V id =0 V over the range 0 < V ic < +1.8 V. * hw3, 2: diff pair w/ tail resistor 1.8 V oc = 1.8 V V oc V ic = 0.5 V Voltages (lin) m 900m 800m 700m 600m 500m 400m V oc = V V ic = 1.16 V 0 200m 400m 600m 800m Voltage X (lin) (VOLTS) V ic The equivalent half-circuit is V DD R D V oc 10 1 V ic 2R SS When V ic < V T, the transistor is operating in cutoff and the output is at V DD =1.8 V. When V ic > V T, the transistor operates as a common-source with source-degeneration amplifier until it goes into triode. We need to find the point where this occurs. At the edge of saturation,

9 V = V AT V DD I ( R + 2R ) = D SS 2I W k L 2 ( RD + 2RSS ) I + I VDD = 0 W k L Solving the quadratic equation, I = 12.5 µa, and V = V. Therefore, V S = I ( 2 RSS ) = V, and V T = V. So, the transistor goes from saturation to triode at the point, AT V ic = V S + V T + V AT = 1.16 V V oc = V S + V AT = V d) Since the differential half-circuit is exactly the same as with the ideal tail current source, this is the same as in (3d). A dm = gm( RD ro ) = 14 and the gain is large over the range 0.1 V < V id < 0.1 V. The gain drops off because one of the transistors goes into cutoff. e) The common-mode gain is slightly different due to the source resistor. where A cm gmrd = = 2 1+ ( 1+ χ ) g ( 2R ) g m = 140 µs m SS γ χ = 2( 2φ + V ) = 1 2 SB f) The differential output resistance is the same as in (4f), R od 2 ( R r ) = 187 kω = D o

10 * hw3, 4: diff pair w/ tail resistor.model nch nmos level=1 tox=25 vto=0.5 kp=140e-6 lambda=0.1 gamma=0.5 phi=0.6 vdd vdd * set up common mode and differential inputs vic vic vid vid 0 0 e1 vi1 vic vid e2 vi2 vic vid * set up to measure output common mode e3 voc1 0 vo e4 voc voc1 vo rcm voc 0 1 rd1 vdd vo1 100k rd2 vdd vo2 100k m1 vo1 vi1 s 0 nch w=10u l=1u m2 vo2 vi2 s 0 nch w=10u l=1u rss s k.options post=2 nomod.probe dc vod=v(vo1,vo2) voc=v(voc).op.dc vid dc vic tf.alter.tf v(vo1,vo2) vid v(voc) vic.end **** mosfets subckt element 0:m1 0:m2 model 0:nch 0:nch id u u vgs m m vds m m Vds vth m m vdsat m m **** small-signal transfer characteristics v(vo1,vo2)/vid = Adm input resistance at vid = 1.000e+20 output resistance at v(vo1,vo2) = k Rod **** small-signal transfer characteristics v(voc)/vic = Acm input resistance at vic = 1.000e+20 output resistance at v(voc) = 0.

11 The schematic for the circuit used is: vdd rd1 R od rd2 vo1 vo2 vi1 m m vi2 e1 vic s e2 vic rss voc e4 vid voc1 rcm vid e3

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