CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

Size: px

Start display at page:

Download "CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators"

Suzan Walker
6 years ago
Views:

1 IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater or smaller than zero, or to compare the value of one signal to another. The second most widely used components after amplifiers. Widespread use in A/D converters, data transmission, switching power regulators. Using an opamp for a comparator: too slow but a good example to discuss design principles for minimizing V OS and charge injection. Other approaches: multistage comparators, positive-feedback track-and-latch comparators, fully differential comparators.

2 IsLab Analog Integrated ircuit Design OMP-2 Using An Opamp for A omparator Using an open-loop opamp for a comparator. Slow response time due to slewing and settling time. A simple approach. V OS Limited resolution due to V OS of 2 5 mv for typical MOS processes. IsLab Analog Integrated ircuit Design OMP-3 Switched-apacitor omparator Operation: reset phase ( ) comparison phase ( ). is a slightly advanced version of so that charge-injection effects are reduced to the effect due to only the switch. The opamp must be stable for unity-gain feedback during. The bottom plate of integrated capacitors has more significant parasitic capacitance between it and substrate than the top plate.

3 IsLab Analog Integrated ircuit Design OMP-4 Therefore, the bottom plate is always connected to the less sensitive node rather than critical node. Although used in early ADs, this opproach is not preferable nowadays due to slow operation (500 Hz). A technique for speeding up (50 times) the comparision time is to disconnect the compensation capacitor during the comparision phase. The input capacitor is never charged or discharged during operation, v remains at 0 V. Use a reasonably large to minimize charge injection and clock-feedthrough effects. If and of switches attached to the bottom plate interchanged, the comparision operation would be noninverting. But must be charged or discharged during reset phase. IsLab Analog Integrated ircuit Design OMP-5 ancelling Input-Offset Voltage Errors The reset phase. V OS V OS The comparision phase. V OS V OS

4 IsLab Analog Integrated ircuit Design OMP-6 harge-injection Errors harge injection (clock feedthrough): unwanted charges is injected into the circuit when the transistors turn off. The comparator with switches: channel charge overlap. ov3 ov1 Q 1 v 1 v 2 Q 3 Q 2 ov2 IsLab Analog Integrated ircuit Design OMP-7 hannel charge: V DS = 0. Q ch = WL ox (V GS V t ) When Q 3 turns off: v 2c (channel charge) v 2o (overlap ). v 2c = Q ch/2 v 2o = v GS3 ov3 ov3 = oxw 3 L 3 V eff3 2 = (V DD V SS ) ov3 ov3 = oxw 3 L 3 (V DD V tn ) 2 v GS3 v 2 ov3 Resolution v = v 2c v 2o = 23 mv

5 IsLab Analog Integrated ircuit Design OMP-8 Making harge-injection Signal Independent When Q 2 turns off, its charge injection causes a negative glitch at v 1, but this will not cause any change in the charge stored in since the right side of is connected to an open node (no current flow). i = dv dt = 0, v = v 2 v 1 = 0 Thus, v 2 is unaffected by the charge injection of Q 2. When Q 1 turns on, v 1 will settle to regardless of the charge injection of Q 2. The charge injection of Q 1 has no effect due to similar reason. By turning off first, the circuit is affected only by the charge injection of Q 3. And the charge injection is signal independent. IsLab Analog Integrated ircuit Design OMP-9 A lock Generator with Advanced Phases Nonoverlapping two-phase clock with phases advanced by two inverter delays. φ a

6 IsLab Analog Integrated ircuit Design OMP-10 Minimizing Errors Due to harge Injection The simplest way is to use larger capacitors, but this would require a large amount of silicon area: v 1/. Integrated capacitors have parasitic capacitances between the bottom plate and the substrate. This bottom plate capacitance might be about 20% of the size of the realized capacitor. This capacitor would have to be driven by the input circuits, which would slow down the circuits. A top plate capacitance also exists due primarily to interconnect capacitance, but it is typically on the order of 1 to 5% of the realized capacitance. IsLab Analog Integrated ircuit Design OMP-11 A fully differential switched-capacitor comparator: the charge injection of Q 3a matches that of Q 3b v /10. Q 1 Q 3a Q 2 Q 3b Q 3 Q 4

7 IsLab Analog Integrated ircuit Design OMP-12 A multistage switched-capacitor comparator: error voltage storing ( ) eliminating ( ), the uncompensated error voltage in the input of the last stage v n, v 1 = charge injection offset, input equivalent error voltage (57 µv), refer to clock waveforms. v 1 ( 1 ) = A 1 ( v 1 ) = v 2, v 1 ( ) = A 1 ( v 1 ) v 2 ( ) = v 1 ( ) v 2 = A 1 ( v 1 ) A 1 v 1 = A 1 ( = A 2 (v 2 v 2 ) = A 1 A 2 v ) 2 v n = A 1 A 1 A 2 A n1 1 v 1 v 1 v 2 A A 2 IsLab Analog Integrated ircuit Design OMP-13 Speed of Multistage omparators A multistage comparator using a cascade of inverters: very high resolution as combining with fully differential design techniques. Although the multistage comparator has speed limitation due to multiphase clock, it can be reasonably fast and stable because of high-speed individual stages that have only a 90 phase shift. The parasitic load capacitance of the ith stage: except for the last stage, pi o,i gs,i1 < 2 gs,i for large W if gs o, r. A 1 p1 A 2 p2 A 3 p3

8 IsLab Analog Integrated ircuit Design OMP-14 The unity-gain frequency of a single stage i: L = 2 gs,i. ω ti g mi = ω T 2 gs,i 2 The transfer function of a single stage: dominant-pole approximation. A i (s) A 0i 1 s/ω pi, ω pi ω ti A 0i The overall transfer function of an n-stage comparator. A(s) = A0i A i (s) 1 s A n 0 1/ω pi 1 sn/ω pi The overall time constant of an n-stage comparator. τ n ω pi = 2nA 0 gs g m 4nA 0L 2 3µ n V eff 4 ns IsLab Analog Integrated ircuit Design OMP-15 Latched omparators A modern high-speed comparator: preamp track-and-latch stage. v L v L Preamplifier v o v o v i v i v L v L track and latch

9 IsLab Analog Integrated ircuit Design OMP-16 Preamplifiers: low gain (4 10) for high speed, used for higher resolution and reduction of kickback effects. Kickback denotes the charge transfer either into or out of the inputs when the TAL stage goes from track mode to latch mode. Without a preamplifier, cause very large glitches in the input circuit, especially when the input impedances are not perfectly matched limited accuracy. The track-and-latch stage: amplifies the signal further during the track phase, and then amplifies it again during the latch phase by positive feedback minimizes the total number of gain stages. Hysteresis might be eliminated by connecting internal nodes to one of power supplies or by connecting differential nodes together (no memory). For high resolution, coupling capacitors and reset switches are included to eliminate any V OS and v errors. IsLab Analog Integrated ircuit Design OMP-17 Latch-Mode Time onstant Two back-to-back inverters as a simplified model of a TAL stage in the latch phase. The inverters can be modelled as a VS driving an R load for v x v y. v y v x v x R L L A v R L v y R L L A v R L v x Node equations by KL: τ L = R L L, v v x v y. dv x τ L dt v x A v v y = 0, ( τl A v 1 ) ( d v dt dv y τ L dt v y A v v x = 0 ) = v

10 IsLab Analog Integrated ircuit Design OMP-18 Voltage difference between the output voltages of inverters. v = v 0 e (A v1)t/τ L v 0 e t/τ Latch-mode time constant: L k 1 WL ox, G m k 2 g m. τ = τ L A v 1 R L L A v = L = k 1 L 2 = (2 4) G m k 2 µ n V eff L 2 µ n V eff The latch time for a voltage difference v v L (valid logic voltage) the speed would be limited by preamplifiers and TAL during track phase. ( ) vl t latch = τ ln 0.5 ns 1 GHz v 0 If v 0 is small, the rise time can be larger than the allowed time for the latch phase undetermined logic value for succeeding circuitry. This is called metastability. Even when v 0 is large enough, circuit noise can cause v 0 to become small enough to cause metastability. IsLab Analog Integrated ircuit Design OMP-19 A Two-Stage omparator with Digital Output Low-impedance nodes and diode-connected loads for high speed, precharging nodes to eliminate hysteresis, fully differential comparator. Preamplifier Latch Digital output Positive feedback Latch

11 IsLab Analog Integrated ircuit Design OMP-20 A Two-Stage omparator with apacitive oupling apacitive coupling to eliminate V OS and charge-injection errors: resolution v < 0.1 mv at a 2-MHz clock frequency for 5-µm technology. MFB circuitry Positive feedback Track Track First S gain stage Second gain stage IsLab Analog Integrated ircuit Design OMP-21 Homework Problems: 7.1, 7.6, 7.7, 7.8, Describe the operation principle and the important properties of the comparator used in [1]. References [1] Y. T. Wang and B. Razavi, An 8-Bit 150-MHz MOS A/D onverter, IEEE J. of Solid-State ircuits, vol. 35, no. 3, pp , [2] A. Worapisher, J. B. Hughes, and. Toumazou, Speed and accuracy enhancement techniques for high-performance switched-current comparators, IEEE J. of Solid-State ircuits, vol. 36, no. 4, pp , 2001.

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually