Master Degree in Electronic Engineering. Analog and Telecommunication Electronics course Prof. Del Corso Dante A.Y Switched Capacitor

Transcription

1 Master Degree in Electronic Engineering TOP-UIC Torino-Chicago Double Degree Project Analog and Telecommunication Electronics course Prof. Del Corso Dante A.Y Switched Capacitor Working Principles and Filters application Switched capacitor technique as filtering implementation and filter design (TI MF10) Paolo Vinella s

2 1. Switched Capacitor Basics SUMMARY OF GOALS: From traditional resistors to switched capacitor approach Device building up 2

3 Realizing a RESISTOR inside an IC Resistors essential building blocks in analog/digital circuits (voltage splitting, current limiting, ) Inside integrated circuits Diffused Integrated Resistor: uniformly doped silicon area with ohmic metallic contacts: t ρ = f ( μ n, N D ) W L 1 RESISTIVITY: ρ= q μ n N RESISTANCE: R = ρ L D t W Manufacturers consider the following parameters: LAYER RESISTANCE: R = ρ t RESISTANCE: R = R L W Nowadays, strict IC available surface & scaling constrains: this approach very space (surface) consuming! 3

4 Solution: SWITCHED CAPACITOR Inside CMOS-based IC, realizing a CAPACITOR and having a CLK source is like pizza for Italians C P1, C P2 up to 30%C 1! Traditional resistor replaced by SWITCHED CAPACITOR (SC) approach: capacitor driven alternatively by two switches between power supply sources: R I S1 S2 I S1 CLOSED S2 OPENED Q 1 = C V 1 V1 V2 V1 C V2 S1 OPENED S2 CLOSED Q 2 = C V 2 I = V 1 V 2 R CHARGE VARIATION: Q = Q 1 Q 2 = C (V 1 V 2 ) CURRENT: I = Q T = C (V 1 V 2 ) T = C V 1 V 2 f CLK 4

5 SWITCHED CAPACITOR: a resistor-like device! Comparing the two expressions of currents previously found we get: R EQ = 1 C f CLK 1 R EQ I 12 2 f CLK : clock signal (switching) speed C: nominal value of the capacitance GOLDEN RULE: A capacitor, connected alternatively between two low-impedance points (two voltage sources) driven by two switches, behaves like a resistor put between these two points VERSATILE: function of clock frequency SMALL: C=5pF ; f CLK =100kHz R EQ = 2MΩ A SAMPLED SYSTEM: suitable for signals with frequency f S << f CLK (typical: ratio of 5 or more) Φ1 SWITCHES DRIVEN BY TWO-PHASES NON OVERLAPPING CLOCK digital signal Φ2 t t 5

6 SWITCHES: which device? CMOS devices are populated by MOSFET: we can use them as switches (ohmic area). OFF near GΩ ; ON tenth of Ω BASIC SWITCH: single nmos or pmos Φ Φ Φ TRANSMISSION GATE: reduced and constant R ON (V DS - independent) Φ Device turned ON : ohmic region for both nmos and pmos G ON = K V AL V tn + V tp R ON K Kn = μ n C OX Wn Ln = K p = μ p C OX Wp Lp 6

7 2. Switched Capacitor in basic FILTERS SUMMARY OF GOALS: Low-Pass passive cell Low-Pass active cell: Integrator Stray-Capacitive Insensitive circuits 7

8 Basic application: 1 st Order LP passive cell Simply replace the resistor of the RC LP cell with a capacitor: only capacitances in the circuit! S1 S2 R= 1 C 1 f CLK Φ v i C1 C2 v o v i C2 v o TRANSFER FUNCTION: H s = src 2 = 1 1 CUT-OFF FREQUENCY: f C C = = s 2 2πRC 2 2π C 1 f CLK C 1 f C CLK 2 H(j2πf) db 0 H(j2πf) 90 20dB/dec 0 f C f 0.1f C C f 10f C f f C depends on RATIO among two capacitances f C tunable varying the frequency f CLK of the signal Φ 8

9 1 st Order LP active cell: Integrator The circuit behaves as analog integrator, offering a LP transfer function plus some gain CAREFUL at high f! C2 C2 v i R1 + v o v i Φ1 C1 Φ2 + v o TRANSFER FUNCTION: H s = Z c H s = Z RR 1 C2 C 1 f CLK H s = 1 C 1 s f C CLK 2 CUT-OFF FREQUENCY: f C = 1 2π C 1 C 2 f CLK H(j2πf) db H(j2πf) C 1 C 2 f CLK 20dB/dec 90 f C f f SAME BENEFITS AS BEFORE! 9

10 Integrator-like behavior: WHY?! CONSIDERING TRADITIONAL (R) CIRCUIT: v i CONSIDERING SWITCHED CAPACITOR EQUIVALENT CIRCUIT: reason in terms of charge transfer from input to output! Every clock cycle: 1. Φ1 active: C1 absorbs a charge Q=C 1 v i 2. Φ2 active: same charge moved away from C1 to C2 Assuming v i =V i =const, during Φ2 the output changes by C 1 V i / C 2 each clock cycle: Vo= Q C 2 = C 1 C 2 V i V i S 1 R1 C1 S 2 I I + C2 C2 V O v o On feedback branch: I(t)= dq t dt Q c t =C 2 v c (t) but this is the input current! v i (t) R 1 = C 2 dvo dt V O C 1 C 2 V i t I(t)=C 2 dvc dt v o t vo 0 v c = v o dvo = 0 t vi t R 1 C 2 dt vo t = vo 0 1 R 1 C 2 0 t v i t dt I(t)= C 2 dvo dt Approximate the staircase waveform with a ramp: the circuit behaves as an integrator! Final value of V o after every k clock cycle T CK : Vo(kT CK ) = Vo[(k 1)T CK ] V i [(k 1)T CK ] C 1 C 2 10

11 Limitation: parasitic capacitances! Both C1 and C2 realized within the same integrated circuit: they exhibit parasitic components towards ground at both pins! C P21 C P22 C2 Ideal behavior of the device clearly v i Φ1 C1 Φ2 + v o influenced by parasitic: charge dispersion! C P11 C P12 All critical? NO, only C P11! C P12 between GND and GND: no effect! C P21 between virtual GND of the OPAMP and GND: no effect! C P22 in parallel to (driven by) v O : no effect on C2 charge! C P11 in parallel with C1 => the real C1 is C1+C P11 : problematic! we can do better. Let s see how 11

12 4-switch cell: an help we need IDEA: to avoid influence of parasitic let s try to put C1 in series instead of parallel use 4-switch CELL C Φ1 Φ1 output MUST v I O i see a GND! Φ2 Φ2 Still seen as equivalent resistor: 1. Φ1 active: C charges with Q=C v i 2. Φ2 active: C discharged to GND. We take I o f CLK /sec times I O =Qf CLK Req = v i I 0 R EQ = 1 C f CLK SAME RESULT! INVERTING 4-SWITCH CELL: exchange position of Φ1 and Φ2 in output branch: now I O =-Qf CLK (current with opposite sign) 12

13 Stray Insensitive Active Integrator Plug the 4-switch CELL inside the active integrator: C2 C1 v i Φ1 Φ1 + v o Φ2 Φ2 We get rid of parasitic effects! C P21 C P22 C P11 C P12 C2 C1 v i Φ1 Φ1 + v o Φ2 Φ2 13

14 Non-Inverting Active Integrator Using the INVERTING 4-switch CELL we can realize a NON-INVERTING integrator: C2 C1 + v i Φ1 Φ2 v o Φ2 Φ1 It overcomes the inverting limitation of the standard integrator! 14

15 3. Switched Capacitor in COMPLEX FILTERS SUMMARY OF GOALS: II Order Filters recall Tow-Thomas (State Variable) filter with SC IC Texas Instrument TI MF-10 implementation 15

16 II order filters: recall (1) BAND-PASS LOW-PASS HIGH-PASS 16

17 II order filters: recall (2) NOTCH ALL-PASS 17

18 II order filters: recall (3) BANDPASS LOWPASS HIGH-PASS NOTCH ALL-PASS 18

19 State Variable Filter: recall Device Block Diagram: V i A 0 A 1 V 0 V 1 Σ -1 -A 2 V A 1 A 2 V A B 0 B 1 B 2 Circuital implementation: V LP V BP V HP 19

20 Commercial SC Active Filter: Texas Instrument MF10 2 filter blocks (A and B) general purpose (State-Variable filters) up to 4 th order filters Can realize any filter response type (Butterworth, Bessel, Cauer and Chebyshev) Each BLOCK: LP, BP, HP, N, A.P (called MODES OF OPERATION): Mode BP LP HP N AP No. of Resistors Adjustable f CK /f 0 1 * * * 3 No 1a H OBP1 = Q H OBP2 = +1 H OLP No f 0 dependent on CLK ; Q MAX depends on MODE (up to 150) Notes May need input buffer. Poor dynamics for high Q. 2 * * * 3 Yes (above f CK /50 or f CK /100) 3 * * * 4 Yes Universal State-Variable Filter. Best general-purpose mode 3a * * * * 7 Yes As above, but also includes resistor-tuneable notch 4 * * * 3 No Gives Allpass response with H OAP = 1 and H OLP = 2 5 * * * 4 Gives flatter allpass response than above if R 1 =R 2 = 0.02R 4 6a * * 3 Single pole 6b HOLP1 = +1 HOLP2 = -R3/R2 2 Single pole f 0 Q Range up to khz Operation up to khz ; CLK up to MHz Consider LP filter at output Supply ±7V or +14V. Can source 3 ma and sink 1.5 ma 20

21 Inside the TI MF10: periphery Digital and Analog positive power supplies (can be tied together) Notch/AllPass/HighPass output Used in AllPass (input to S1 then switch 1 points to LP out (that is, no filtering: simple short!) BP output LP output Input Vi Clock input to drive upper filter Defines f CLK /f 0 ratio Defines supply for MF10 INTEGRATORS (driven by CK) connects one of the inputs of each filter's second summer to either GND or LP output Digital and Analog negative power supplies (can be tied together) 21

22 Inside the TI MF10: State Variable Filters Standard State Variable Filter is replicated in two independent blocks A and B: BLOCK A BLOCK B Set up some PINs to get the standard Double Integrator (LP + BP + HP) corresponding to MODE 3: 22

23 Design example: Mode #3 (BP, LP, HP) Design extremely simple 1) Set some pins to «HI» or «LO» to select mode of operation 2) Choose external resistors to realizefilter with desired parameters Design equations for MODE#3: f 0 = f CLK 100 R2 R4 or f 0 = f CLK 50 R2 R4 ; Q= R2 R4 R3 R2 H 0 =HP gain HP f f CLK 2 = R2 R1 H 0 BP =BP gain f=f 0 = R3 R2 H 0 LP =LP gain f 0 = R4 R1 23

24 Design example: Fourth Order Chebyshev LP filter As simple as previous case 1) Set some pins to «HI» or «LO» to select mode of operation 2) Choose external resistors to realizefilter with desired parameters (look at tables for Chebyshev parameters) How final circuit looks like: CASCADING: connect LP A output to input INV B through input resistance R1B of block B Output taken from LP B pin Input fed to block A Same CLK for both filter blocks! 24

25 4. Final REMARKS SUMMARY OF GOALS: Traditional vs Switched Capacitor filters Final brainstorming 25

26 Traditional vs S.C. filters: which one? Tradeoff! SWITCHED CAPACITOR FILTER ACCURACY f0 clk deviation 0.2% TRADITIONAL ( CONTINUOUS TIME ) FILTER Must use very accurate resistors, capacitors, and sometimes inductors, or trim component COST inexpensive for complex design Basic: easy (RC one-pole filter fast to build) Growing complexity/accuracy: cost increases NOISE OFFSET VOLTAGE FREQUENCY RANGE TUNABILITY SC Filter use integrators: small capacitors but high τ large input resistor required higher thermal noise! clock feed through Quite high: up to 1V. Not good for precise DC applications Typically 0.1Hz to 100kHz Just change fclk (variations up to 5 6 dec) very little noise (just thermal noise of resistors) Offset of OPAMP and of filter stages can be optimized (less than 1mV) large and expensive reactive components if work at low frequencies to change f0 tunable components needed COMPONENT COUNT / PCB AREA ALIASING DESIGN EFFORT single monolithic filter, outside few resistors + CLK sampled-data devices: AA filter at input + LP filter at output a capacitor or inductor per pole, more devices for active filters Just requency limitations due to OPAMP Nowadays, software tools (like WEBENCH Active Filter Designer): less manual efforts 26

27 Thanks for your attention! 27