Nyquist-Rate A/D Converters
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1 IsLab Analog Integrated ircuit Design AD-51 Nyquist-ate A/D onverters כ Kyungpook National University IsLab Analog Integrated ircuit Design AD-1 Nyquist-ate MOS A/D onverters Nyquist-rate : oversampling AD. A/D converter architectures. Low-to-medium speed Medium speed High speed High accuracy Medium accuracy Low-to-medium accuracy Integrating Successive approximation Flash Oversampling Algorithmic Two-step Interpolating Folding Pipelined Time-interleaved
2 IsLab Analog Integrated ircuit Design AD-2 Integrating A/D onverters A popular approach for high accuracy and low speed. Very low offset and gain errors. Highly linear. Small amount of circuitry in implementation. Usage in voltage or current meters. Dual-slope integrating converters. IsLab Analog Integrated ircuit Design AD-3 Dual-Slope Integrating onverters Phase I: For a fixed interval T 1 = 2 N T clk, switch S 1 is connected to such that V x is given by V x (t) = t dt = 1 1 t Phase II: For a variable interval T 2, switch S 1 is connected to V ref such that V x is decaying in a constant slope. V x (t) = V x (T 1 ) t V ref dt = T 1 V ref (t T 1 ) T If V x equals to 0 when t = T 1 T 2, T 2 is related to T 1 by T 2 T 1 = V ref = B out2 N T clk 2 N T clk = b b b N 2 N
3 IsLab Analog Integrated ircuit Design AD-4 A dual slope A/D converter. S 2 S 1 S 2 B out V ref S V x omparator ontrol logic ounter V x V 3 lock Phase I V 2 V 1 Phase II T 1 T 1 T 2 t Design of 1 and 1 for a large peak value of V x to reduce noise. IsLab Analog Integrated ircuit Design AD-5 A dual-slope converter does not suffer from gain error, but it can have an offset error quad-slope: first ground, next signal. Low speed: 2 N1 clock cycles in the worst-case conversion. T 1 = an integer multiple of 1/(60 Hz) or (.67 ms) to attenuate the power line noise. = (ideal) (60 Hz) = (ideal) A sin(120πt φ) V x (t) = T dx = T1 0 (ideal) 1 1 dx T1 0 (60 Hz) dx 1 1 Effective input filtering for integrating-then-reset behavior h(t) = a square pulse of length T 1. H(f) = sin(πf T 1 ) πf T 1 = 20 db/decade for side lobes
4 IsLab Analog Integrated ircuit Design AD-6 Successive-Approximation onverters One of the most popular approaches. Quick conversion time and moderate circuit complexity. Operation by binary search algorithm. Determination of the closest digital word to match an input signal. DA-based successive-approximation AD. harge-redistribution AD. esistor-capacitor hybrid AD. IsLab Analog Integrated ircuit Design AD-7 Bipolar Successive-Approximation Algorithm void SaAdc( n, b, vin, vref ) int n, /* resolution of AD */ b[]; /* offset binary code of result */ float vin, /* input voltage ( vref) */ vref; /* reference voltage */ { int i; float vda = 0.0; /* output voltage of D/A converter */ for ( i = 0; i < n; i ) { if ( vin >= vda ) { b[i] = 1; vda = vda vref / pow( 2, i1 ); } else { b[i] = 0; vda = vda - vref / pow( 2, i1 ); } // equivalent statements } // vda = vda - vref / pow( 2, i ); // b[i] -> 0 } // vda = vda vref / pow( 2, i1 );
5 IsLab Analog Integrated ircuit Design AD-8 Successive-Approximation Diagram V V bit IsLab Analog Integrated ircuit Design AD-9 Unipolar Successive-Approximation Algorithm void UniSaAdc( n, b, vin, vref ) int n, /* resolution of AD */ b[]; /* offset binary code of result */ float vin, /* input voltage (< vref) */ vref; /* reference voltage */ { int i; float vda = vref / 2; /* output voltage of D/A converter */ for ( i = 0; i < n; i ) { if ( vin >= vda ) { b[i] = 1; vda = vda vref / pow( 2, i2 ); } else { b[i] = 0; vda = vda - vref / pow( 2, i2 ); } // equivalent statements } // vda = vda - vref / pow( 2, i1 ); // b[i] -> 0 } // vda = vda vref / pow( 2, i2 );
6 IsLab Analog Integrated ircuit Design AD-10 DA-Based Successive-Approximation AD Unipolar input signal. S/H for unchangeable input signal during one-bit conversion. omparator successive-approximation register (SA). ontrol logic DA. DA determines the accuracy and speed of the AD. N clock cycles to complete an N-bit conversion. IsLab Analog Integrated ircuit Design AD-11 A DA-based successive-approximation A/D converter. S/H SA ontrol logic B out V D/A D/A converter
7 IsLab Analog Integrated ircuit Design AD-12 harge edistribution in Switched apacitors Initial charges: q 1 = 1 (v a v c ), q 2 = 2 (v b v c ). harge redistribution: v b v d. q 1 = q 1 q = 1 (v a v x ), q 2 = q 2 q = 2 (v d v x ) harge conservation and voltage change: q 1 q 2 = q 1 q 2. (v x f(v a ), v b = 0, v c = V OS, v d = V ref, 1 = 2 ) v x = v c 2 (v d v b ) = V OS V ref v c v x v a q 1 q 2 v b v d 1 2 IsLab Analog Integrated ircuit Design AD-13 Unipolar harge-edistribution A/D onverter A single circuit: S/H DA subtraction. Input signal: 0 < V ref. Error signal V x ( V D/A ): always compared to ground. Sample mode: All capacitors are charged to while the comparator is being reset to its offset voltage. Hold mode: The comparator is taken out of reset by opening S 2, and then all capacitors are switched to ground. Finally, S 1 is switched so that V ref can be applied to the capacitor array during bit cycling. Bit cycling: The largest capacitor 8 is switched to V ref. V x now goes to V OS V ref /2. If V x V OS ( V ref /2), then this capacitor is left connected to V ref and b 1 = 1.
8 IsLab Analog Integrated ircuit Design AD-14 Otherwise, this capacitor is reconnected to ground (V x = V OS ) and b 1 = 0. This process is repeated for the smaller capacitors to finish the conversion offset voltage cancellation. Parasitic capacitance at node x does not cause conversion errors. Bottom plates of capacitors should be connected to V ref side. A 4-bit unipolar charge-redistribution AD. Sample mode: V x = V OS S SA b 1 b 2 b 3 b 4 S 3 S 1 V ref IsLab Analog Integrated ircuit Design AD-15 Hold mode: V x = V OS S SA b 1 b 2 b 3 b 4 S 3 S 1 V ref Bit cycling: V x = V OS V ref /2 S SA b 1 b 2 b 3 b 4 S 3 S 1 V ref
9 IsLab Analog Integrated ircuit Design AD- Bipolar Successive-Approximation by Divided emainder void DiSaAdc( n, b, vin, vref ) int n, /* resolution of AD */ b[]; /* offset binary code of result */ float vin, /* input voltage ( vref) */ vref; /* reference voltage */ { int i; float vda = - vin; /* divided remainder */ for ( i = 0; i < n; i ) { if ( vda <= 0.0 ) { b[i] = 1; vda = vda vref / pow( 2, i1 ); } else { b[i] = 0; vda = vda - vref / pow( 2, i1 ); } // equivalent statements } // vda = vda - vref / pow( 2, i ); // b[i] -> 0 } // vda = vda vref / pow( 2, i1 ); IsLab Analog Integrated ircuit Design AD-17 Signed harge-edistribution A/D onverter Input signal: V ref /2 < V ref /2. Using only a single reference voltage. Sample mode: All capacitors, except for the largest capacitor, are charged to while the comparator is being reset to its offset voltage. The largest capacitor is now connected to V ref /2. Hold mode: The comparator is taken out of reset by opening S 2, and then all capacitors, except for the largest capacitor, are switched to ground. The sign of the input signal is determined by looking at the comparator output. Finally, S 1 is switched so that V ref /2 can be applied to the capacitor array during bit cycling.
10 IsLab Analog Integrated ircuit Design AD-18 Bit cycling: If V x V OS, then is positive and b 1 is set to 1, and conversion proceeds as in the unipolar case, starting with b 2. The largest capacitor 8 is switched to ground if is negative. This is level shift operation causing V x to become V OS /2 V ref /4 (which is a negative value since V ref /2). And conversion proceeds as in the unipolar case, starting with b 2. educed S/N ratio by using /2 in the conversion process. Any error in the MSB capacitor causes both an offset and a sign-dependent gain error due to level shift for < 0. onversion results expressed in offset binary code digital recoding. A 4-bit signed charge-redistribution A/D converter. IsLab Analog Integrated ircuit Design AD-19 Sample mode: V x = V OS S SA b 1 V ref /2 b 2 b 3 b 4 S 3 S 1 V ref /2 Hold mode: V x = V OS /2 S SA b 1 V ref /2 b 2 b 3 b 4 S 3 S 1 V ref /2
11 IsLab Analog Integrated ircuit Design AD-20 0 Bit cycling: V x = V OS /2 V ref /8 < 0 Level shift (b 1 0): V x = V OS /2 V ref /4 Bit cycling: V x = V OS /2 V ref /4 V ref /8 = V OS /2 V ref /8 S SA b 1 V ref /2 b 2 b 3 b 4 S 3 S 1 V ref /2 IsLab Analog Integrated ircuit Design AD-21 esistor-apacitor Hybrid A/D onverter ombination of resistor string and capacitor array. Step 1: All the capacitors are charged to while the comparator is being reset. Step 2: The operation is performed to find the two adjacent resistor nodes that have voltages larger and smaller than. To find the smaller voltage node, charging all the capacitors to the voltage of each resistor-string node, check the comparator output for (V x = V OS V ri < V OS ) from the top node. Step 3: All the capacitors are charged to the lower voltage. Step 4: The successive approximation is performed by switching capacitors to the bus having the larger voltage.
12 IsLab Analog Integrated ircuit Design AD-22 A 6-bit resistor-capacitor hybrid A/D converter. V ref Step 1: V x = V OS Step 2: V x = V OS V ri < V OS Step 3: V x = V OS V L Step 4: V x = V OS V L (V H V L )/2 S i 4 2 S 2 SA SH b 1 b 2 b 3 S 3 S L IsLab Analog Integrated ircuit Design AD-23 Speed Estimate for harge-edistribution onverters Simplified model of a capacitor array during sampling time. s2 2 N1 2 N2 2 s1 vi Open-circuit time constant and charging time for better than 0.5-LSB accuracy (e T/τ < 0.5/2 N ) rough estimate for maximum sampling rate. τ = X i io i = ( s1 s2 )2 N 1 ω H, T > 0.69(N 1)τ
13 IsLab Analog Integrated ircuit Design AD-24 Algorithmic A/D onverter yclic or recirculating A/D converter. A small amount of analog circuitry. S/H amp 2x amp comparator subtraction circuit. An accurate multiply-by-two gain amp: sample the input signal twice using the same capacitor. Similar operation as SA converters: Whereas an SA converter halves the reference voltage in each cycle, an algorithmic converter doubles the error voltage while leaving the reference voltage unchanged. 8[ (b b b )V ref ] = 2[2(2 b 1 V ref ) b 2 V ref ] b 3 V ref 0 IsLab Analog Integrated ircuit Design AD-25 ode for A Bipolar yclic AD void yclicadc( n, b, vin, vref ) /* bipolar cyclic or algorithmic A/D converter */ int n, /* resolution of AD */ b[]; /* offset binary code of result */ float vin, /* input voltage ( vref) */ vref; /* reference voltage */ { int i; float vda = vin; for ( i = 0; i < n; i ) { if ( vda >= 0 ) { b[i] = 1; vda = 2.0 * vda - vref; // 2.0 * ( vda - vref/2 ) } else { b[i] = 0; vda = 2.0 * vda vref; // 2.0 * ( vda vref/2 ) } } }
14 IsLab Analog Integrated ircuit Design AD-26 A bipolar algorithmic A/D converter. S 1 S/H Amp omparator b i 2x Amp S 2 V ref /2 V ref /2 IsLab Analog Integrated ircuit Design AD-27 Multiply-by-Two Gain Amp for yclic onverters Phase 1: sample and V OS : v 1 = V OS, v 2 = V OS, v o = V OS. v 2 2 v 1 1 v o Phase 2: transfer charge q 1 to 2 : v 1 = V OS, v 2 = V OS 1 2, v o = 1 2. v 2 2 v 1 1 v o
15 IsLab Analog Integrated ircuit Design AD-28 Phase 3: sample again: v 1 = V OS, v 2 = V OS 1 2, v o = V OS. v 2 2 v 1 1 v o Phase 4: combine q 1 and q 2 on 1 : v 2 = V OS, q 2 = 2 v 2 = 1, v 1 = V OS q 2 = 2v i V 1 OS, v o = 2 independent of 1, 2, and V OS. v 2 2 v 1 1 v o IsLab Analog Integrated ircuit Design AD-29 Major Error Sources for S A/D onverters Offset voltage of op amps offset-cancellation method. apacitor mismatches ratio-independent technique. Finite gain of op amps gain-insensitive technique. lock feedthrough and charge injection dummy switches, MOS switches, and fully differential structures. φ s φ s v W 0.5W H 1 v o
16 IsLab Analog Integrated ircuit Design AD-30 Parallel A/D converters. Flash A/D onverters Standard approach for realizing very high speed: 8-b 500-MHz. A resistor string 2 N comparators an encoder. Fast but large area and power small clocked comparator using a MOS inverter (φ = 1: v = v r v, φ = 0: v g = v r v ). v r φ v Latch φ φ Output code = thermometer code: need of a code converter. Top and bottom /2 resistors for 0.5 LSB offset. v g IsLab Analog Integrated ircuit Design AD-31 A 2-bit flash A/D converter. V ref V DD /2 /2 0.5 LSB offset Overrange Thermometer-to-binary encoder b 1 b 2
17 IsLab Analog Integrated ircuit Design AD-32 Design Issues for Flash A/D onverters Input capacitive loading: A large parasitic load at the node due to the large number of comparators speed limit. esistor-string bowing: Errors in the voltages of the nodes of the resistor string due to the input currents of bipolar comparators. Signal and clock delay: Small differences in the arrival of clock or input signals at each comparators. It would only take 5 ps to change through 1 LSB for the case where a 250-MHz 1-V peak-input sinusoid is being encoded by an 8-bit A/D converter with V ref = 2 V usage of a high-speed S/H circuit which can be more difficult to realize than the flash converter itself. IsLab Analog Integrated ircuit Design AD-33 Substrate and power-supply noise: For V ref = 2 V and an 8-bit converter, only 7.8 mv of noise injection would cause a 1 LSB error clock shielding, running differential clocks closely together, separation of analog power supply from digital supply, on-chip power-supply bypassing (small resistors in series with bypass capacitors). Bubble error removal: A bubble of lone 1 or 0 will occur within a thermometer code due to comparator metastability, noise, crosstalk, limited bandwidth, etc 3-input NAND gate to remove a bubble. Flashback: When latched comparators are switched from track to latch mode, or vice-versa, there is charge glitch at the input to the latch. If there is no preamplifier, this will cause major errors due to the unmatched impedances at the comparator inputs (one input: resistor string other input: input signal).
18 IsLab Analog Integrated ircuit Design AD-34 Two-Step A/D onverters Two-step or subranging A/D converters. The most popular approach for high speed medium accuracy. Less silicon area, less power, less capacitive loading: 2 2 N/2 comparators (2 N comparators in N-bit flash converters). Less stringent resolution of comparators: N 2 bit accuracy. Larger latency delay for the first output. N 2 -bit MSB AD N 2 -bit DA 2N/2 gain amp N -bit LSB AD. 2 A 10-b 75-MHz 2-W subranging A/D converter in IsLab Analog Integrated ircuit Design AD-35 An 8-bit two-step A/D converter. S/H 4-bit MSB AD 4-bit DA V 1 Vq Σ Amp 4-bit LSB AD Higher 4 bits (b 1 b 2 b 3 b 4 ) Lower 4 bits (b 5 b 6 b 7 b 8 ) The reason for digital error correction is to significantly ease the requirements on the 4-bit MSB A/D converter (8 4-bit accuracy). is found by properly combining the digital values of V 1 and V q. = V 1 (4 bits) V q (5 bits) (gain = 8)
19 IsLab Analog Integrated ircuit Design AD-36 Interpolating A/D onverters Input comparators as linear amplifiers near threshold voltages. Interpolation between output voltages of two input comparators by a resistor string interpolating factor of M. eduction in the number of input comparators lower input capacitance, reduced power dissipation, lower number of accurate reference voltages created by a resistor string. Adding series resistors to equalize delay times to latch comparators. Interpolation by capacitors or current mirrors instead of resistor string. A 10-b 20-MHz 30-mW MOS AD in A 8-b 100-MHz 1.5-µm MOS AD in IsLab Analog Integrated ircuit Design AD-37 A 3-bit interpolating A/D converter with interpolating factor of 4. V ref = 1 V Latch comparators V 2 (Overflow) latch 8 latch 7 Input latch 6 comparators latch 5 V 1 latch 4 latch 3 latch 2 latch 1 Digital logic b 1 b 2 b 3
20 IsLab Analog Integrated ircuit Design AD-38 Possible transfer responses for input-comparator output signals. V V 1 V 2 Latch threshold Delay equalization by adding resistors and current interpolation by mirrors. latch /4 latch latch /4 latch 9 I I I I I I 2 9 latch elative widths shown IsLab Analog Integrated ircuit Design AD-39 Folding A/D onverters Folding architecture by analog preprocessing of folding blocks (FBs). The folding rate is the number of output transitions for single FB as is swept over input range number of bits in the converter. eduction in the number of latch comparators < 2 N (interpolating) Folding blocks realized using cross-coupled differential pairs. The MSB converter would usually be realized by combining FB signals (b 2 = V 1, b 1 = V c of transistor connected to V r2 in FB V 1 ) Frequency-multiplying effect of FBs limits the practical folding rate. Folding and interpolating AD: reduction in the number of FBs. An 80-MHz, 80-mW, 8-b MOS folding A/D converter in 1996.
21 IsLab Analog Integrated ircuit Design AD-40 A 4-bit folding A/D converter with a folding rate of 4. 2-bit MSB AD b 1 b 2 Folding-block response V ref = 1 V [ 1 4, 2 4, 3 4 ] V 1 Folding block V 1 Latch V = ˆ 4, 8, 12, V T V Folding block V 2 Latch V = ˆ 3, 7, 11, 15 Folding block V 3 Latch V = ˆ 2, 6, 10, 14 Digital logic b 3 b 4 V T V 3 V T V Folding block V 4 Latch V = ˆ 1, 5, 9, 13 V T IsLab Analog Integrated ircuit Design AD-41 Pipelined A/D onverters Pipelined AD: The first stage operates on the most recent sample while all other stages operate on residues from previous samples. Each stage: SHA, ADS, DA, subtracter. N clock latency for the first output: offset-binary code. High throughput rate: two clocks per conversion, low hardware cost. Gain amplifiers in the first few stages have most stringent accuracy. Digital error correction: redundancy (more bit per stage). Implementation by switched-capacitor S/H/Gain amplifiers.
22 IsLab Analog Integrated ircuit Design AD-42 A pipelined A/D converter. Stage 1 Stage 2 Stage N-1 Stage N D N1 D 2 D N1 D 1 D 2 D N1 Digital logic b N b N1. b 2 b 1 IsLab Analog Integrated ircuit Design AD-43 One stage of a pipelined A/D converter. S/H Σ 2 k v o k-bit AD k-bit DA k bits Transfer function of a 2.8-bit pipeline stage: log b. v o (V, V ) (V, V )
23 IsLab Analog Integrated ircuit Design AD-44 Error Sources in Pipelined ADs Offset and gain errors in S/H circuits and amplifiers. A/D subconverter nonlinearity. D/A subconverter nonlinearity. Op amp settling-time errors. Effects of gain, offset, and A/D subconverter nonlinearity are reduced or eliminated with digital error correction D/A subconverter nonlinearity and op amp settling-time errors limit the performance. The digital error correction postpones decisions on inputs that are near the A/D subconverter decision levels until the residues from these inputs are amplified to the point where similar nonlinearity in later A/D subconverters is insignificant. IsLab Analog Integrated ircuit Design AD-45 A 2-bit pipeline stage. S/H Digital Error orrection 2-bit AD 2 bits 2-bit DA Σ 4 v o Transfer functions: ideal and practical, error detection and correction (overrange: 10 1 = 11, v o V LSB, underrange: 01 1 = 00, v o V LSB ) v r v o (V, V ) 10 1 = 11 v o v r (V, V ) 01 1 = 00
24 IsLab Analog Integrated ircuit Design AD-46 eduction of the stage gain to detect the overrange: a factor of 2. ( 4 2, correction range = V /4) v o (V, V ) v o v r (V, V ) Addition of systematic offsets to eliminate the subtraction (AD offset shifts decision levels to the right, DA offset shifts transfer function down) S/H Σ 2 v o V 4 2 bits V 4 2-bit AD 2-bit DA IsLab Analog Integrated ircuit Design AD-47 Transfer functions with offsets and without the top decision level (a correctable error because correction range = V /4) v o (V, V ) v o (V, V ) (V, V ) (V, V ) A 1.5-bit pipeline stage: The digital correction and output coding is done by adding (i 1)th stage output to ith stage output with one bit overlap. (AD decision levels = V 4, V 4 ; DA voltage levels = V 2, 0, V 2 ) S/H Σ 2 v o 2 bits 1.5-bit AD 1.5-bit DA
25 IsLab Analog Integrated ircuit Design AD-48 orrection table for 6 regions of the transfer function: dotted line = last stage. (raw output a 1 a 2, correction c i from stage i 1, corrected output b 1 b 2 ) v o V V 2 V 4 V 2 V V V 2 V 4 0 V V V a 1 a 2 c i b 1 b 2 c i 1 0 raw outputs final output IsLab Analog Integrated ircuit Design AD-49 Time-Interleaved A/D onverters Very high speed A/D conversion. Parallel operation of many A/D converters. The input S/H amplifier is critical, sometimes realized in a different technology (GaAs S/H circuits). Mismatches in the channels will produces tones at f s /m. For example, consider a dc input signal in a time-interleaved converter where one converter has a dc offset of 100 mv. This converter will produce every fourth digital word different from other three. A 1-GHz 6-bit AD in 1987.
26 IsLab Analog Integrated ircuit Design AD-50 A four-channel time-interleaved A/D converter. φ 1 S/H N-bit AD φ 2 φ 0 S/H N-bit AD V i S/H φ 3 Digital MUX Digital output S/H N-bit AD φ 4 S/H N-bit AD IsLab Analog Integrated ircuit Design AD-51 Homework Modeling of the n-bit pipelined A/D converter with 1.5-bit stage by the language. What is the correction range for AD decision levels? Problems 13.2, 13.4, 13.7, 13.12, 13.14, eferences [1] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr.,. amachandran, and T.. Viswanathan, A 10-b 20-Msample/s analog-to-digital converter, IEEE J. of Solid-State ircuits, vol. 27, no. 3, pp , [2] G. hien, High Speed, Low Power, Low Voltage Pipelined Analog-to-Digital onverter, MS Thesis, U.. Berkeley, 1996.
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