EXAMPLE DESIGN PART 2

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1 ECE37 Advanced Analog Circuits Lecture 4 EXAMPLE DESIGN PART 2 Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca

2 Course Goals Deepen understanding of CMOS analog circuit design through a top-down study of a modern analog system a delta-sigma ADC Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that every competent designer ought to know. ECE37 4-2

3 Date Lecture (M 3:00-5:00) Ref Homework RS MOD & MOD2 ST 2, 3, A : Matlab MOD& RS 2 MODN + Σ Toolbox ST 4, B 2: Σ Toolbox RS 3 Example Design: Part ST 9., CCJM 4 3: Sw.-level MOD RS 4 Example Design: Part 2 CCJM TC 5 SC Circuits R 2, CCJM 4 4: SC Integrator TC 6 Amplifier Design Reading Week No Lecture TC 7 Amplifier Design 5: SC Int w/ Amp RS 8 Comparator & Flash ADC CCJM TC 9 Noise in SC Circuits ST C RS 0 Advanced Σ ST 6.6, 9.4 Project TC Matching & MM-Shaping ST , TC 2 Pipeline and SAR ADCs CCJM 5, Exam Proj. Report Due Friday April Project Presentation ECE37 4-3

4 NLCOTD: Non-Overlapping Clock Generator Our SC circuits require two non-overlapping clocks. How do we generate them?? ECE37 4-4

5 Highlights (i.e. What you will learn today) Transistor-level implementation of MOD2 op-amp, SC CMFB, comparator, clock generator 2 MOD2 variants 3 Variable quantizer gain ECE37 4-5

6 Review: MOD2 U Standard Block Diagram z z z Q E V NTF( z) = ( z ) 2 STF( z) = z Scaled Block Diagram U z X X 2 /3 /3 z z 9 Q V /3 /9 ECE37 4-6

7 Review: Schematic st -stage capacitor sizes set for SNR = 00 OSR = 500 and 3-dBFS input V ref = V and the full-scale input range is ± V. 2 nd -stage capacitor sizes set by minimum allowable capacitance ECE37 4-7

8 Review: Simulated Spectrum 0 20 SQNR = 05 OSR = dbfs/nbw Smoothed Spectrum 08-dBc 3 rd harmonic Theoretical PSD (k = ) 20 NBW=46Hz k 0k 00k Frequency (Hz) ECE37 4-8

9 Review: Implementation Summary Choose a viable SC topology and manually verify timing 2 Do dynamic-range scaling You now have a set of capacitor ratios. Verify operation. 3 Determine absolute capacitor sizes Verify noise. 4 Determine op-amp specs and construct a transistor-level schematic Verify. 5 Layout, fab, debug, document, get customers, sell by the millions, go public, ECE37 4-9

10 Effect of Finite Op Amp Gain Linear Theory Suppose that the amplifier has finite DC gain A. Define µ = A. To determine the effect on the integrator pole, let s look at our SC integrator with zero input: φ µq 2 C 2 C φ2 C2 φ2 φ A v = q 2 C 2 ( µc C 2 )q 2 ECE37 4-0

11 A fraction of q 2 leaks away each clock cycle: q 2 ( n + ) = ( ε)q 2 ( n), where ε = µc C 2 Thus, the integrator is lossy, with a pole at z = ε Q: How big can ε get before the effect becomes significant? z-plane: π OSR ε z = A: ε π OSR ECE37 4-

12 Op Amp Gain Requirement Linear Theory According to the linear theory, finite op amp gain should not degrade the noise significantly as long as A > ( C C 2 )( OSR π) For our implementation of MOD2, in which C C 2 = 4 and OSR = 500, this leads to A > 40 = 32 db, which is quite a lax requirement! As OSR is decreased, the gain requirement goes down ECE37 4-2

13 Op Amp Transconductance Settling time Model the op amp as a simple g m : C2 C β βg m g m C3 v g m v Ceff β = C 2 ( C + C 2 ) C eff = C 3 + C C 2 ( C + C 2 ) This is a single-time-constant-circuit with τ = C eff ( βg m ) ECE37 4-3

14 Settling Requirements If g m is linear, incomplete settling has the same effect as a coefficient error and thus g m can be very low In practice, the g m is not linear and we need to ensure nearly complete settling As a worst case scenario, let s require transients to settle to part in 0 5 This should be more than enough for 00 dbc distortion. ECE37 4-4

15 Settling Requirements (cont d) If linear settling is allocated /4 of a clock period, T 4 τ T 4ln0 5 we want exp = 0 5, or τ = = 20 ns and thus g m = C eff C eff = f βτ β s ln0 5 For INT of our MOD2: 4p.33p C eff = f 4p +.33p = 0.5 pf β = 3 4 f s = MHz g m = 30 µa/v *. 0.5 comes from the single-ended to differential translation. ECE *

16 Slewing The maximum charge transferred through C is u p,max = 0.5 V v refn = 0.5 V C q max = C V =.33 pc If we require the slew current to be enough to transfer q max in /4 of a clock period, then I slew = q max T 4 µa ECE37 4-6

17 Building Block Op Amp bias4 VDD bias3 VON VIP VIN VOP vocm 2 bias2 2 vocm bias 2 2x 2 bias Folded-cascode op-amp with switched-capacitor common-mode feedback ECE37 4-7

18 Op-Amp Design Bias Current Bias Currents 2I I VDD 0,2I Slew Currents 2I I 2I,0 VON VIP VIN VOP I 2x 2I +I, I I Not good practice to let currents go to 0. Need to increase the current in output leg. Slew constraint dictates I >5 µa ECE37 4-8

19 Op-Amp Design gm v g m v v M 2 v--- 2 I = g mv/2 g m = 0.5 g m Square-law MOSFET model: g m = ( 2I D ) ( V ) I D = 5 µa, g m 30 µa/v V 0.33 V Usually V 200 mv, so we should be able to get high enough g m. ECE37 4-9

20 Transistor Sizes & Bias Point W/L 2.5/ / / / V 0.5/0.3 0µA.0/ µA 2.0V Vdsat =0.5V.25V Vdsat =0.5V 0.35V 7.5µA Allowable swing is +0.6 V, 0.75 V Simulated g m =36µA/V, A =48dB g m is high enough and the gain is 6 required. ECE

21 Ideal Common-Mode Feedback OP ON OP CM ON CM Can use this circuit to speed up the simulation ECE37 4-2

22 Simulated Waveforms P2 V v(xp) v(xn) The output voltage initially goes the wrong way? 0.5 µs/div ECE

23 Expanded Waveforms P2 V v(xp) Slewing Linear Settling τ ~ 30 ns (Longer than expected).6.4 v(xn).2 00 ns/div ECE

24 dbfs/nbw Simulated Spectrum SQNR = 08 OSR = dBc 3 rd harmonic k 0k 00k Frequency (Hz) Theoretical PSD (k = ) This was too easy! Although this one simulation did take an hour. NBW=46Hz ECE

25 SC Common-Mode Feedback Common-Mode /2-Circuit I V ocm C a C b V cm V M V gs V V cm V ocm = V cm + V gs V If V = V gs, then V ocm = V cm. ECE

26 Latched Comparator VDD Y+ Y S Set/Reset Latch: v R S R VSS Inverter thresholds are chosen so that the inverters respond only after R/S have resolved. Falling phase initiates regenerative action S and R connected to a Set/Reset latch. ECE

27 Switch Resistance Sampling Phase C Vin R sw If R sw is constant, its has only a filtering (linear) effect, which is benign Unfortunately, the on-resistance of MOS switches varies with V gs (and hence V in ) Must make MOS switches large enough ECE

28 Differential Half-Circuit: Switch Resistance Integration Phase R sw C C2 2g m R sw increases the settling time by a factor of +4g m R sw Set R sw to make the increase in τ small 40g m So in our MOD2, we want R sw 0.75 kω. BTW, my simulation used R sw = kω and was OK. ECE

29 NLCOTD: Non-Overlapping Clock Generator P CK? P2 ECE

30 Non-Overlapping Clock Generator CK P P2 CK P P2 Non-overlap time set by NOR s t PLH ECE

31 Clocking Details Early/Late Phases D C D M M2 Charge injected via M is (non-linearly) signaldependent, whereas charge injection from M2 is signal-independent Open M2 (early) then open M (late) so that charge injected from C gs cannot enter C ECE37 4-3

32 Clocking Details Bottom-plate sampling D C M Bottom Plate M2 C p small big Substrate Parasitic capacitance on the right terminal of C degrades the effectiveness of early/late clocking C p for the top plate is smaller, so use the top plate for the right terminal and the bottom plate for the left ECE

33 Complementary Clock Alignment We need complementary clocks if transmission gates are used for the switches Q: How do we align them? A: Carefully size the inverters relative to their capacitive loads, or use a transmission gate to mimic an inverter delay: CK CKP CKN Need to match delay of 3 INVs to 2 INVs CK CKP CKN ECE

34 Professional Clock Generator CK Non-overlap control Delay control CK D 2 2D * * To maximize the time available for settling, make the early and late phases start at the same time ECE * * D 2D 2 Buffers for driving large clock loads

35 Review: Implementation Summary Choose a viable SC topology and manually verify timing 2 Do dynamic-range scaling 3 Determine absolute capacitor sizes 4 Determine op-amp specs and construct a transistor-level schematic Verify. Verify. Verify. 5 Layout, fab, debug, document, get customers, sell by the millions, go public, This last step is an exercise for the reader. ECE

36 Topological Variant Feed-Forward U z z z Q E V NTF( z) = ( z ) 2 STF( z) = 2z z 2 + Output of first integrator has no DC component Dynamic range requirements of this integrator are relaxed. Although STF near ω = 0, STF = 3 for ω = π Instability is more likely. ECE

37 Topological Variant Feed-Forward with Extra Feed-In U z z z Q E V NTF( z) = ( z ) 2 STF( z) = + No DC component in either integrator s output Reduced dynamic range requirements in both integrators, esp. for multi-bit modulators. + Perfectly flat STF No increased risk of instability. Timing is tricky ECE

38 Topological Variant Error Feedback U Q E V z - 2 z - E NTF( z) = ( z ) 2 STF( z) = + Simple Very sensitive to gain errors Only suitable for digital implementations. ECE

39 Is MOD2 The Only 2 nd -Order Modulator? Except for the filtering provided by the STF, any modulator with the same NTF as MOD2 has the same input-output behavior as MOD2 SQNR curve is the same. Tonality of the quantization noise is unchanged. Internal states, sensitivity, thermal noise etc. can differ from realization to realization BUT, in terms of input-output behavior, A 2 nd -order modulator is truly different only if it possesses a truly different (2 nd -order) NTF ECE

40 0 A Better 2 nd -Order NTF Pole-Zero Plot Moving poles closer to zeros lowers NTF gain, allowing larger inputs Separating the zeros reduces in-band noise: f B -a a f B ECE

41 NTF Comparison db db lower NTF gain NTF zero near passband edge Normalized Frequency Plain MOD2 Improved MOD2 ECE37 4-4

42 SNR vs. Amp Comparison MOD2b more tolerant of large inputs SQNR (db) ~ 6 db better SQNR MOD2 MOD2b Signal Amplitude (dbfs) ECE

43 MOD2 Internal Waveforms 75% of FS 3 x y = x 2-3 Quantizer overloads ~20% of the time ECE

44 MOD2b Internal Waveforms 75% of FS 3 x Smaller internal state swing y = x 2 Quantizer overloads much less often ECE

45 Gain of a Binary Quantizer v v = y v = 0.5y y Our assumed linear model The effective gain of a binary quantizer is not known a priori The gain (k) depends on the statistics of the quantizer s input Halving the signal doubles the gain. ECE

46 Gain of the Quantizer in MOD2 The effective gain of a binary quantizer can be computed from the simulation data using E[ y ] k = [S&T Eq. 2.5] E[ y 2 ] For the simulation of 2-4, k = 0.63 k alters the NTF: NTF ( z) NTF k ( z) = k + ( k )NTF ( z) ECE

47 Revised PSD Prediction 0 20 Theoretical PSD k = dbfs/nbw Simulated Spectrum (smoothed) Theoretical PSD (k = ) 20 NBW = Normalized Frequency Agreement is now excellent ECE

48 Variable Quantizer Gain When the input is small (below 2 dbfs), the effective gain of MOD2 s quantizer is k = 0.75 MOD2 s small-signal NTF is thus ( z ) NTF( z) = z 2 0.5z This NTF has 2.5 db less quantization noise suppression than the ( z ) 2 NTF derived from the assumption that k = Thus the SQNR should be about 2.5 db lower than. As the input signal increases, k decreases and the suppression of quantization noise degrades SQNR increases less quickly than the signal power. Eventually the SQNR saturates and then decreases as the signal power reaches full-scale. ECE

49 What You Learned Today Transistor-level implementation of MOD2 op-amp, SC CMFB, comparator, clock generator 2 MOD2 variants 3 Variable quantizer gain ECE

50 Op Amp Gain Requirement Nonlinear Theory MOD2 has a deadband around u = 0 whose width is approximately 0.5( a c ) + a ( ( 3) ( 3) ) + ( 9) = = A 2 A 2 Since we didn t need so much gain to get excellent AC performance, this calculation looks like it is conservative ECE A 2 To make the deadband less than LSB wide, < undbv( 00) = 0 5, 6A 2 or A > 400 = 52 db

51 Op Amp Gain Requirements Nonlinear Theory 2 Finite DC gain incomplete charge transfer The gain is a nonlinear function, so the residual charge is nonlinearly related to the output voltage of the amplifier The residual charge is akin to noise. However, if the amplifier output contains signal components, then nonlinear gain can result in harmonic distortion The feedforward topology is known to yield low distortion even when the amplifier gain is low. The effects are difficult to quantify analytically, and so we typically rely on simulations ECE37 4-5

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