Pipelined multi step A/D converters


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1 Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, , India 04 Nov 2006
2 Motivation for multi step A/D conversion Flash converters: Area and power consumption increase exponentially with number of bits N Impractical beyond 78 bits. Multi step conversioncoarse conversion followed by fine conversion Multistep converters Subranging converters Multi step conversion takes more time Pipelining to increase sampling rate
3 Two step A/D converterbasic operation S/H 2 M 1 comparators A/D1 M bits m D/A V q 2 M V q Σ 2 M A/D1  Total resolution N = MK Digital output n = 2 K mk K bits k m k MK M K concatenation Second A/D quantizes the quantization error of first A/D Concatenate the bits from the two A/D converters to form the final output
4 Two step A/D converterbasic operation A/D1, DAC, and A/D2 have the same range Second A/D quantizes the quantization error of first A/D Use a DAC and subtractor to determine V q Amplify V q to full range of the second A/D Final output n from m, k A/D1 output is m (DAC output is m/2 M ) A/D2 input is at k th transition (k/2 K ) = k/2 K 1/2 M m/2 M = (2 K m k)/2 MK Resolution N = M K, output n = 2 K m k Concatenate the bits from the two A/D converters to form the final output
5 Two step A/D converter: Example with M = 3, K = 2 V q 2 M V q transition points of A/D2 3V LSB2 2V LSB2 V LSB2 input range of A/D2 V LSB1 V LSB 2V LSB 2 M 1V LSB V LSB1 2V LSB1 2 M 1V LSB1 transition points of the overall A/D Second A/D quantizes the quantization error of first A/D Transitions of second A/D lie between transitions of the first, creating finely spaced transition points for the overall A/D.
6 Quantization error V q V q slope=1 size of discontinuity = D/A step size V LSB1 location of discontinuities =A/D1 transition points V q vs. : Discontinuous transfer curve Location of discontinuities: Transition points of A/D1 Size of discontinuities: Step size of D/A Slope: unity
7 Two step A/D converter ideal A/D1 V q 2 M V q 3 /4 /2 /4 input range of A/D2 V LSB1 V LSB 2V LSB 2 M 1V LSB V LSB1 2V LSB1 2 M 1V LSB1 A/D1 transitions exactly at integer multiples of /2 M Quantization error V q limited to (0, /2 M ) 2 M V q exactly fits the range of A/D2
8 Two step A/D converter M bit accurate A/D1 V q 2 M V q A/D2 overload ideal transitions actual transitions input range of A/D2 V LSB1 V[2] V[1] V[2 M 1] V[2] V[1] V[2 M 1] A/D2 overload A/D1 transitions in error by up to /2 M1 Quantization error V q limited to ( /2 M1, 3 /2 M1 ) a range of /2 M 1 2 M V q overloads A/D2
9 Two step A/D with digitial error correction (I) /2 M1 S/H 2 M 1 comparators A/D1 M bits m D/A V q 2 M V q Σ 2 M1 A/D1  Reduce interstage gain to 2 M 1 K M m addition with Total resolution N = MK1 1 bit overlap k Digital output n = 2 K1 mk2 K2 subtract 2 K K bits k MK1 Add /2 M1 (0.5 LSB1) offset to DAC output to keep V q positive Subtract 2 K 2 from digital output to compensate for the added offset Overall accuracy is N = M K 1 bits; A/D1 contributes M 1 bits, A/D2 contributes K bits; 1 bit redundancy Output n = 2 K 1 m k 2 K 2
10 Two step A/D with digitial error correction (I) Ideal A/D1 V q 2 M1 V q 2V LSB1 3 /4 /2 /4 input range of A/D2 V LSB1 2 M 1V LSB 2V LSB V LSB 2 M 1V LSB 2V LSB V LSB 2 M 1 V q varies from /4 to 3 /4 2 M 1 V q outside this range implies errors in A/D1
11 Two step A/D with digitial error correction (I) M bit accurate A/D1 V q 2 M1 V q ideal transitions 2V LSB1 actual transitions A/D2 input outside this range implies errors in A/D1 input range of A/D2 V LSB1 V[2 M 1] V[2] V[1] V[2 M 1] V[2] V[1] 2 M 1 V q varies from 0 to A/D2 is not overloaded for up to 0.5 LSB errors in A/D1
12 Two step A/D with digitial error correction (I) M bit accurate A/D1 A/D1 Transition shifted to the left m greater than its ideal value by 1 k lesser than than its ideal value by 2 K 1 A/D output n = 2 K 1 m k 2 K 2 doesn t change A/D1 Transition shifted to the right m lesser than its ideal value by 1 k greater than than its ideal value by 2 K 1 A/D output n = 2 K 1 m k 2 K 2 doesn t change 1 LSB error in m can be corrected
13 Two step A/D with digitial error correction (II) S/H 2 M 1 comparators 0.5LSB offset A/D1 M bits m D/A V q 2 M V q Σ 2 M A/D1  Total resolution N = MK1 Digital output n = 2 K1 mk Reduce interstage gain to 2 M 1 Shift the transitions of A/D1 to the right by /2 M1 (0.5 LSB1) to keep V q positive K bits k m k MK1 M K addition with 1 bit overlap Overall accuracy is N = M K 1 bits; A/D1 contributes M 1 bits, A/D2 contributes K bits; 1 bit redundancy Output n = 2 K 1 m k, no digital subtraction required implies simpler digital logic
14 Two step A/D with digitial error correction (II) Ideal A/D1 V q 2 M1 V q 2V LSB1 3 /4 /2 /4 input range of A/D2 V LSB1 2 M 0.5V LSB 2.5V LSB 1.5V LSB 2 M 0.5V LSB 2.5V LSB 1.5V LSB 2 M 1 V q varies from 0 to 3 /4; /4 to 3 /4 except the first segment 2 M 1 V q outside this range implies errors in A/D1
15 Two step A/D with digitial error correction (II) M bit accurate A/D1 V q 2 M1 V q ideal transitions actual transitions 3 /4 2V LSB1 /2 /4 input range of A/D2 V LSB1 V[2 M 1] V[2] V[1] V[2 M 1] V[2] V[1] 2 M 1 V q varies from 0 to A/D2 is not overloaded for up to 0.5 LSB errors in A/D1
16 Two step A/D with digitial error correction (II) M bit accurate A/D1 A/D1 Transition shifted to the left m greater than its ideal value by 1 k lesser than than its ideal value by 2 K 1 A/D output n = 2 K 1 m k doesn t change A/D1 Transition shifted to the right m lesser than its ideal value by 1 k greater than than its ideal value by 2 K 1 A/D output n = 2 K 1 m k doesn t change 1 LSB error in m can be corrected
17 Two step A/D with digitial error correction (IIa) S/H 2 M 2 comparators 0.5LSB offset A/D1 M bits m D/A V q 2 M V q Σ 2 M A/D1  Total resolution N = MK1 Digital output n = 2 K1 mk K bits k m k MK1 M K addition with 1 bit overlap 0.5LSB ( /2 M 1 ) shifts in A/D1 transitions can be tolerated If the last transition ( /2 M 1 ) shifts to the right by /2 M 1, the transition is effectively nonexistentstill the A/D output is correct Remove the last comparator M bit A/D1 has 2 M 2 comparators set to 1.5 /2 M, 2.5 /2 M,..., 1.5 /2 M Reduced number of comparators
18 Two step A/D with digitial error correction (IIa) Ideal A/D1 V q 2 M1 V q input range of A/D2 2V LSB1 V LSB1 1.5V LSB 2.5V LSB 2 M 1.5V LSB last comparator removed 1.5V LSB 2.5V LSB 2 M 1.5V LSB last comparator removed 2 M 1 V q varies from 0 to ; /4 to 3 /4 except the first and last segments 2 M 1 V q outside this range implies errors in A/D1
19 Two step A/D with digitial error correction (IIa) M bit accurate A/D1 V q 2 M1 V q ideal transitions actual transitions 2V LSB1 transition points of A/D2 3V LSB2 2V LSB2 VLSB2 input range of A/D2 V LSB1 V[2 M 2] V[2] V[1] V[2 M 2] V[2] V[1] 2 M 1 V q varies from 0 to A/D2 is not overloaded for up to 0.5 LSB errors in A/D1
20 Two step A/D with digitial error correction (IIa) M bit accurate A/D1 A/D1 Transition shifted to the left m greater than its ideal value by 1 k lesser than than its ideal value by 2 K 1 A/D output n = 2 K 1 m k doesn t change A/D1 Transition shifted to the right m lesser than its ideal value by 1 k greater than than its ideal value by 2 K 1 A/D output n = 2 K 1 m k doesn t change 1 LSB error in m can be corrected
21 Switched capacitor (SC) amplifier φ 1 C 1 0V V out C 1 => voltage v 2 on =C 1 / C 1  v 2 C 1 0V V out C 1 0V V out total charge on this surface = 0 total charge on this surface = 0 φ 1 : C 1 connected to ground; reset; reset switch provides dc negative feedback around the opamp φ 1 : Input sampled on C 1 ; in feedback φ 1 : Charge at virtual ground node is conserved V out = C 1 /
22 Non inverting SC amplifier C 1 0V V out φ 1 0 C 1 => voltage v 2 on =C 1 /  v 2 C 1 0V V out C 1 0V V out total charge on this surface = C 1 total charge on this surface = C 1 φ 1 Change the phase of input sampling to invert the gain
23 SC realization of DAC and amplifier C/4 b 1φ 1 b 1φ 1 2 M1 C C/4 0V V out b 2φ 1 b 2φ 1 φ 1 C/2 b 1,b 2: Thermometer coded bits from A/D1 (M = 2 in this case) Pipelined A/D needs DAC, subtractor, and amplifier sampled on C 1 in (positive gain) sampled on M/2 M C 1 in φ 1 (negative gain). M/2 M C 1 realized using a switched capacitor array controlled by A/D1 output C 1 / = 2 M 1 At the end of φ 1, V out = 2 M 1 ( m/2 M )
24 Two stage converter timing and pipelining T s clock phases φ 1 φ 1 φ 1 sampling instant S/H 2 M 2 comparators 0.5LSB offset 2 M V q V q Σ 2 M A/D1  Sample and Hold T H T H T H m available clk(φ 1,φ2) A/D1 D/A clk(φ 1,φ2) clk(φ 1,φ2) M bits 1/2 cycle delay K bits A/D1 DACAmplifier S R S R S reset amplify reset amplify reset k available m to adder k A/D2 S R S R
25 Two stage converter timing and pipelining S/H holds the input V i [n] from the end of previous φ 1 A/D1 samples the output of S/H Amplifier samples the output of S/H on C Opamp is reset φ 1 S/H tracks the input A/D1 regenerates the digital value m Amplifier samples of S/H on m/2 M C Opamp output settles to the amplified residue A/D2 samples the amplified residue A/D2 regenerates the digital value k. m, delayed by 1/2 clock cycle, can be added to this to obtain the final output S/H, A/D1, Amplifier function as before, but on the next sample V i [n 1] In a multistep A/D, the phase of the second stage is reversed when compared to the first, phase of the third stage is the same, and so on
26 Effect of opamp offset φ 1 C 1 V off V out Voff C 1 => voltage v 2 on =C 1 / C 1 (V off  )  v 2 C 1 V off V out C 1 V off V out =V off C 1 / total charge on this surface = CV off Voff total charge on this surface = CV off Voff φ 1 : C 1 is charged to V off instead of input offset cancellation; no offset in voltage across : V out = C 1 / V off ; Unity gain for offset instead of 1 C 1 / (as in a continuous time amplifier)
27 Correction of offset on φ 1 φ 1 C 1 V off V out Voff : Charge to the offset voltage instead of 0 V φ 1 : V out = C 1 / ; Offset completely cancelled
28 Nonidealities Random mismatch: Capacitors must be large enough (relative matching α1/ WL to maintain DAC, amplifier accuracy Thermal noise: Capacitors must be large enough to limit noise well below 1 LSB. Opamp s input referred noise should be small enough. Opamp dc gain: Should be large enough to reduce amplifier s output error to /2 K 1. Opamp bandwidth: Should be large enough for amplifier s output settling error to be less than /2 K 1.
29 Thermal noise in SC amplifiers R sw3 R sw1 C 1 0V V out φ 1 V off Rsw2 V nsw3 R sw3 R sw1 V nsw1 C 1 0V V out C 1 0V V out V nsw2 V off Rsw2 V off φ 1 Noise from switch resistances Noise from the amplifierignored
30 Thermal noise in SC amplifiers : φ 1 : R sw1 : C 1 has a voltage noise of variance kt /C 1 R sw2 : has a voltage noise of variance kt /. R sw1 : Its contribution in (kt /C 1 ) will be amplified to kt /C 1 (C 1 / ) 2 R sw2 : Its contribution in (kt /C 1 ) will be held R sw3 : Results in a noise kt /C 1 on C 1 and kt /C 1 (C 1 / ) 2 at the output Total output noise: kt / (2C 1 / 1) 2kT /C 1 (C 1 / ) 2 Input referred noise: kt /C 1 (2 /C 1 ) 2kT /C 1 C 1 must be large enough to minimize the effects of thermal noise
31 Op amp models V out /V d (db) finite dc gain model: A 0 first order model: A 0 /(1s/ω d ) integrator model: ω u /s full model: A 0 /(1s/ω d )(1s/p 2 )(1s/p 3 )... A 0 ω d ω u p 2 p 3 ω Opamp has finite dc gain, predominantly first order rolloff, and many high frequency poles High frequency poles should be beyond the unity gain frequency of the feedback loop gain (not necessarily the opamp s open loop gain) for stability. Effect of dc gain and first order rolloff modeled separately for simplicity
32 Effect of opamp dc gain C 1 V x V out A 0 V out /V d (db) finite dc gain model: A 0 first order model: A 0 /(1s/ω d ) integrator model: ω u /s full model: A 0 /(1s/ω d )(1s/p 2 )(1s/p 3 )... φ 1 A dc ω d ω u p 2 p 3 ω : V out = V x = 0 φ 1 : V out = C 1 / 1/1 (1 C 1 / )/A 0 ; Reduced dc gain in the amplifier Error should be smaller than /2 K 1 A 0 > 2 MK 2 K 1 2 M 1 1 Approximately, A 0 > 2 MK, 2/LSB of the overall converter
33 Effect of finite unity gain frequency of the opamp finite dc gain model: A 0 first order model: A 0 /(1s/ω d ) integrator model: ω u /s C 1 full model: A 0 /(1s/ω d )(1s/p 2 )(1s/p 3 )... V x(t) V out (t) A 0 ω u /s φ 1 p 2 p 3 ω d ω u : V out (t) = V x (t) = V out (0) exp( ω u t) Incomplete reset Worst case: V out (0) = ; Error smaller than /2 K 1 at the t = T s /2 ω u 2 ln(2)(k 1)f s p 2,3,... > ω u
34 Effect of finite unity gain frequency of the opamp finite dc gain model: A 0 first order model: A 0 /(1s/ω d ) integrator model: ω u /s C 1 full model: A 0 /(1s/ω d )(1s/p 2 )(1s/p 3 )... V x(t) V out (t) A 0 ω u /s φ 1 p 2 p 3 ω d ω u φ 1 : V out (t) = C 1 / (1 exp( ω u C 1 t) ) V out (0) exp( ω u C 1 t) Incomplete settling of amplified residue V q Worst case: C 1 / = ; Error smaller than /2 K 1 at the t = T s /2; V out (0) = 0 after reset. ω u /(1 2 M 1 ) 2 ln(2)(k 1)f s (ω u in rad/s, f s in Hz) ω u /(1 2 M 1 ) is the unity loop gain frequency assuming no parasitics p 2,3,... > ω u /(1 2 M 1 )
35 Effect of finite unity gain frequency of the opamp Depending on amplifier topology, reset and amplifying phases pose different constraints In our example, amplifying phase constraint is more stringent (loop gain in amplifying and reset phases are very differentbetter to have them close to each other) ω u itself can depend on capacitive load(different for φ 1, ) Higher order poles p 2, p 3,... need to be placed above the unity loop gain frequency, not necessarily ω u
36 Single stage opamptransconductor v in  g m v in φ 1 C 1 0V V out Model of a single stage opamp SC amplifier C 1 C 1 V out V out φ 1 φ 1 : Capacitive load = C 1 : Capacitive load = C 1 /(C 1 )
37 Single stage opamptransconductor Loop opened at opamp input C 1 V f V t V out C 1 V f V t V out φ 1 Loop broken at the opamp input to evaluate loop gain φ 1 V out(s)/v t (s) = g m /sc 1 Opamp unity gain frequency ω u = g m /C 1 V f (s)/v t (s) = g m /sc 1 Unity loop gain frequency ω u,loop = g m /C 1 V out(s)/v t (s) = g m /s(c 1 /C 1 ) Opamp unity gain frequency ω u = g m /(C 1 /C 1 ) V f (s)/v t (s) = g m /sc 1 Unity loop gain frequency ω u,loop = g m /C 1
38 Multi step converters Two step architecture can be extended to multiple steps All stages except the last have their outputs digitally corrected from the following A/D output Accuracy of components in each stage depends on the accuracy of the A/D converter following it. Accuracy requirements less stringent down the pipeline, but optimizing every stage separately increases design effort Pipelined operation to obtain high sampling rates Last stage is not digitally corrected
39 Multi step A/D converter 12 bit A/D 9 bit A/D 6 bit A/D 3 bit A/D V 4 4b A/D V 3 4b A/D V 2 residue gen. residue gen. 4b A/D residue gen. V 1 3b A/D C 5 4 bits C 4 4 bits C 3 4 bits 3 bits D out /12 D N C N D N1 /9 D N C N D N1 /6 D N C N D N1 /3 D 4 D 3 D 2 D 1 Analog path Quantizer and residue generator (14 comparators) 4b A/D V in  V q S/H A/D D/A Σ 8 residue gen. 8V q 4 bits Digital path Digital correction D N1 C N D N D N = 2 K1 C ND N1 C N: {0,...,14} K: cumulative number of bits after N th stage 4,4,4,3 bits for an effective resolution of 12 bits 3 effective bits per stage
40 Multi step convertertradeoffs Large number of stages, fewer bits per stage Fewer comparators, low accuracylower power consumption Larger number of amplifierspower consumption increases Larger latency Fewer stages, more bits per stage More comparators, higher accuracy designs Smaller number of amplifierslower power consumption Smaller latency Typically 34 bits per stage easy to design
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