Introduction to CMOS VLSI Design. SPICE Simulation. Curtis Nelson Walla Walla University

Transcription

1 Introduction to CMOS VLSI Design SPICE Simulation Curtis Nelson Walla Walla University

2 Outline q Introduction to SPICE q DC Analysis q Transient Analysis q Subcircuits q Eldo Slide 2

3 SPICE q SPICE is the most commonly used analog circuit simulator q The simulator was developed at the University of California, Berkeley, and was first released in 1972 q SPICE fundamentals Comments Devices Commands Slide 3

4 Introduction to SPICE q Simulation Program with Integrated Circuit Emphasis Developed in 1970 s at Berkeley Many commercial versions are available HSPICE is a robust industry standard Has many enhancements currently in use q Written in FORTRAN for punch-card machines Circuits elements are called cards Complete description is called a SPICE deck Slide 4

5 SPICE Begins Under urging from his advisors, Laurence Nagel of UC Berkley develops a proprietary non-military simulator. Under further pressure, he rewrites an open source circuit simulator; SPICE Program Year Language Of Note CANCER 1968 FORTRAN No Radiation SPICE FORTRAN Nodal Analysis SPICE FORTRAN Variable Timestep SPICE C Accounted for Shrinking Nodes SPICE derivatives are still being developed by large IC CMOS VLSI Design

6 SPICE1 q Nodal analysis poor representation of inductors & floating sources q Fixed timestep Transient analysis q BJTs changed to use Gummel-Poon q JFET & MOSFET devices included CMOS VLSI Design

7 SPICE2 q Modified Nodal Analysis includes branch currents now reliably models inductors and sources. q Variable timestep included for transient q MOSFETs and BJTs overhauled and extended q SPICE2G.6 is last FORTRAN version and is the basis for many implementations used today CMOS VLSI Design

8 SPICE3 q Written in C q Graphics interface q MESFETS, lossy transmission lines, non-ideal switches added. q Models updated to accommodate shrinking geometries. q No longer compatible with previous versions CMOS VLSI Design

9 Today q SPICE bundled behind many schematic capture and layout packages q Proprietary versions still in development by large IC design houses. q Covered by the BSD license CMOS VLSI Design

10 Writing Spice Decks q Writing a SPICE deck is like writing a good program Plan: sketch schematic on paper or in editor Modify existing decks whenever possible Code: strive for clarity Start with name, , date, purpose Generously comment Test: Predict what results should be Compare with actual Garbage In, Garbage Out! Slide 10

11 Lab1 Spice Deck *.CONNECT statements *.CONNECT GND 0 * ELDO netlist on Mon Mar at 15:15:04 * * Globals. *.global GND VDD * * component pathname : $MGC_WD/inv1 *.subckt INV1 OUT IN MP1 OUT IN VDD VDD p L=2u W=5u MN1 OUT IN GND GND n L=2u W=5u.ends INV1 ** MAIN CELL: component pathname : $MGC_WD/buf1 * X_INV11 N$1 N$5 INV1 X_INV13 VO N$2 INV1 V1 N$5 GND PULSE ( 0V 5V 0nS 1nS 1nS 20nS 50nS ) V2 VDD GND DC 5V C1 VO GND notchedrow 300f X_INV12 N$2 N$1 INV1 * * eldo include file. *.end Slide 11

12 Example: RC Circuit * rc.sp * David_Harris@hmc.edu 2/2/03 * Find the response of RC circuit to rising input * * Parameters and models * option post * * Simulation netlist * Vin in gnd pwl 0ps 0 100ps 0 150ps ps 1.8 R1 in out 2k C1 out gnd 100f Vin R1 = 2KΩ C1 = 100fF + Vout - * * Stimulus * tran 20ps 800ps.plot v(in) v(out).end Slide 12

13 Result (Textual) legend: a: v(in) b: v(out) time v(in) (ab ) m p p p p p p m +b + + a p b a p b a p b a p b a p b a p b a p b a p b a p b + + +a p b + + +a p b + + +a p b + +a p b + +a p b a p b + +a p b + +a p b+ +a p b +a p b +a p b +a p b +a p b +a p b +a p b--+a p b +a p b +a p b +a p b +a p b+a p b+a p b+a p b+a p ba p ba Slide 13

14 Result (Graphical) 2.0 v(in) 1.5 v(out) p 200p 300p 400p 500p 600p 700p 800p 900p t(s) Slide 14

15 Sources q DC Source Vdd vdd gnd 2.5 q Piecewise Linear Source Vin in gnd pwl 0ps 0 100ps 0 150ps ps 1.8 q Pulsed Source Vck clk gnd PULSE ps 100ps 100ps 300ps 800ps PULSE v1 v2 td tr tf pw per v2 td tr pw tf v1 per Slide 15

16 SPICE Elements Letter R C L K V I M D Q W X E G H F Element Resistor Capacitor Inductor Mutual Inductor Independent voltage source Independent current source MOSFET Diode Bipolar transistor Lossy transmission line Subcircuit Voltage-controlled voltage source Voltage-controlled current source Current-controlled voltage source Current-controlled current source Slide 16

17 Units Letter Unit Magnitude a atto f femto p pico n nano 10-9 u micro 10-6 m milli 10-3 k kilo 10 3 x mega 10 6 g giga 10 9 Ex: 100 femtofarad capacitor = 100fF, 100f, 100e-15 Slide 17

18 DC Analysis * mosiv.sp * * Parameters and models * include '../models/tsmc180/models.sp'.temp 70.option post 4/2 I ds * * Simulation netlist * *nmos Vgs g gnd 0 Vds d gnd 0 M1 d g gnd gnd NMOS W=0.36u L=0.18u V gs V ds * * Stimulus * dc Vds SWEEP Vgs end Slide 18

19 I-V Characteristics q nmos I-V V gs dependence Saturation V gs = 1.8 V gs = 1.5 I ds (µa) 100 V gs = V gs = V ds V gs = 0.6 Slide 19

20 MOSFET Elements M element for MOSFET Mname drain gate source body type + W=<width> L=<length> + AS=<area source> AD = <area drain> + PS=<perimeter source> PD=<perimeter drain> Slide 20

21 Transient Analysis * inv.sp * Parameters and models * param SUPPLY=1.8.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post * Simulation netlist * Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0 'SUPPLY' 50ps 0ps 0ps 100ps 200ps M1 y a gnd gnd NMOS W=4 L=2 + AS=20 PS=18 AD=20 PD=18 M2 y a vdd vdd PMOS W=8 L=2 + AS=40 PS=26 AD=40 PD=26 * Stimulus * tran 1ps 200ps.end Slide 21 a 8/2 4/2 y

22 Transient Results q Unloaded inverter Overshoot Very fast edges v(a) v(y) (V) t f = 10ps t pdf = 12ps t pdr = 15ps t r = 16ps p 100p 150p 200p t(s) Slide 22

23 Subcircuits q Declare common elements as subcircuits.subckt inv a y N=4 P=8 M1 y a gnd gnd NMOS W='N' L=2 + AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10' M2 y a vdd vdd PMOS W='P' L=2 + AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10'.ends q Ex: Fanout-of-4 Inverter Delay Reuse inv Shaping Loading Shape input Device Under Test Load a b c d e X1 X2 X3 X Load on Load 512 X5 256 f Slide 23

24 FO4 Inverter Delay * fo4.sp * Parameters and models * param SUPPLY=1.8.param H=4.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post * Subcircuits * global vdd gnd.include '../lib/inv.sp' * Simulation netlist * Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000ps X1 a b inv * shape input waveform X2 b c inv M='H' * reshape input waveform.end Slide 24

25 FO4 Inverter Delay Cont. X3 c d inv M='H**2' * device under test X4 d e inv M='H**3' * load x5 e f inv M='H**4' * load on load * Stimulus * tran 1ps 1000ps.measure tpdr * rising prop delay + TRIG v(c) VAL='SUPPLY/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling prop delay + TRIG v(c) VAL='SUPPLY/2' RISE=1 + TARG v(d) VAL='SUPPLY/2' FALL=1.measure tpd param='(tpdr+tpdf)/2' * average prop delay.measure trise * rise time + TRIG v(d) VAL='0.2*SUPPLY' RISE=1 + TARG v(d) VAL='0.8*SUPPLY' RISE=1.measure tfall * fall time + TRIG v(d) VAL='0.8*SUPPLY' FALL=1 + TARG v(d) VAL='0.2*SUPPLY' FALL=1.end Slide 25

26 FO4 Results 2.0 a b 1.5 c d 1.0 (V) 0.5 t pdf = 66ps t pdr = 83ps e f p 400p 600p 800p 1n t(s) Slide 26

27 Optimization q HSPICE can automatically adjust parameters Seek value that optimizes some measurement q Example: Best P/N ratio We ve assumed 2:1 gives equal rise/fall delays But we see rise is actually slower than fall What P/N ratio gives equal delays? q Strategies (1) run a bunch of simulations with different P size (2) let HSPICE optimizer do it for us Slide 27

28 P/N Optimization * fo4opt.sp * Parameters and models * param SUPPLY=1.8.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post * Subcircuits * global vdd gnd.include '../lib/inv.sp' * Simulation netlist * Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000ps X1 a b inv P='P1' * shape input waveform X2 b c inv P='P1' M=4 * reshape input X3 c d inv P='P1' M=16 * device under test Slide 28

29 P/N Optimization X4 d e inv P='P1' M=64 * load X5 e f inv P='P1' M=256 * load on load * Optimization setup * param P1=optrange(8,4,16) * search from 4 to 16, guess 8.model optmod opt itropt=30 * maximum of 30 iterations.measure bestratio param='p1/4' * compute best P/N ratio * Stimulus * tran 1ps 1000ps SWEEP OPTIMIZE=optrange RESULTS=diff MODEL=optmod.measure tpdr * rising propagation delay + TRIG v(c)val='supply/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling propagation delay + TRIG v(c) VAL='SUPPLY/2' RISE=1 + TARG v(d) VAL='SUPPLY/2' FALL=1.measure tpd param='(tpdr+tpdf)/2' goal=0 * average prop delay.measure diff param='tpdr-tpdf' goal = 0 * diff between delays.end Slide 29

30 P/N Results q P/N ratio for equal delay is 3.6:1 t pd = t pdr = t pdf = 84 ps (slower than 2:1 ratio) Big pmos transistors waste power too Seldom design for exactly equal delays q What ratio gives lowest average delay?.tran 1ps 1000ps SWEEP OPTIMIZE=optrange RESULTS=tpd MODEL=optmod P/N ratio of 1.4:1 t pdr = 87 ps, t pdf = 59 ps, t pd = 73 ps Slide 30

31 Power Measurement q HSPICE can measure power Instantaneous P(t) Or average P over some interval.print P(vdd).measure pwr AVG P(vdd) FROM=0ns TO=10ns q Power in single gate Connect to separate V DD supply Be careful about input power Slide 31

32 Logical Effort q Logical effort can be measured from simulation As with FO4 inverter, shape input, load output Shape input Device Under Test Load Load on Load a X1 M=1 b X2 M=h c X3 d X4 e X5 f M=h 2 M=h 3 M=h 4 Slide 32

33 Logical Effort Plots q Plot t pd vs. h Normalize by τ y-intercept is parasitic delay Slope is logical effort q Delay fits straight line very well in any process as long as input slope is consistent d abs τ = 15 ps h Slide 33

34 Logical Effort Data q For NAND gates in TSMC 180 nm process: q Notes: Parasitic delay is greater for outer input Average logical effort is better than estimated Slide 34

35 Comparison Slide 35

36 Eldo q Mentor Graphics product q One of the leading SPICE simulators q Takes a long time to learn (Even longer to master) q ~/anacad/documentation/ eldo_rf.pdf (387) Eldo RF eldo_ur.pdf (1365) Eldo user manual eldo_sources.pdf Lists all sources eldo_devices.pdf Lists all devices eldo_commands.pdf Lists all commands equations.pdf (837) Device equations Slide 36

37 Eldo Devices Slide 37

38 Eldo Sources Slide 38

39 Eldo Commands Slide 39

40 Eldo Overview Slide 40

41 Eldo Syntax q First line (title) is always ignored q Case insensitive q To continue lines use + q Comments begin with * q Inline comments! q Multiline comments #com #endcom q Scale factors Slide 41

42 Arithmetic Functions (1) Slide 42

43 Arithmetic Functions (2) Slide 43

44 Operators Slide 44

45 Expressions q Numerical expressions must be eclosed in { }, or ( ) q String expressions must be enclosed in q Mathematical grouping ( ) q Used in: Calculation of M, R, L, C parameters Time point values in PULSE, PWL, SFFM, SIN and EXP Voltage and current sources values.param,.extract and.defwave Slide 45

46 Common Devices q M MOS-Transistor q R Resistor q C Capacitor q L Inductor Slide 46

47 MOS Transistor mxx d g s b <model> w=width l=length m1 out in vss vss modn w=10u l=0.35u m2 out in vdd vdd modp w=10u l=0.35u Slide 47

48 R, L, C [R L C]xx n1 n2 size R1 n1 n2 100k C1 n1 n2 1p L1 n1 n2 1n Slide 48

49 Combining Devices.subkt filter in out param: res=100k cap=1p R1 in out res C1 out 0 cap.ends filter... x1 in out filter res=200k Slide 49

50 Independent sources Vxx n1 n2 [DC AC SIN PWL PULSE...] Ixx n1 n2 [DC AC SIN PWL PULSE...] V1 vdd 0 dc 3 V2 vin 0 dc 0.5 ac 1 V3 vip 0 pwl (0 0 1u 3) V4 vis 0 sin ( Meg) Ib ibias 0 dc 1uA Ibias vdd ib dc 10uA Slide 50

51 Dependent voltage sources Exx n1 n2 value={expression} Exx n1 n2 nc1 nc2 amplification ++ q Can be used to model devices/circuits Slide 51

52 Dependent current sources Gxx n1 n2 value={expression} Gxx n1 n2 nc1 nc2 amplification ++ q Can be used to model functions.param gm1=10u... Vip vip 0 dc 0.5 ac 1... G1 ib n1 value={gm1*v(vip)} Slide 52

53 .dc q DC sweep v1 vdd 0 dc 3....dc v m1 out vin vdd vdd modp w=1u l=0.35u....dc m1 w 1u 10u 1u Slide 53

54 .tran q Transient analysis.tran 100n 10u 5u 100n Used to calculate maximum step size 10u Stop 5u Start Slide 54

55 .inc q Include other files into your testbench..inc <path to file> q Can be relative or absolute.inc../da/mycircuits.cir.inc $HOME/project/da/mycircuits.cir Slide 55

56 .lib q Create library file1.cir:.lib sn.subckt my_switch vds clk out vdda vssa xs2 vds clk out vdda vssa sn_035.ends.endl sn.lib sp.subckt my_switch vds clk out vdda vssa xs2 vds clk out vdda vssa sp_035.ends.endl sp testbench:.lib file1.cir sn... Xn in clk out vdda vssa my_switch Slide 56

57 .option q Sets Eldo options..option <option>.option noascii No ascii waveform data..option aex Print extracted data to separate file.option msgnode Print all warnings... Slide 57

58 .plot q.plot <waveform>.plot v(vout).plot i(v1).plot gm(m1)! Gm for MOSFET Slide 58

59 Summary q We covered: Introduction to SPICE DC Analysis Transient Analysis Subcircuits Spice particulars Eldo Slide 59