Analog and Mixed-Signal Design for SOC

Transcription

1 nalo and Mixed-Sinal Desin for SO Det. of Electrical Enineerin

2 Outline nalo and Mixed-Sinal Desin in the SO Era urrent Mirrors and Biasin ircuits Sinle-Stae mlifiers Oerational mlifiers ay of nalo and Mixed-Sinal s

3 TS nternational Technoloy oadma for Semiconductors htt://ublic.itrs.net Minimum Gate enth for Diital Transistors Gate enth Projections enth in nm

4 TS cont. Suly oltaes for Diital and nalo s Suly oltae Projections oltae.5 nalo Suly ane 0.5 Diital Suly oltae

5 TS cont. The mixed-sinal suly voltae continues to la that of hih-erformance diital by two or more enerations. combination of multile ate oxide thickness, multile thresholds, and D-D conversion is needed to suort the increased mixed-sinal requirements. Solutions in active threshold reulation, substrate biasin, and novel desin architecture will be required to extend the trend for lower suly voltaes for mixed-sinal alications. n alternative to full interation is the SP that combines circuits made with different technoloies and otimized for the desired functions. We exect that full-diital imlementations in MOS will relace most analo functions excet for analo-to-diital conversion D. 5

6 hallenes for MS desiners Major ssues m and o are both deradin. difficult to build hih ain amlifiers. Feedback is difficult to use. Sinal swin is decreasin with DD. difficult to et accetable SN Many existin architectures will not function Gates are leakin. hare redistribution circuits may not work Devices becomes increasinly nonlinear. Sectral erformance of many circuits will derade. Many existin architectures will not ive accetable erformance. Matchin is becomin worse. difficult to obtain accetable soft yields Performance exectations are increasin. ncreased mask and rocessin costs ncreased concerns ab MS test 6

7 MS desin in SO ncreasin need for data converters Oversamed for low-frequency hih resolution Nyquist rate structures for hiher seeds Feedback will be even more imortant in hih sectral urity alications. Desin for yield will become essential. New circuit architectures that oerate at low voltaes will become essential. 7

8 Outline nalo and Mixed-Sinal Desin in the SO Era urrent Mirrors and Biasin ircuits Sinle-Stae mlifiers Oerational mlifiers ay of nalo and Mixed-Sinal s 8

9 MOS Transistors MOS N-Well Process NMOS PMOS field oxide SS B S G D D G S B oly DD SiO n n ate oxide SiO -subtrate n SiO n-well ommon Used Symbols NMOS D B G PMOS G S S B D 9

10 MOS Transistors cont. mortant Dimensions of a MOS Transistor tox W : hannel lenth W: hannel width tox: oxide thickness aacitance OX G ε t OX OX OX W oxide caacitance er unit area ate caacitance 0

11 MOS Transistors cont. Drain urrent Equation in Saturation eion ncludin channel-lenth modulation and body Effects W D µ n OX GS tn λ DS K si ε o qn where λ λ Φ DS eff B tn tno γ SB Φ F Φ F where tno tn SB 0 and γ qn SUB OX ε si t to γ BS Φ F Φ F

12 Small-Sinal Model inear omonents inear esistor inear aacitor Q Deendent ircuits β r α S S S S y sloe The sloe corresonds to resistance, conductance, caacitance, transconductance, etc. x

13 Small-Sinal Model cont. inear roximation for Nonlinear omonents dy x0 d y x0 y x y x0 x x0 x x0 dx dx For small x x x, y y x y x 0 0 dy x dx 0 x y 0 y y x 0 dy x 0 dx x x. Find the oeration oint.. Determine the sloe, which determine the value for the linear comonent. 3. emove the D bias, and relace the device with the linear comonents. 3

14 4 MOS Small-Sinal Model m v s v s - G S D r ds mb v bs v bs - B tn GS D D OX n tn GS OX n Q GS D m W W v i µ µ F SB BS tn F F SB tno tn m F SB m BS tn tn D Q BS D mb v v i v i Φ Φ Φ γ γ η φ γ D DS D ds ds v i r λ α

15 MOS Device aacitances ariation of GS and GD versus GS fixed Saturation reion, P, P s s d sb db s 3 d d OX d s OX W W jd O W d overla ca. js P OX jsw O P jsw :source and drain areas :source and drain erimeters s W excludin the side adjacent to the channel 5

16 6 MOS Device aacitances cont. Triode reion ut-off reion sw j d jd d db sw j s js s sb O OX OX d O OX OX s tn GS OX n DS D ds ds P W P W W W W W W r µ del OX del OX b sw j d jd d db sw j s js s sb O OX d O OX s W W P P W W

17 Basic urrent Mirrors MOSFETs as urrent Source Biasin in saturation with a fixed ate voltae Usin resistive divider to rovide the ate voltae b Sensitivity to DD W µ nox b tn λ eff suly, rocess and temerature 7

18 urrent oiers Basic urrent Mirrors cont. D GS f f GS EF Diode-onnected device rovidin inverse function ssume λ0. urrent Mirror EF µ n µ n W / W / OX OX W W EF GS GS tn tn 8

19 Errors in urrent Mirrors Simle urrent Mirror in Outut resistance M in saturation reion : eff M M in - GS - W / λeff GS W / tn eff λ Μ Μ r ds 9

20 ascode urrent Mirror Suressin hannel-enth Modulation Effect cascode structure Outut esistance m 0 r ds3 m3 rds3 rds m r ds 0

21 ascode urrent Mirror cont. Head-room consumed by a cascode mirror N GS 0 N GS tn3 eff 0 µ W n OX eff EF / tn 0 tn0 EF µ W n OX / tn 0U simle cascode 80.0U 40.0U U 500M

22 ascode urrent Mirror cont. Minimum headroom voltae b GS tn b GS

23 ow-oltae ascode urrent Mirror Modified of ascode M for ow-oltae Wide- Swin Oeration b GS tn b tn GS eff eff M in saturation : X GS GS GS GS Min saturation : b GS GS tn b GS tn tn tn tn GS b GS tn b GS tn GS b tn tn GS GS tn 3

24 ow-oltae ascode urrent Mirror cont. Biased by a diode-connected transistor b M5 EF M M M4 M3 - W W W 5 W 3 W 4 n W n W W et Then, and eff eff eff 5 b EF eff eff 4. n n eff 3 n eff eff eff tn5 n EF W OX µ naccuracy due to eff eff Body effect Some marin is necessary to ensure saturation. educe the asect ratio for M5. tn5 4

25 ow-oltae ascode urrent Mirror cont. Desin for short-hannel Devices 5

26 eulated Drain urrent Mirror 6

27 Suly-ndeendent Bias Suly-Deendent Biasin esistive Bias olden reference current EF DD M M EF DD M M DD / m sensitive to DD W / W / Examle 7

28 Suly-ndeendent Biasin cont. Usin MOSFET only DD EF µ W / n OX n tn EF µ W / OX t 8

29 Suly-ndeendent Biasin cont. Suly-ndeendent Biasin DD DD W/ P KW/ N M 4 M 3 M B M W/ P W/ N W/ P W/ N M 3 M 4 M M B KW/ P W/ N µ tn Nelect the body effect. n W OX µ n OX N W N B µ K n OX K W N tn B Examle for on-channel devices 9

30 Suly-ndeendent Biasin cont. Short-hannel Device 30

31 Suly-ndeendent Biasin cont. Usin feedback to increase the ut resistance of MOSFET 3

32 Suly-ndeendent Biasin cont. mroved circuit 3

33 Outline nalo and Mixed-Sinal Desin in the SO Era urrent Mirrors and Biasin ircuits Sinle-Stae mlifiers Oerational mlifiers ay of nalo and Mixed-Sinal s 33

34 34 ommon-source mlifier ommon-source mlifier - N M 3 M M N DD bias // db db ds ds r r 3 0 ] [ d s s d d m d m d s in db m v s s s s s D ] [ where b a b s sa s d s s d in d m d s in m in m d

35 ommon-source mlifier cont. Miller s Theorem - Y - K / Miller aacitance K M riht v0 left m K m K d d d d -3dB Frequency - oen-circuit time constant method 3dB i i i m Y d Miller aacitor usually nelected in [ s M ] Y riht - Y Y K Y Y K Y Y Y K Y Y Y K 35

36 Source-Follower Source Follower DD in M in in s s d m s s s r ds bias N - rds rds / s sb db r ds M 3 M in in d s s m s v0 m / m m m s m s ds ds ds < ds / m No voltae ain ow ut resistance Not sufferin from Miller effect better frequency resonse Exhibitin lare amounts of overshoot and rinin under certain conditions 36

37 ommon-gate mlifier ommon-gate mlifier DD M 3 M bias bias M N S - r in r in s in m m s in s G ds s s ds ds S ds rin r in m r ds m G ds For r ds, r in m The ain is slihtly less than that of the common-source amlifier. Since the ate of the transistor is ac round, it does not suffer from Miller effect. Frequency resonse is suerior to that of S amlifier. 37

38 ascode mlifier bias M 5 M 6 N - DD bias in M 4 M 3 M M ascode mlifier o on Folded-ascode mlifier imrovin inut rane on o v0 For m m3 on in 3dB r m r << ds ds3 r r ds ds4 o, the - 3dB frequency is ususally dominant by the ut ole due to its lare ut resistance. 38

39 Differential Pair Differential mlifier i D i D v M M.5 i B 39

40 Differential mlifier cont. urrent Mirror oad -- are-sinal nalysis 0 0 SS M, M 3, M 4 : off M, M 5 : dee triode 0 SS SS SS f in in SS SS SS f in in SS SS 0 M : off M 4 : dee triode DD 40

41 Differential mlifier cont. /O haracteristic vs. DD For symmetric circuit, F 4

42 Differential mlifier cont. Small-Sinal nalysis symmetric Swins due to the oad alculation of Gm i G m i v in m vin m m vin v m in 4

43 43 Differential mlifier cont. alculation of Overall Gain r o4 X 4 4, 4 3 3, // // o o o X o X o X o m o X X r r r r r r r // r r db m v db db ds ds bias M ds bias M ds bias W OX n m r r 4 4 λ λ µ - in M M M4 M3 bias

44 Differential mlifier cont. Sinle-Ended vs Differential mlifier v ro // r m o For iven device dimension, this circuit requires half of the bias current to achieve the same ain as a differential air. However, advantaes of differential oeration often weih the ower enalty. 44

45 Differential mlifier cont. Power-Suly ejection atio PS DD M3 M4 M M o v dd i / m3 r o i r o4 v o B M5 PS d dd PS v 0 dd PS- ss v v PS o ss 0 d ss SS mainly due to mismatches dd d v v o dd v 0 s / r o s / // r o4 45

46 Systematic Desin roach Parameter Domains for haracterizin mlifier Performance Derees of Freedom: Small-sinal arameter domain r GB v m o Natural desin arameter domain m {, r m o} { W /, D} v µ n λ OX W / D GB µ n λ OX W / D lternate arameter domain { P, } v λ GB DD P 46

47 47 Systematic Desin roach cont. Desin Equations v M v d / -v d / B DD M M M5 MB B M3 M4 : α 3 min 5 max 5 4 5, 5 tan 80 // et DD D t DD D W ox n m v t n W ox n n W ox n m v n DD D n ds ds DD D D B DD B D GB S PM P GB P r r P P α α µ λ λ µ λ λ µ λ λ α α λ λ α α α α t SG tn GSn or bias : Excess

48 Systematic Desin roach cont. nut ommon-mode ane M M For M5 in the saturation reion, M- SD5min M DD 5 5 SG DD 5 For M in the saturation reion, SD M SG GS 3 t t 3 G tn3 D t t GS 3 t 48

49 Systematic Desin roach cont. Sread Sheet Method DD n ox n tn ox t µm, W0µm, DS0.85 and D00u α 3 BE5 vo vodb GB Hz f Hz PM S/us icmmax icmmin max min B D5 W/ W/3 W/5 49

50 Outline nalo and Mixed-Sinal Desin in the SO Era urrent Mirrors and Biasin ircuits Sinle-Stae mlifiers Oerational mlifiers ay of nalo and Mixed-Sinal s 50

51 deal Oams and lications deal Oam in- - in id o OUT N N id o 0 BW Oen oo OUT N OUT N sloe - 5

52 deal Oams and lications cont. lose oo with Neative Feedback OUT N N For and neative feedback, 0. nvertin amlifier N OUT virtual short N N N N OUT OUT Finite oen-loo ain N OUT OUT N OUT N OUT OUT OUT / 5

53 deal Oams and lications cont. Non-invertin amlifier N OUT N OUT N OUT Finite oen-loo ain N OUT Difference amlifier N N OUT N OUT N OUT N OUT OUT / 3 OUT 4 OUT For OUT and 4, 53

54 General onsiderations Stability Basic neative-feedback system Examle Y X H s s βh s oo ain : s βh s ssume β is frequency in deendent and β. N OUT β f β >>, OUT N OUT N. β / β β / β / 54

55 55 Stability cont. Barkhausen s riteria for oscillation Examle δ / 0 / 80 ] / [ 3 / / 3 / j j j j s s Z Z Z s s o. The system oscillates at o j j

56 Stability cont. Bode lot of loo ain for unstable and stable system o 80 0 db o 80 System is unstable, if j j o 80 0dB > < 80 o excess ain excess hase System is stable, if j j o 80 0dB < > 80 o 0 db o 80 : ain crossover oint GX : hase crossover oint PX 56

57 Stability cont. Time-domain resonses versus the ole locations σ j ex σ j t HP oles Unstable with rowin amlitudes mainary oles Unstable with constant-amlitude oscillation HP oles stable 57

58 One-ole system Stability cont. oo ocus β H s s / Y X 0 0 β s s /[ β ] unconditional stable 58

59 59 Stability cont. Multiole Systems Two-ole system 0 0 0, For 4 / / / / s s s s s X Y s s s H β β β β β ± still unconditional stable

60 Stability cont. Three-ole system β dditional oles and zeros imact the hase to a much reater extend than they do the manitude. f the feedback factor decreases, the circuit becomes more stable because the ain crossover move toward the oriin while the hase crossover remains constant. 60

61 Stability cont. Phase Marin System is stable, if j j o 80 0dB < > 80 o Small PM are PM Phase Marin PM j 0dB 80 Gain Marin PM 0lo j j Phase Marin PM j Y X Y X βh j j j 0dB 0dB 0dB 75 0dB H j0db βh j / β ex j75.5 β o ex j75 0dB o 0dB o lare eakin o o / β / j o 5 o 0dB 6

62 Stability cont. 45 hase marin j Phase Marin PM j Y X Y X j j 0dB 0dB 0dB 35 / β / β o ex j j β o βh j 0dB 30% eak 0dB 80 ex j35 o 45 o o 6

63 Stability cont. losed-loo time resonse for various hase marin Y X Otimum value β PM60, j0 db neliible frequency eakin little rinin and fast settlin Examle: unity-ain buffer lare-sinal ste resonse W/50 µm/0.6µm f t 50 MHz PM65 Nonlinearity of the circuit causes the variation of the oles and zeros durin transient. 63

64 Practical Desin Parameters s v s v s v v d OS cm cm dd dd ss s v ss Gain and bandwidth ain-bandwidth roduct Phase marin Slew rate and settlin time Offset voltae ommon-mode rane M ommon-mode rejection ratio M Power-suly rejection ratio PS v PS v PS dd ss M v cm 64

65 Practical Desin Parameters cont. inear Settlin Time due to the finite unity-ain frequency of the oam β in s For ste Simle first - order model of comensated oam : 0 s s / << <<, losed - loo ain : s s β s 0 β t and t s. s Note : β s / β a dominant - ole -3dB t t 0 βt τ Ste esonse: v v in t ste t ste u t e t / τ in s s ste % accuracy 4.6τ 0.% accuracy 6.9τ d ste Sloe t 0 dt τ f S > Sloe, no slew - rate limitin occurs. 65

66 66 Practical Desin Parameters cont. Examle: Oam Gain and Unity Gain Frequency for an D β β β β β β β 0.5SB / > < N O N O O v O O MHz f MHz f f N t N f f t N t K K settle t K settle N v F F F , f 84dB / 0.5, For 4 > > β β β settle settle N t t N N settle N t t t db t final t N t f t e e v settle > < < β πβ β τ β τ τ τ 0. ln ln ln, To settle within oam :unity - ain frequency of / 3 /,

67 67 Telescoic Oam Desin Equations 7 5 min 3 9 max , 9 tan 80 4 / 4 4 et DD D t DD D W ox n m v t n D n D m v n DD D n ds ds m ds ds m DD D D B DD B D GB S PM P GB P r r r r P P α α µ λ λ λ λ λ λ α α λ λ α α α α v B DD M M M9 MB M3 M4 : α B B M M6 M7 M8 D D ds m λ r / λ

68 Desin Equations Folded-ascode Oam B Q0 Q8 Q9 Q7 consumin more ower wider M slihtly larer ut swin B Q6 Q5 - in Q Q bias v0 3dB [ m6 ds6 m M r DD r ds Outut swin : r eff 3 DD ds3 ] tn eff 3 r m8 ds8 ds0 eff 6 r ~ M eff 8 effb eff 0 GS 68

69 Folded-ascode Oam cont. Bias urrents and Slew ate 0 > bias bias / bias / bias bias bias / bias bias ase bias bias bias < off bias bias bias bias S ase bias bias bias off bias bias bias bias bias bias S 69

70 Folded-ascode Oam cont. Puroses for Q and Q Q and Q are turned off durin normal oeration and almost have no effect on the oam. Q and Q act as clam transistors to revent the drain voltaes Q and Q from havin lare transients where they chane from their small-sinal voltaes to voltaes very close to the neative ower-suly voltae. Thus, the oam can recover more quickly followin a slew-rate condition. ncrease the slew-rate erformance of the oam: bias bias < S bias bias 70

71 Folded-ascode Oam cont. Desin Examle vo 4 [ αλ λ λ κ αλ 5 n n n 7 ] bias- M B DD M4 M3 GB α D µ W/ P Secification: vo db Set to calculate the erformance. alculation esults: vo db M DD GB MHz 5 GB MHz M5 P mw BE7 B µ M7 α S /µs 3 M M3 N- BE9 M- M9 M omax M M N omin casc- casc-n bias-n M6 M8 M0 MΩ M5 M7 OUT α B / M9 7

72 Gain Boostin ncreasin the Outut medance by Feedback m o o Gain Boostin in ascode Stae r r r r m o o reulated cascode v min m3 ro 3 m GS 3 m o o r m eff r r m3 o3 r r m o o 7

73 Gain Boostin cont. Gain Boostin for Differential ascode Stae min SS GS5 eff 3 73

74 74 Gain Boostin cont. Folded-ascode ircuit Used as uxiliary mlifier 3 min min, eff eff SS eff SS Y X ]// // [ o o m o m m m v o o m m o o m o o o m m r r r r r r r r r r

75 Gain Boostin cont. Gain Boostin lyin to Sinal and oad Paths n contrast to two-stae oams, where the entire sinal exeriences the oles associated with each stae, in a ain-boosted oam, most of the sinal directly flows throuh the cascode devices to the ut. Only a small error comonent is rocessed by the ain-boostin amlifier and slowed down. 75

76 Fully-Differential Oams in in v in in The Need for ommon-mode Feedback ircuits The inut and ouut common - mode levels are well defined, equal to DD SS D /. The inut and ouut common - mode levels are not well defined. Mismatches between the currents in PMOS and NMOS transistors may result in lare ut voltae chanes. P N P // N 76

77 ontinuous-time MFB ircuits ommon-mode Feedback MFB ircuits ommon-mode feedback with resistive sensin 77

78 ontinuous-time MFB ircuits cont. ommon-mode feedback usin source followers Note: and or and must be lare enouh to ensure that M 7 or M 8 is not starved at a lare ut swin. Sensin and controllin ut M level 78

79 S MFB ircuits Switched-caacitor MFB circuit more accurately defined M level eset mode : S on mlification mode : S M, off GS 6,7 GS 6,7 GS 5 eset mode : S,4,5 on, M GS 6 mlification mode : S 4,5 on, GS 5 M 79

80 S MFB ircuits cont. nother examle OUT OUT M φ φ φ φ M S φ φ φ S φ bias φ : φ : Q Q Q Q Q Q cntrl Q Q Q S S S 0 cntrl cntrl, cm S cntrl Q cntrl S S 0 cntrl cntrl cntrl cm cm S S bias bias, cm, cm cntrl cm For cntrl cntrl cntrl,, bias S cm bias cm cm bias cntrl 80

81 Two-Stae Oams Two-Stae MOS Oam with Outut Buffer Equivalent ircuit for Uncomensated Oam with c and M 6 m m m m7 r ds r ds6 // r ds4 // r ds7 8

82 8 Two-Stae Oams cont. D ain: Frequency esonse With omensation Due to the square-law nature, and are usually quite closed to each other. Phase marin is sinificantly less than 45. The oam must be comensated before used in a closed-loo confiuration. ' ' ' ' vo v s s s tan tan ] ][ [ ' ' ' ' v vo v j j / v v v vo m m v m v m v G

83 83 omensation With omensation aacitor c HP zero ] [ z m m m v tan tan tan z v z vo v j s s s s Translatin the dominant ole toward oriin to imrove stability Pole slittin as a result of Miller comensation

84 omensation cont. Unity-ain frequency and ain-bandwidth roduct Effect of HP zero ' ' Find unity - ain frequency. Since t >>, v s s t vo m vo vo v jt ain - bandwidth roduct t 84

85 omensation cont. Effect for the ut stae v d m v d v o m v o - - v o - m8 v o -v o r ds8 v o m9 v o r ds9 m9 v o - m8 v o v o v d - m v d v o - m v o v o - Find zero by settin v 0. v v m9 o m8 o Usin node equation at v, one can obtain s v [ s ] v 0 m o o o m8 m s [ s ] 0 m9 o m8 m m8 m8 m9 s[ ] m 0 sz m9 m9 m8 m9 For 9, s z m8 m m m HP zero 85

86 86 omensation cont. ead omensation z Several ways to choose Z : Takin Z / m, one can eliminate the HP zero. et z to cancel the nondominant ole. However, is often not known a riori. et z. t to increase the hase marin. unity - ain frequency 0 t z 3 m v Z Z m ] [ m m v

87 omensation cont. Other aroaches to emove HP zero Eliminatin forward sinal feedthrouh 87

88 omensation cont. ndirect urrent Feedback z mc HP zero 88

89 omensation cont. ndirect feedback comensation with additional ower dissiation 89

90 Desin Equations Slew rate First-stae ain m r Second-stae ain Gain-bandwidth First ole ds Second ole r ds4 Zero / m7 D5 λ λ m λ λ z m Z 4 t HP Zero S D5 / / D6 / / Positive M cmmax DD - SD5sat - SG Neative M cmmin SS GS3 T Positive ut swin max DD - SD6sat - GS8 Neative ut swin min SS DS9sat Power dissiation P diss D5 D6 D8 D0 D DD - SS W/, / /, W 3,4 3,4 W/ 6 / / W

91 Desin Equations cont. Nonlinear Settlin Time: due to slew-rate limitin Slew ate: the maximum rate that ut can chane S d dt d dt Offset oltae max cmax D5 D Since S andom offset: due to device mismatches resultin from rocess variations. emloyin matchin lay technique Systematic offset: due to desin error For D in D Since GS 3 D3 W / 3 in, D5 /. GS 4, D7 W / DS3 7 DS 4 GS 7 GS3 M3 and M7 is equivalent to a current mirror.. SG m t t and and t D5 W / m D6 5 W / W / 7 4 eff D7 D6 W / µ t 6 OX W / W / 6 5 W D d ste Sloe t 0 dt τ f S > Sloe, no slew - rate limitin occurs. lso for the current mirror M5 and M6,, 9

92 9 Desin Equations cont. lternate Desin Equations ] ][ [ 4 / / / // and //. and et n n v v v vo n W ox n n W ox n W ox n m v n m v n W ox n n W ox n m v n DD n D D n D ds ds m D n ds ds D n ds ds D DD D D D D P r r r r P λ λ λ λ λ λ µ λ λ µ µ λ λ λ λ µ λ λ µ λ λ α α α λ λ λ λ λ λ λ λ α α α α GB S PM x P D t z t t m m m m t z s m m DD D W ox n m t tan tan tan 90.. α α µ

93 omarison omarison 93

94 94 ascode-ascade Oam 9 9 z / / / / / / DD B Z DD Z Z m Z DD B m m DD vo DD m n n o o m m o o m o o m vo DD B DD GB P S P P P GB P GB P α α α α α α α λ λ λ λ λ λ α λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ α α DD SS in M M M3 M4 M5 in M8 c M6 c M9 o o M7 M0 M M M3

95 MOS Technoloy ow-oltae Oam 95

96 ow-oltae Oam cont. nut ommon-mode ane of a Differential nut Stae DDmin icmmax icmmin SD3 sat SD3 sat DD GS tn SD3 sat DS sat DS 5 sat GS tn DS5 sat DS5 sat For sat 0.3, DDmin 0.9 DD.5 and tn 0.7, icmmax.9 and icmmin.3 96

97 ow-oltae Oam cont. Parallel NMOS and PMOS Differential nut Stae onn on DSN 5 sat DD GSN SDP5 sat SGP Effective inut transconductance 97

98 98 ow-oltae Oam cont. onstant m Differential nut Stae Usin urrent omensation. 4, For., For. 4, For 0 et b n DD icm on b n on icm onn b onn icm n mt P OX N OX n P OX mp n N OX n mn W W W W < < < < < < β µ µ β µ µ

99 MOS Switches in ow-oltae Desin Pass Transistors 99

100 MOS Switches in ow-oltae Desin cont. Problem for the switch Use transmission ate. ncrease ate voltae to.3. arer lay area t may not turned on for low voltae. 00

101 MOS Switches in ow-oltae Desin cont. hare Pums oltae Generators 0

102 MOS Switches in ow-oltae Desin cont. hare-pum lock Driver Nonoverlain clock eneration circuit 0

103 MOS Switches in ow-oltae Desin cont. Bootstra circuit and switchin device.. M. bo and P.. Gary, ".5-, 0-bit, 4.3-MS/s MOS Pieline nalo-to-diital onverter, EEE Journal of Solid-State ircuits, vol 34, May

104 Desin concet Switched-Oam Switched-caacitor interator Switchable oam Switched-caacitor biquad Switched-oam biquad nut structure J.rols and M.Steyaert, Switched-oam: n aroach to realize full MOS switched caacitor circuits at very low ower suly voltaes, EEE J. Solid-State ircuits, vol. 9, , u

105 Switched-Oam Examle: Fully-Differential Switched-Oam MD M. Waltari and K... Halonen, - 9-bit ielined switched-oam D EEE J. Solid-State ircuits, vol. 36,. 9-34, Jan

106 Outline nalo and Mixed-Sinal Desin in the SO Era urrent Mirrors and Biasin ircuits Sinle-Stae mlifiers Oerational mlifiers ay of nalo and Mixed-Sinal s 06

107 ay onsiderations Differences Between ay and ircuit The differences are mainly due to the followin reasons: ateral diffusion Etchin under the rotection Boundary deendent etchin Error in the attern size due to Tri-dimensional effects These effects are not very substantial for diital systems; but they may have a sinificant imact on the accuracy of analo circuits and must be avoided or comensated. 07

108 ay onsiderations cont. bsolute and elative ccuracy 08

109 ay onsiderations cont. ay of an analo MOS transistor Poor lay and its equivalent circuit orrect ay Metal rofile with multi-contacts and only one contact 09

110 ay onsiderations cont. ay of a wide transistor Poor lay orrect lay slit into several arallel transistors educin sb and db 0

111 ay onsiderations cont. ay of Matchin Transistors Sources causin transistor mismatches Gradient effect existin in the fabrication rocess To minimize the effect, two transistors that must be matched to each other should be laced very close. For wide transistors, lay techniques to imrove matchin must be emloyed.

112 ay onsiderations cont. MOS Matchin Model T σ t W σ β β β W

113 3 ay onsiderations cont. Errors in Matched MOS Transistor Pairs / β β σ σ σ σ β β σ σ m t GS t m DS DS T m m t m β σ β β σ

114 ay onsiderations cont. 4

115 ay onsiderations cont. ays of a Differential Pair Normal lay nter-diitized lay ommon-centroid lay 5

116 ay onsiderations cont. Orientation of transistors Poor lay of transistors with different orientation Boundary deendent etchin omensation of boundary deendent etchin with dummy elements 6

117 ay onsiderations cont. ay or esistors W cont s W : sheet resistor Ω / sq s ay of two matched resistors 7

118 ay onsiderations cont. esistance is temerature-deendent. Matched resistors should be arraned with their centroids laced symmetrical with resect to the ower devices. esistor realized by well diffusion 8

119 9 ay onsiderations cont. ay of aacitors ross-section and lay of a caacitor Matchin deends on the erimeter. ' : Undercut xp W x W x x W W P W t ox ε ox

120 ay onsiderations cont. ay of ratioed caacitors Matched caacitor with common-centroid symmetry aacitors with non-inteer Multile of unit caacitor 0

121 ay onsiderations cont. ay of nalo ells Guidelines Use transistors with the same orientation. Minimize the source or the drain contact area by stackin transistors. esect the symmetries that exist in the electrical network as well as in the lay to reduce offset. Use low resistive aths when a current needs to be carried. Shield critical nodes. Examle: two-stae Oam Placement of transistors in a stacked fashion

122 ay onsiderations cont. orresondin lay Use of dummy transistors in the lacement of transistors

123 ay onsiderations cont. Diital Noise oulin aacitive coulins nalo lines red arallel to the diital lines Searation to reduce horizontal coulin Dummy line for horizontal shieldin rossin between analo lines and clocks 3

124 ay onsiderations cont. oulin throuh the substrate Usin well-shieldin Noise njection throuh the ower suly 40 tot tot analo diital analo d dt tot 4

125 ay onsiderations cont. educe : keein the diital and analo sections as searate as ossible and merin them at the lace very close to the suly ad. f ossible, use searate ads for the analo and diital section. When extra ins are available, searate ins for the analo and diital suly should be used. Place the suly ins in the middle of the frames. 5

126 ay onsiderations cont. Floor Plannin of Mixed-Sinal Blocks General uidelines Put the analo critical comonents as far as ossible from the diital elements. Make the connections to the critical nodes as short as ossible. void crossin between the analo biasin lines and diital busses. Path of bias and suly lines for basic analo cells Tyical floorlan of an S filter 6

127 ay onsiderations cont. Tyical floorlan of a fully-differential S filter Tyical floorlan of a mixed-sinal chi 7

128 ay onsiderations cont. Block Diaram ay of a Pielined D 8

129 ay onsiderations cont. Decoulin aacitors in a Mixed-Sinal hi 9

130 eferences. J. Baker, MOS: ircuit Desin, ay, and Simulation, EEE Press, 005. P. E. llen and D.. Holber, MOS nalo ircuit Desin, Oxford University Press, nc., 00. B. azavi, Desin of nalo MOS nterated ircuits, McGraw-Hill, nc., 00. D.. Johns and K. Martin, nalo nterated ircuit Desin, John Wiley & Sons, nc., 997. J. E. Franca and Y. Tsividis, eds., Desin of nalo- Diital S ircuits for Telecommunications and Sinal Processin, Prentice-Hall,