ECEG 351 Electronics II Spring 2017

Transcription

1 G 351 lectronics Sprin 2017 Review Topics for xa #1 Please review the xa Policies section of the xas pae at the course web site. Please especially note the followin: 1. You will be allowed to use a non-wireless enabled calculator, such as a T You will be allowed to use one inch two-sided handwritten help sheet. No photocopied aterial or copied and pasted text or iaes are allowed. f there is a table or iae fro the textbook or soe other source that you feel would be helpful and that is not included on the forula sheet will provide to you, please notify e. 3. All help sheets will be collected at the end of the exa but will be returned to you later. The followin is a list of topics that could appear in one for or another on the exa. Not all of these topics will be covered, and it is possible that an exa proble could cover a detail not specifically listed here. However, this list has been ade as coprehensive as possible. Althouh sinificant effort has been ade to ensure that there are no errors in this review sheet, soe iht nevertheless appear. The textbook is the final authority in all factual atters, unless errors have been specifically identified there. You are ultiately responsible for obtainin accurate inforation when preparin for your exa. nternal structure of bipolar junction transistor (JT) - npn: thin p-type base sandwiched between n-type eitter and collector - pnp: opposite of npn - base-eitter () and collector-base () junctions are reular pn junctions and act the sae way (i.e., they can be forward or reverse-biased; they have turn-on voltaes) JT circuit sybols - pay attention to directions of arrows (arrow indicates the eitter terinal and JT type; arrow of npn is not pointin in ) npn pnp npn vs. pnp JTs - v and v of npn JTs have positive values in noral operation - v and v of pnp JTs have neative values in noral operation (use v and v, which are positive, instead) - i and i flow into base and collector terinals of npn JTs and out of base and collector terinals of pnp JTs - i-v characteristics of npn and pnp JTs have voltaes of opposite sin 1 of 5

2 Qualitative understandin of operation of JT - turn-on voltae (V F ) of base-eitter junction (approx. 0.7 V for Si) - effect of chanin base current i - effect of chanin collector-eitter voltae v (norally junction is reverse biased or at least not heavily forward biased; necessary for collector current to flow) - directions and polarities of iportant currents and voltaes (i, i, i, v, v ) - thin base reion required to allow electrons (npn) or holes (pnp) to flow fro eitter to collector - eitter ore heavily doped than base allows base to fill with inority carriers (electrons for npn; holes for pnp) when base current flows - base-eitter junction is forward biased if v is at turn-on voltae (V F ) - i-v characteristic of junction is the sae as that of a pn-junction diode: v nv i T Se, where S = saturation current of junction, n = eission coefficient (typically assued to equal one), and V T = theral voltae, which is iven by T V T =, where T = teperature in kelvins (V T = 25 V at roo tep.) 11,600 - collector-base junction is usually reverse biased (produces depletion reion) or lihtly forward biased - collector current related to base current by i = βi in the active reion, where β = forward D current ain (values are typically , but vary aon JT types, even aon individual units of a iven type within the sae anufacturin batch) - β varies stronly with teperature General analysis techniques for JT circuits - deterination of reion of operation (cutoff, active, or saturation) o try to deterine if base-eitter junction is forward biased, if possible; helps to rule out (or not) cut-off reion o assue JT is in one reion and analyze the circuit based on that assuption o check all voltaes and currents and deterine whether or not their values are consistent with the initial assuption. f so, analysis is coplete. f not, use the results of the initial analysis to deterine likely reion of operation. Repeat analysis under new assuption and confir. - v (for npn JTs) is always positive (neative for pnp; i.e., v is positive for pnp) - v 0.7 V (for Si npn) in the active and saturation reions - in cut-off reion, i = i = 0 and v < 0.7 V (for Si npn) - in active reion, v 0.7 V, i = βi and v > v sat V (for Si npn) - in saturation reion, v 0.7 V, i < βi and v = v sat V (for Si npn) - for ore accurate analysis (rarely necessary), use v nv i T Se, where S = saturation current, n = eission coefficient (typically assued to equal one), and V T = theral voltae JT inverter circuits - can be used as loical NOT ates - transfer characteristic (v o vs. v in ) has neative slope in active reion and nearly zero slope in cut-off and saturation reions - JT inverter is also called a coon-eitter aplifier - has an alost linear transfer characteristic in active reion 2 of 5

3 Four-resistor JT biasin circuit V V R R R 1 V equiv. to R V R 2 V V + V R R - for analysis purposes, can represent base biasin network by a Thévenin equivalent circuit consistin of: V R2 = V R1 + R2 and R = R R 1 2 siplifies evaluation of - desin for quiescent output voltae, collector current, and/or voltae drop across eitter resistor (if present) - usually bias JT for operation in the active reion - the paraeter β has stron teperature dependence and device variation - neative feedback via eitter deeneration resistor (R ) stabilizes - current throuh R 1 and R 2 is typically desined to be 0.1 to 1 ties (or ties ); upper end of that rane is excessive in ost cases - resistors R 1 and R 2 do not behave as a true voltae divider because 0; however, they approxiate a voltae divider because should be sall copared to current throuh R 1 and R 2 (1/10 or less) - trade-off: hiher current throuh R 1 and R 2 leads to ore stable quiescent point but lower input resistance and hiher current deand fro power supply - 1 coon desin rule of thub: R R = V, althouh the voltae across R 3 is soeties desined to be less than this (e.., if V set to V /3) - variation for bipolar (pos./ne.) power supplies: use R and R but only a sinle resistor (R ) fro base to round General sall-sinal odelin - definition of increental sinal (sall sinal) - separation of bias considerations (quiescent levels; output voltae swin rane) fro sall-sinal considerations (ain, input and output resistance) - replaceent of D voltae sources with short circuits (because the voltae across a D voltae source cannot chane with tie) - replaceent of D current sources with open circuits (because the current throuh a D current source cannot chane with tie) - D voltae sources are typically bypassed at A (i.e., at sinal frequency) usin capacitors - sall-sinal odel of JT is valid only when device operates in the active reion but not in cut-off or saturation reions - sall-sinal odel of FT is valid only when device operates in the saturation reion but not in cut-off or triode reions 3 of 5

4 - derivation of sall-sinal voltae ain - difference between open-circuit ain A vo, aplifier ain A v, and overall ain G v - derivation of sall-sinal input resistance R in ; test source usually necessary - derivation of sall-sinal output resistance R o ; test source usually necessary - siplifications in ain/resistance expressions when one ter is uch reater/saller than another ter - derivation of the input or output resistance lookin into a particular pair of terinals usin a test source (v t and i t ) Source: Sedra & Sith, Microelectronic ircuits, 7 th ed., 2015, p Two-port aplifier representation (refer to diara above) - v in and v o are the voltaes easured at the aplifier s input and output terinals; note that in eneral v in is not the sae as v si (Thévenin equivalent source voltae) - a set of input or output terinals is soeties called a port - input port of aplifier has an equivalent input resistance R in - A v = voltae ain with load; A vo = open-circuit voltae ain (R L ) - no-load ain assues that R L, not R L = 0 - output port of aplifier can be represented as a Thévenin equivalent circuit with dependent voltae source A vo v in and output resistance R o - relationship between source resistance R si and input resistance R in required to axiize input voltae or current to aplifier - relationship between output resistance R o and load resistance R L required to axiize output voltae or current fro aplifier Sall-sinal odelin of JT circuits - sall-sinal odels of JT: hybrid-pi odel and T odel - sall-sinal condition: v be << nv T, where n = eission coefficient (usually assued to equal unity); and V T = theral voltae, related to teperature T in kelvins by V T = T/11,600 - increental base-eitter resistance r π and what it represents (finite slope of i -v characteristic of base-eitter pn-junction, which obeys diode equation): nvt β r π = = = re ( β +1) - increental collector-eitter resistance r o (called transistor output resistance in the textbook) and what it represents (non-zero slope of i -v characteristic in the active reion); typically 50 kω or ore for JTs - relationship between sall-sinal output port resistance (collector-eitter resistance) and arly voltae (V A ): VA ro - dependence of of JT on quiescent collector current : = nv T 4 of 5

5 - relationship between α and β (where = α ): β α = β +1 - eitter resistance r e in T odel of JT: α rπ re = = β +1 - derivation of fro i vs. v equation (diode eqn applied to junction) - effect of eitter deeneration resistor (R ) on ain, input resistance - effect of aount of neative feedback (1 + R ) on peak allowable input voltae in aplifiers with eitter deeneration and its derivation - typical values of iportant JT and circuit paraeters such as β, r o, bias resistor values, and saturation voltae - pnp sall-sinal odel: directions of i b and βi b and polarity of v be sae as for npn odel - data sheet notation: h F = β; h fe = β; h ie = r π ; h oe = 1/r o asic aplifier desin - identify ost restrictive specifications - use analysis to derive relationships between coponent and device paraeters (i.e., quantities like β and resistor values) and specified perforance requireents such as ain and input/output resistance - desin bias network to adjust, swin rane, and other paraeters to satisfy specifications - select capacitor values, bypass arraneents, etc.) to eet reainin specifications or to confir that iniu perforance requireents will be et Relevant course aterial: HW: #1, #2, #3 Labs: #1, #2 Readin: Assinents fro Jan. 16 throuh Feb. 8, includin: Source Deeneration iasin for Discrete MOSFT Aplifiers This exa will focus priarily on course outcoe #1 (only the aterial applicable to JT circuits) as listed on the ourse Policies and nforation sheet distributed at the beinnin of the seester and also on the ourse Description pae of the course web site. 5 of 5