Polytech Montpellier MEA M2 EEA Systèmes Microélectroniques. Analog IC Design

Transcription

1 ours I - 03/04 - Séane 6 8/03/04 Polyteh Montpellier ME M EE Systèmes Miroéletroniques nalo I Desin hapter VII OP stability and ompensation Pasal Nouet / nouet@lirmm.r Your irst nalo Desin V dd =3.3V T T 8 T 9 T 0 V I ds T V- V+ T 5 T 6 T T6 T 3 I ds7 I ds3 T V bias T 7 T 3 T 4 Voltae reerene Dierential pair ommon soure urrent soures tie load ommon drain ompensation

2 ours I - 03/04 - Séane 6 8/03/04 OP stability 3 Introdution Miller OT is a two-stae ampliier with hih output impedane V dd D ain m out m out V+ V- Open-Loop Dynami I Perormanes bias Slew-Rate (V/s) : SR Unity-ain requeny (MHz) : u ut-o requeny / bandwidth (khz) : Gain-Bandwidth produt (MHz) : GBW or a irst order behaiour, GBW= u I bias V dd

3 ours I - 03/04 - Séane 6 8/03/04 Introdution 5 Soure L o V G >V t Gate V D >>V e s d Drain p+ n+ n+ sb db p- NMOS Gate apaitanes s d WLox WLo 3 WL o ox ox L L o 0 Juntion apaitane (reerse bias) db d jd h js sb S j0 jx Vxb 0 Introdution 6 MOS Transistor "Small Sinal" model or dynami analysis d G D s S s m s r ds db S ds sb 3

4 ours I - 03/04 - Séane 6 8/03/04 First Pole nalysis 7 T 3 V dd T 4 s T in ds m ds4 in d in? V in - T T V in + I bias I bias d 4, d V bias T 7 T 3 d 0 % s 3 oxp W L Miller Transormation i i E i' E i' S i S i E i' E i' S i S V in -.V in V in -.V in i E i i i pv out Vin i E ' E pv i E Input urrent out pv pv in i ' i in E ' E ' is i is p V ' S i Output urrent out Vin is pvout i S 4

5 ours I - 03/04 - Séane 6 8/03/04 Miller Transormation With > 0 et >> : i E i' E i' S i S V in -.V in Pole due to First Stae Output 0 V dd V in - T 3 T 4 m s in ds ds4 in T d in s p d p T T V + in in s d p I bias I bias V bias T T 3 7 ds m ds4 in in p ds ds4 5

6 ours I - 03/04 - Séane 6 8/03/04 response -0 db/déade -40 db/déade er pôle ème pôle Voltae ollower 6

7 ours I - 03/04 - Séane 6 8/03/04 Voltae ollower 3 T=50ns os =0MHz 4 response -0 db/déade -40 db/déade er pôle ème pôle 7

8 ours I - 03/04 - Séane 6 8/03/04 Summary 5 Simpliied Model One stae One pole First stae pole is dominant (Miller Eet) two stae mpliier should be stable Simulation simulations :, u and GBW Other poles (urrent soure, ) Oten, a two stae ampliier is not naturally stable OP ompensation 6 8

9 ours I - 03/04 - Séane 6 8/03/04 Dominant pole adjustment 7 Idea: st pole shits down to low requenies by addin in parallel with d example: d total ds 500Hz 6 ds.. 3,6.0 5 pf total ds ds4 T 3 T 4 V dd V- V+ T T V bias mpliier behaes like a irst order iruit GBW I bias7 T 7 T I bias3 T 3 8 = 00F pf 5pF 0pF =59Hz 9

10 ours I - 03/04 - Séane 6 8/03/04 lose-up iew o the Miller eet 9 Vdd T 3 T 4 V V- V+ T T V bias I bias7 T 7 T I bias3 T 3 r ds // ds4 r d ds d // d 4 ds3 d3 d // s load load m. in r m. out r lose-up iew o the Miller eet 0 m. in r m. out r out out out out m. in p. out p. ( in, out ) r m. out out r out out p. out r p a r m b r r p p. out in out out m r m. in r p r m r m ap bp r r m m. out r 0

11 ours I - 03/04 - Séane 6 8/03/04 lose-up iew o the Miller eet m. in r m. out r out in ap bp mr ap bp p mr m p p p p p p z r m r m m Inreasin z and p are shited down aordinly Inrease o m silion ost, power onsumption Desin Tip : hiher m inreases stability lose-up iew o the Miller eet Solution: addin a serial resistane st and nd poles doesn t moe a lot dditional 3 rd hiher requenies Zero is haned: z Zero an be adjusted m R to ompensate nd pole (not robust enouh) just ater the unity ain requeny (iable solution) R s s m. in r m. out r

12 ours I - 03/04 - Séane 6 8/03/04 Zero positionin or stability: irst method 3 Step : First simulation with random 0 (5pF) and R s =0 hoie o a phase marin extrat u measure ( u ) Vdd T 3 T 4 V- V+ T T V bias I bias7 T 7 R s T I bias3 T 3 Step : alulation o = 0. ( u ) Zero u +0% R s alulation Zero positionin or stability: nd method nd method: hoie o unity-ain requeny: Example: rom initial u =8MHz 4 u 0MHz alulation o the apaitane: m u Zero positionnin i u + 0% : MHz z MHz R s R z m m s

13 ours I - 03/04 - Séane 6 8/03/04 Lab work : OP ompensation 5 OP haraterization 6 V dd =3.3V T T 8 T 9 T 0 I ds T T V- V+ T 5 T 6 T 3 I ds7 I ds3 T V bias T 7 T 3 T 4 OP used as a oltae ollower: apply a oltae step at the input I iruit is stable (GBW is low), inrease open loop oltae ain by inreasin output resistane o irst and seond ampliier stae Usin analysis and bode diaram, alulate a ompensation iruit or your OPMP 3

14 ours I - 03/04 - Séane 6 8/03/04 onnexion MERH4 mkdir MS035 mkdir = make diretory (dir name an be hoosen reely) d MS035 d = hane diretory soure /sot_eii/adene/.oni_ms40 ams_ds -64 -teh 35b4 -mode irt & will prepare your older (diretory) to desin in MS 35B4 tehnoloy Next runs : ams_ds -64 4