# V DD. M 1 M 2 V i2. V o2 R 1 R 2 C C

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1 UNVERSTY OF CALFORNA Collee of Enineerin Department of Electrical Enineerin and Computer Sciences E. Alon Homework #3 Solutions EECS 40 P. Nuzzo Use the EECS40 90nm CMOS process in all home works and projects unless noted otherwise. n this homework you may use just the typical (tt) device parameters.. Pole-Zero Doublets: n this problem we will be lookin at the behavior of the pseudo-differential amplifier shown below to ain some intuition into the oriin and response of pole-zero doublets. You can assume that M and M form a differential pair (i.e. their small sinal model parameters are identical) with infinite small-sinal output impedance (r o ). Moreover, you can assume that R is larer than R, and all capacitors are neliible with the exception of the ones explicitly drawn in the diaram. V DD V i M M V i V o V o R R C C a. Derive an expression for the transfer functions H (s) V o (s) /V i (s) and H (s) V o (s) /V i (s) in terms of R, R, C and the transistors m. This question is really just askin for the ain of a common source (CS) stae. H (s) V o (s) /V i (s) and H (s) V o (s) /V i (s) can then be derived by inspection as follows: ( ) m H s m R Cs + R Cs m H s m R Cs + R Cs ( ) R R

2 b. Sketch the manitudes of H and H versus frequency on the same plot. H (ω) db H (ω) db m R m R -0dB/dec /R C /R C m/c ω c. Now derive and sketch the time-domain voltae response of V o to a voltae step on V i. Similarly, derive and sketch the time-domain voltae response of V o to a voltae step on V i. Althouh this problem is obviously solvable with inverse Laplace transforms, let s take a simple intuitive approach. We know that initially C looks like a short circuit, and so at t 0, V o 0 as well. We also know that C will eventually become an open circuit, so at t, V o - m R. Finally, we know that the time constant of the settlin will be R C since that is the location of the pole. Now all we have to do is use this information to plu values into an equation that ives the time domain response of a sinle-pole system: V t V + V V e t RC o( ) initial ( final initial )( ) V t R e t RC o( ) m ( ) Similarly, for V o we obtain V t R e. trc o( ) m ( ) This answer is indeed correct and requires essentially no math to reach. However, just to show a more formal method of solvin the problem, we can reach the same result usin inverse Laplace transforms to solve for the step response V o (s) as follows: mr Vi () s Vo () s s s R Cs and rememberin that ( + ), L t τ ( e ) ss ( τ + ).

3 0 Step Response - m R Amplitude - m R Time (sec) d. Usin the results from part a. and part b., sketch the manitude of the transfer function for differential ain H(s) (V o -V o )/(V i -V i ). Since we are just interested in the differential ain, we can assume that the amplifier is driven by a purely differential sinal (no common mode) such that V d V i -V i. Therefore, we have V i V d / and V i -V d /. Moreover, we observe that V o will totally be determined by V i and, similarly, V o will totally be determined by V i. Therefore, usin the results from parts a. and b., we can write: Vd Vd Vo Vo H() svi H() svi H() s H() s Vd ( H() s + H() s ) V ( () () o V H s + H s o ) m R R H() s + Vi Vi + RCs + RCs RR + C s m R R R R ( + ) + ( + R Cs)( + R Cs) We can certainly draw the Bode diaram directly startin from the expression of H(s) computed above. As an alternative, we can still use the Bode diarams part b. to sketch the one of H(s). n fact, we found that H(s) is practically the arithmetic mean of H (s) and H (s), with a sin inversion. The manitude of H(s) can then be inferred from the manitude of the mean of H (s) and H (s). However, care must be taken to manipulate the plots of H (s) and H (s) when they are in loarithmic scale. The result is shown in the fiure below. We observe that H(s) has a lower frequency pole ω p /(R C) and a hiher frequency pole ω p /(R C), which are respectively associated with the left and riht side of the pseudo-differential amplifier. Since ω p kicks in at lower frequencies with respect to ω p, there is a frequency band in which the contribution of M to the differential ain becomes practically neliible with respect to the contribution iven by M, which creates a zero at the frequency ωp + ωp R+ R ωz +. R C R C CR R 3

4 H(ω) db m R m (R +R )/ m R -0dB/dec /R C /(R R )C /R C m /C ω n this frequency band where the sinal on the left side of the circuit is essentially bein heavily filtered out while the sinal on the riht side of the circuit still has ain, the overall differential ain is dominated by the riht side of the circuit i.e., the ain is simply equal to m R. e. Now sketch the time-domain voltae response of the differential output V o -V o to a differential voltae step (V i -V i ). While you can certainly derive this response usin inverse Laplace transforms and partial fractions, you may find it sinificantly easier to use your answers from the previous sections instead. Without havin to solve for the time domain solution mathematically, we know that both capacitors will initially look like short circuits, which means that the output will start at 0. Eventually the response settles to m (R +R )/. Moreover, the system has two poles and one zero as seen in part d. Since this is a linear system, we expect the step response is a combination of two exponentials such as: ωpt ωpt ( ) ( ) + ( ) V t V e V e V do f f f f ( + ) m R R + V () All that we need to do is to determine V f and V f. However, we have seen in part d. that H(s) can already be split into the sum of two rational functions, each associated with one of its poles: mr/ mr / H() s + + R Cs + R Cs. () We can therefore immediately conclude from () that the desired step response is V do R R +. m ( ) trc ( e ) ( ) m trc t e As evident from the above expression, the step response of the differential voltae can also be obtained by combinin the step responses found in part c, adequately scaled. A sketch of this response, overlapped with the plot of its components is shown below. 4

5 Step Response m (R +R )/ m R / Amplitude m R / 0 Time (sec) As we deduce from the above fiure, the dominant pole ets the output voltae most of its way towards its final value while the fast non-dominant pole ets it the rest of the way. This is basically always the case for the eneric transfer functions with two poles and one zero, when there is a dominant pole. To be convinced about this, let us look for an approximate mathematical model for the step response of a eneric transfer function below: H () s ( + s ω ) ( + s ωp )( + s ωp) z. (3) The system described by H (s) can always be decomposed into two sinle-order systems usin partial fraction decomposition A H () s + B ( + s ωp ) ( + s ωp) where A and B need to satisfy A+ B A ωp + B ωp ωz With a little bit of alebra, this comes out to: ( ) ( ) ( ) ( ) ω ω z ωp z p p ω ω ω p A B ω ω ω ω ω ω z p p z p p which ive us the coefficients of the exact step response. However, if ω p >> ω p, B can very well approximated by ω p /ω z since ω p ωp ωp ω ω z p B as ωp ωp 0 ω ( ωp ωp ) z 5

6 and therefore A can be approximated as ( ω p / ω z ). n other words, when the second pole is truly non-dominant, we can approximate the step response of H (s) as: ωp ( ) ωp t ωp ( ) ωp t + ( ) h t e e ωz ωz. From this expression, we can conclude aain that the dominant pole ets us most of the way towards the final value while the fast non-dominant pole ets us the rest of the way. This approximation can be extremely accurate in many practical cases of interest. Note that there are other methods you could have used to arrive at an answer for this question. Any solution that follows a physically correct line of thinkin and arrives at a reasonable result will receive full credit.. Switched-capacitor amplifier: What is the total noise variance at the output of the switched capacitor amplifier shown below at the end of a complete cycle (i.e., durin φ )? You can assume that the OTA is simply implemented by an NMOS common-source stae with a iven m and infinite r o. φ C f φ V i φ φ C s φ φ - + V o Durin φ, all we are really doin is samplin V i onto C s. Given that V i has some finite source resistance (and hence some thermal noise associated with it), when φ oes low, we will sample a noise variance of kt/c s. Once φ oes hih, this noise voltae will appear at the neative input of our OTA, which will respond to it by transferrin that chare onto C f and restorin the virtual round. Therefore: v o, Vi kt Cs kt Cs Cs Cf Cf Cf. To et the total noise at the output, we just need to look at the noise contribution of the OTA itself durin φ. First, let s draw the small sinal equivalent circuit (inorin the noise sampled onto C s ): C s v i C f m v i i M V o f you look at this circuit, you should pretty quickly realize that the transistor is essentially in a diodeconnected confiuration just that there is a capacitive voltae divider between the drain and the ate. So, the effective resistance of the transistor will just be (C f +C s )/(C f m ). Since the effective load capacitance is C s C f /(C s +C f ), the noise at the output due to the OTA will be: 6

7 v v o, m ( + s) m ( + ) s f o, m + Cf Cf Cs ( + ) C C C kt C C 4kTγm γ 4CC C C C CC kt C C γ f f s f s f f s f s f Therefore, the total noise at the output will be: v kt C C + γ + s f o Cf C f Cs Note that the above calculation assumed that the switches were ideal, and hence did not include any noise sampled onto C f durin φ. f the switches were not ideal, there would be an additional kt/c f of noise voltae variance at the output. 3. Gain Boosted Cascode: This problem will focus on the ain-boosted cascode amplifier shown below. To simplify the analysis, you can inore the r o of the transistors and all of the capacitors except for those explicitly drawn in the diaram. v 3 v 4 M C C3 M3 v v M C a. What is the frequency response H(s) v 3 (s)/v (s) of this amplifier? Approximately what is the unity ain frequency of the amplifier? As usual, let s first draw the small sinal model: v 4 C 3 m3 v m (v -v 4 ) v m v C C v 3 7

8 The fastest way to fiure out the frequency response of this amplifier is just to look at how much of the current from M will make it to flow into the output load (i.e., C). f we look at the input impedance of M from node v, it will be: Z 4 m3 im, m ( v4 v) v sc3 sc3 ZiM, sc m ( + ) m3 3 v Now we can just use the current divider between Z i,m and /sc : sc sc sc sc out, M M + 3 m ( m3 + 3) m ( m3 + sc3 ) M ( m3 + 3) s( C3 m3 ) ( ) ( ) out, M m sc s C C out, M M s CC 3 mm3 + s C3 m3 + From here, it is easy to see that: ( 3 m3 ) ( ) ( ) + s C m H( s) s CC 3 mm3 s C3 m3 + + sc As lon as the amplifier is desined to be stable under unity-ain feedback, the dominant pole of the circuit should be set by the output load, and so the unity ain frequency is still just m /C. b. Approximately what conditions are required to uarantee that the ain boostin feedback loop maintains at least 45º of phase marin? You should provide your answer in terms of m, m, m3, C, C, and C 3. What conditions would we obtain if at least 60º of phase marin are required instead? The unity-ain frequency of the ain-boostin CS amplifier is approximately ω u m3 /C 3, and we know that the pole at the source of the cascode is approximately ω p m /C. Therefore, in order to achieve 45º of phase marin, the non-dominant cascode pole must be reater than the unity-ain frequency of the ain-boostin amplifier, i.e.: m m3. () C C 3 n fact, iven the loop ain transfer function for the ain-boostin feedback loop m3 T ( s), sc s C + ( ) 3 m we recall that the phase marin is defined as π ω u π ω u φm π + T( jωu) π arctan arctan. ω ω p p Therefore, to achieve at least 45º of phase marin, we need 8

9 π ω u π ωu arctan ω p 4 ωp () as required in (). f at least 60º of phase marin are required instead, we should modify () as follows π ω u π ωu arctan, ω p 3 ωp 3 which finally ives m 3 m3. C C 3 c. Assumin this amplifier is used in unity ain feedback, what conditions are required to uarantee that the ain boostin feedback loop does not introduce any sinificant pole-zero doublets that miht limit the settlin response? What we re basically tryin to ensure is that the ain-boostin loop settles faster than the ainbandwidth of the overall amplifier. Therefore, we can pretty quickly say that: C m3 C m 3 Another (more mathematical) way of arrivin at this constraint is realizin that open-loop zeros do not move under feedback. This means that when if we close the entire amplifier in unity ain feedback, if we want to ensure that there is no closed-loop pole-zero doublet inside the unity-ain bandwidth, the zero (which is at m3 /C 3 ) must be outside the closed-loop bandwidth (which is m /C ). d. Assume now that C C 3 50 ff, C.5 pf, V* M 80 mv, and V* M 90 mv. n order to achieve at least 60º phase marin and the criteria from part c), what are the minimum and maximum m3 / m? Combinin the solutions from b) and c) we et: C C ff pf m m3 m m m3 m 3C ff 50.5 (3) We also know that D D, and so: D m V M D m V M m m D * 80mV D * 90mV 9

10 Pluin back in to the inequality in (3), we finally et: m 0. m3 m m3 m 0

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