Lecture 21. REMINDERS Review session: Fri.11/9,3 5PMin306Soda in 306 (HP Auditorium) Midterm #2 (Thursday 11/15, 3:30 5PM in Sibley Auditorium)

Transcription

1 Lecture EMINES eiew session: Fri./9,3 5PM306Soda 306 (HP Auditoriu) Midter # (Thursday /5, 3:30 5PM Sibley Auditoriu) OUTLINE Frequency esponse eiew of basic concepts hih frequency MOSFET odel S stae G stae Source follower ascode stae ead: hapter EE05 Fall 007 Lecture, Slide Prof. Liu, U Berkeley

2 A oll Off due to L The ipedance of L decreases at hih frequencies, so that it shunts soe of the put current to round. λ 0 p L A j L In eneral, if node j the sinal path has a sallsinal resistance of j to round and a capacitance j to round, then it contributes tib t a pole at frequency ( j j ) EE05 Fall 007 Lecture, Slide Prof. Liu, U Berkeley

3 Pole Identification Exaple λ 0 p G p L EE05 Fall 007 Lecture, Slide 3 Prof. Liu, U Berkeley

4 Pole Identification Exaple λ 0 p G p L EE05 Fall 007 Lecture, Slide 4 Prof. Liu, U Berkeley

5 eal with a Float apacitance ecall that a pole is coputed by fd the resistance and capacitance between a node and (A) GOUN. It is not straihtforward to copute the pole due to F the circuit below, because neither of its terals is rounded. EE05 Fall 007 Lecture, Slide 5 Prof. Liu, U Berkeley

6 Miller s Theore If A is the oltae a fro node to, then a float ipedance F can be conerted to two float ipedance F can be conerted to two rounded ipedances and : V V V V F F F A V V F F V V V V EE05 Fall 007 Lecture, Slide 6 Prof. Liu, U Berkeley F F F A V V

7 Miller Multiplication Apply Miller s theore, we can conert a float capacitance between the put and put nodes of p p p an aplifier to two rounded capacitances. The capacitance at the put node is larer than the l fl orial float capacitance. F F j F A j A A F F j EE05 Fall 007 Lecture, Slide 7 Prof. Liu, U Berkeley ( ) F F F A j A j A

8 Application of Miller s Theore λ 0 G ( ) F F EE05 Fall 007 Lecture, Slide 8 Prof. Liu, U Berkeley

9 MOSFET Intrsic apacitances The MOSFET has trsic capacitances which affect its perforance at hih frequencies:. ate oxide capacitance between the ate and channel,. oerlap and fr capacitances between the ate and the source/dra reions, and 3. source bulk & dra bulk junction capacitances ( SB & B ). EE05 Fall 007 Lecture, Slide 9 Prof. Liu, U Berkeley

10 Hih Frequency MOSFET Model The ate oxide capacitance can be decoposed to a capacitance between the ate and the source ( ) and a capacitance between the ate and the dra ( ). In saturation, (/3) ate, and 0. parallel with the source oerlap/fr capacitance GS parallel with the dra oerlap/fr capacitance EE05 Fall 007 Lecture, Slide 0 Prof. Liu, U Berkeley

11 Exaple S stae with MOSFET capacitances explicitly shown Siplified circuit for hih-frequency analysis EE05 Fall 007 Lecture, Slide Prof. Liu, U Berkeley

12 Transit Frequency The transit or cut off frequency, f T, is a easure of the trsic speed of a transistor, and is defed as the frequency where the current a falls to. onceptual set-up to easure f T V I I V I I T j T πf T GS EE05 Fall 007 Lecture, Slide Prof. Liu, U Berkeley

13 Sall Sinal Model for S Stae λ 0 EE05 Fall 007 Lecture, Slide 3 Prof. Liu, U Berkeley

14 Apply Miller s Theore p, p, The ( ( ) ) Note that p, > p, EE05 Fall 007 Lecture, Slide 4 Prof. Liu, U Berkeley

15 irect Analysis of S Stae irect analysis yields slihtly different pole locations and an extra zero: z p p XY ( ) ( ) XY The The ( ) ( ) XY The The XY ( ) The XY XY XY EE05 Fall 007 Lecture, Slide 5 Prof. Liu, U Berkeley

16 I/O Ipedances of S Stae λ 0 [ ( ) ] [ ] j GS j B EE05 Fall 007 Lecture, Slide 6 Prof. Liu, U Berkeley

17 G Stae: Pole Frequencies G stae with MOSFET capacitances shown λ 0 p, X X S GS X SB p, Y Y Y B EE05 Fall 007 Lecture, Slide 7 Prof. Liu, U Berkeley

18 A Analysis of Source Follower λ 0 The transfer function of a source follower can be obtaed by direct A analysis, siilarly as for the eitter follower (ref. Lecture 4, Slide 6) a ( j ) GS S j a ( ) ( j) b( j) b S GS SB SB GS SB EE05 Fall 007 Lecture, Slide 8 Prof. Liu, U Berkeley

19 Exaple a ( j ) GS ( j) b( j) a b S [ ( )( )] S GS SB EE05 Fall 007 Lecture, Slide 9 Prof. Liu, U Berkeley GS SB B B

20 Source Follower: Input apacitance S ecall that the oltae a of a source follower is A Follower stae with MOSFET capacitances shown λ 0 S XY can be decoposed to X and Y at the put and put nodes, respectiely: X ( A ) GS GS S GS S EE05 Fall 007 Lecture, Slide 0 Prof. Liu, U Berkeley

21 Exaple λ 0 ( GS r r ) O O EE05 Fall 007 Lecture, Slide Prof. Liu, U Berkeley

22 Source Follower: Output Ipedance λ 0 The put ipedance of a source follower can be obtaed by direct A analysis, siilarly as for the eitter follower (ref. Lecture 4, Slide 9) i X X j G GS j GS EE05 Fall 007 Lecture, Slide Prof. Liu, U Berkeley

23 Source Follower as Actie Inductor jggs j GS ASE : G < / ASE : G > / A follower is typically used to lower the dri ipedance, i.e. G is lare copared to /, so that the actie ductor characteristic i on the riht ihis usually obsered. EE05 Fall 007 Lecture, Slide 3 Prof. Liu, U Berkeley

24 Exaple λ 3 0 ( r r ) j O O GS 3 j GS 3 3 EE05 Fall 007 Lecture, Slide 4 Prof. Liu, U Berkeley

25 MOS ascode Stae For a cascode stae, Miller ultiplication is saller than the S stae. A X, XY Y X XY EE05 Fall 007 Lecture, Slide 5 Prof. Liu, U Berkeley

26 ascode Stae: Pole Frequencies ascode stae with MOSFET capacitances shown (Miller approxiation applied) 0 λ ( ), B p, Y p, GS G X p SB GS B EE05 Fall 007 Lecture, Slide 6 Prof. Liu, U Berkeley GS G

27 λ 0 ascode Stae: I/O Ipedances j j GS ( ) B EE05 Fall 007 Lecture, Slide 7 Prof. Liu, U Berkeley