Chapter 11 Frequency Response. EE105 - Spring 2007 Microelectronic Devices and Circuits. High Frequency Roll-off of Amplifier. Gain Roll-off Thru C L

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1 EE05 - Spr 2007 Microelectronic Devices and ircuits ecture 9 Frequency Response hapter Frequency Response. General onsiderations.2 Hih-Frequency Models of Transistors.3 Frequency Response of S Staes.4 Frequency Response of G Staes.5 Frequency Response of Followers.6 Frequency Response of ascode Stae.7 Frequency Response of Differential Pairs 2 Hih Frequency Roll-off of Aplifier Ga Roll-off Thru V R V s D As frequency of operation creases, the a of aplifier decreases. This chapter analyzes this proble. 3 The capacitive load,, is the culprit for a roll-off sce at hih frequency, it will steal away soe sal current and shunt it to round. 4

2 Frequency Response of the S Stae Exaple: Fiure of Merit V V R D R D FOM... VV T At low frequency, the capacitor is effectively open and the a is flat. As frequency creases, the capacitor tends to a short and the a starts to decrease. A special frequency is /(RD), where the a drops by 3dB. 5 This etric quantifies a circuit s a, bandwidth, and power dissipation. In the bipolar case, low teperature, supply, and load capacitance ark a superior fiure of erit. 6 Bode Plot Exaple: Bode Plot H() s A 0 s s + + z z2 s s + + p p2 When we hit a zero, zj, the Bode anitude rises with a slope of +20dB/dec. p R D When we hit a pole, pj, the Bode anitude falls with a slope of -20dB/dec The circuit only has one pole (no zero) at /(R D ), so the slope drops fro 0 to -20dB/dec as we pass p. 7 8

3 Pole Identification Exaple I Pole Identification Exaple II p p2 R S R D p R S p2 R D 9 0 ircuit with Float apacitor Miller s Theore The pole of a circuit is coputed by fd the effective resistance and capacitance fro a node to GROUND. The circuit above creates a proble sce neither teral of F is rounded. Z ZF ZF Z2 A / A v If A v is the a fro node to 2, then a float ipedance Z F can be converted to two rounded ipedances Z and Z 2. v 2

4 Miller Multiplication Exaple: Miller Theore With Miller s theore, we can separate the float capacitor. However, the put capacitor is larer than the orial float capacitor. We call this Miller ultiplication. R R ( + ) S D F R D + R D F 3 4 MOS Intrsic apacitances Gate Oxide apacitance Partition and Full Model For a MOS, there exist oxide capacitance fro ate to channel, junction capacitances fro source/dra to substrate, and overlap capacitance fro ate to source/dra. 5 The ate oxide capacitance is often partitioned between source and dra. In saturation, 2 ~ ate, and ~ 0. They are parallel with the overlap capacitance to for GS and GD. 6

5 Exaple: apacitance Identification Transit Frequency π f 2π ft 2 T π Transit frequency, f T, is defed as the frequency where the current a fro put to put drops to. GS 7 8 Unified Model for E and S Staes Unified Model Us Miller s Theore 9 20

6 Direct Analysis of E and S Staes Exaple: E and S Direct Analysis z p p2 XY ( + R ) XY RThev + RThev + R ( XY + ) ( + R ) XY RThev + RThev + R ( XY + ) R R( + + ) Direct analysis yields different pole locations and an extra zero. Thev XY XY p + ( ro ro 2) XY RS + RS + ( ro ro 2) ( XY + ) p2 ( ) ( ) R ( r r )( + + ) + ro ro 2 XY RS + RS + ro ro 2 ( XY + ) S O O2 XY XY 2 22 Z Input Ipedance of E and S Staes r π π + ( + R) μ s + ( + ) Z GS RD GD s 23 Frequency Response of G Stae r O px, RS + X GS SB py, R D Y + Y GD DB Siilar to a B stae, the put pole is on the order of f T, so rarely a speed bottleneck. X 24

7 Exaple: G Stae Pole Identification Eitter and Source Followers px, RS SB + GS ( ) py, 2 ( ) DB GD GS 2 DB2 25 The follow will discuss the frequency response of eitter and source followers us direct analysis. Eitter follower is treated first and source follower is derived easily by allow r π to o to fity. 26 Direct Analysis of Source Follower Stae Exaple: Source Follower V GS + s V as bs V GS + s V as bs R ( ) S a GDGS + GDSB + GSSB b R + S GD GD + SB 27 R [ ( )( )] S a GDGS GD GS SB GD2 DB b RSGD + GD SB GD2 DB2 28

8 Input apacitance of Eitter/Source Follower Exaple: Source Follower Input apacitance r O π μ + + R GS GD + + R + + r r ( ) GD GS O O Output Ipedance of Source Follower Active Inductor VX R S GSs+ I s+ X GS 3 The plot above shows the put ipedance of eitter and source followers. Sce a follower s priary duty is to lower the driv ipedance (R S >/ ), the active ductor characteristic on the riht is usually observed. 32

9 Exaple: Output Ipedance Frequency Response of ascode Stae r O ( ) V ro ro2 GS3s+ X I s+ X GS A vxy, x 2 2 For cascode staes, there are three poles and Miller ultiplication is saller than the E/S stae. XY 34 Poles of MOS ascode MOS ascode Exaple p, X R + + S GS GD 2 p, R ( + ) DB2 GD2 p, X R + + S GS GD 2 p, R ( + ) DB2 GD2 py, DB GS 2 GD 2 35 py, DB GS 2 GD GD3 DB3 2 36

10 I/O Ipedance of MOS ascode MOS Differential Pair Frequency Response Z GS+ + GD s 2 Z R s ( + ) GD2 DB2 37 Sce MOS differential pair can be analyzed us halfcircuit, its transfer function, I/O ipedances, locations of poles/zeros are the sae as that of the half circuit s. 38 Exaple: MOS Differential Pair px, py, p, RS[ GS + ( + / 3) GD] R 3 DB GS 3 GD 3 ( + ) DB3 GD3 39