HY:433 Σχεδίαση Αναλογικών/Μεικτών και Υψισυχνών Κυκλωμάτων

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Gertrude Harrison
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1 HY:433 Σχεδίαση Αναλογικών/Μεικτών και Υψισυχνών Κυκλωμάτων «Low Noie Aplifier» Φώτης Πλέσσας

2 F eceiver Antenna BPF LNA BPF Mixer BPF3 IF Ap Deodulator F front end LO

3 LNA De Conideration Noie perforance (covered Power tranfer (covered Ipedance atch (covered Power conuption (not covered Bandwidth (not covered Stability (not covered Learity (not covered

4 Low-Noie Aplifier Firt a tae receiver Aplify weak al Sificant ipact on noie perforance Doate put-referred noie of front end NFubequent NFfrontend NFLNA G Ipedance atch Efficient power tranfer Better noie perforance Stable circuit LNA

5 Noie Fiure Defition NF SN SN out S S out N N out A a function of device NF G N G N device ource G: Power a of the device N ource

6 NF of Cacaded Stae S /N S out /N out G, N, G i, N i, G K, N K, NF NF i NF K NF NF NF G NF3 G G... NFK G G...G K Overall NF doated by NF [] F. Frii, Noie Fiure of adio eceiver, Proc. IE, Vol. 3, pp.49-4, July 944.

7 Sall-Sal Model of MOSFET i i V V C C d r d i i C d C C V db V r r V i d C db : Gate reitance r i : Channel char reitance V

8 Siple Model of Noie MOSFET V V i I d k V ( f WLC Doant at low frequency Flicker noie Theral noie : epirical contant /3 for lon channel uch larer for hort channel PMOS ha le theral noie I ( f ox 4kT d f Input-ferred noie V i ( f 4kT k WLC ox f

9 Noie Approxiation Noie pectral denity /f noie Theral noie doant Theral noie Band of teret Frequency

10 Ipedance Match for LNA eitive teration Serie-hunt feedback Coon-ate connection Inductor deeneration

11 Power Tranfer and Ipedance Match V jx jx L I V L Ipedance atch V Pdel jx L jx Maxi available power P ax Load and ource ipedance conjuate pair eal part atched to 50 oh Power delivered to load P L L, X X L 0 4 L V V * L

12 eitive Teration i o 4kT/ 4kT/ I 4kT V I I I V V Noie fiure NF Introduced by put reitance I I T Sal attenuated

13 Suary - eitive Teration Noie perforance Low-frequency approxiation Input atched = I = 4 NF Broadband put atch Attenuate al Introduce noie due to I NF > 3 db (bet cae

14 Serie-Shunt Feedback F L Broadband atch V ( F ( L L ( a ( a a C F a L C C V F a V i out L out C ( ( ( ( Could be noiy a F a ( F C ( C F ( a a a V a

15 Coon-Gate Structure L 4kT 4kT L V V V 4kT L V V V 4kT

16 Input Ipedance of CG Structure Input ipedance Y = +C Input-ipedance atch Low frequency approxiation Direct without paive coponent / = =50 oh

17 Noie Perforance of CG Structure 4 ( ( ( 4 4 T device C C kt kt N G N G N NF ( ( eff C G G Sal attenuated

18 Suary CG Structure Noie perforance No extra reitive noie ource Independent of power conuption Ipedance atch Broadband put atch No paive coponent Power conuption =/50 Power tranfer Independent of power conuption

19 Inductor Deeneration Structure Z L L i out i C V V V V L V L V I I I L L ( L I I C L C ( I C ( I I L C V C L L Z

20 Input Match for ID Structure Z L L i out V L /C C V V Z = Z ( L L C L C IM{Z }=0 0 (L L C E{Z }= L C

21 Noie Factor of ID Structure Q NF ( C 0 ( C Q L L Increae power tranfer L /C = Decreae NF L /C = 0 Conflict between Power tranfer Noie perforance

22 Suary of ID Structure Noie perforance No reitive noie ource Lare L Ipedance atch Matched at carrier frequency Applicable to wideband application, S <-0dB Power tranfer Narrowband Increae with Power conuption Lare L

23 LNA De Exaple ( i o Aue No flicker noie V r o = fity C d = 0 V 4kT eaonable for appropriate bandwidth Effective tranconductance io Z Geff V Z V V 4kT

24 Power Ga Voltae put Current output * * ( ( ( T eff o o C C j C j C j Z Z G V V i i G

25 Noie Fiure Calculation Power output Device noie + put-duced noie Input-duced noie NF N device G N G N ( C ( / C 4kT 4kT ( C T C

Noie Perforance NF T Low frequency >> ~ >> /50 @ = 50 oh Power

26 Noie Perforance NF T Low frequency >> ~ >> = 50 oh Power conu CMOS technoloy /I D lower than other tech T lower than other tech

27 eview of Firt Exaple No ipedance atch Capacitive put ipedance Output not atched Power tranfer S =(-C /(+C S = /(+C, = = L Power conuption Hih power for NF Hih power for S

28 Cacode V V bia L L L M M V d V o Iolation to iprove hih frequency Sall rane at V d educed feedback effect of C d Iprove noie perforance L

29 Sall Sal Model L L V o L V o L C V V M V L V L L L

30 Folded Cacode Low upply voltae L d reduce or eliate effect of C d Good f T

31 LNA De Exaple ( V dd L vdd L b C b V out M 4 L d L out Output bia V bia M M 3 L b T V C b C L M L nd L Input bia Off-chip atch D. Shaeffer and T. Lee, A.5-V,.5-GHz CMOS low noie aplifier, IEEE J. Solid-State Circuit, vol. 3, pp , May 997.

32 D. Shaeffer and T. Lee, A.5-V,.5-GHz CMOS low noie aplifier, IEEE J. Solid-State Circuit, vol. 3, pp , May 997. LNA De Exaple ( Supply filter L vdd M 4 L d L out V bia M M 3 L b T V C b C L M L nd L Unwanted paraitic

33 Ερωτήσεις / Απορίες?

Introduction to CMOS RF Integrated Circuits Design

Introduction to CMOS RF Integrated Circuits Design Introduction to CMO F Interated Circuit Dein III. Low Noie Aplifier Introduction to CMO F Interated Circuit Dein Fall 0, Prof. JianJun Zhou III- Outline Fiure of erit Baic tructure Input and output atchin