Vgs Forms a Channel CS/EE MOS Capacitor. N-type Transistor

Transcription

1 V Form a hannel S/EE 670 MOS Tranitor Model Electrical Effect Propaation Delay N-type Tranitor MOS apacitor ate and body form MOS capacitor Operatin mode Accumulation V < Depletion Inverion (a) polyilicon ate ilicon dioxide inulator p-type body 0 < V < V t depletion reion + - D + (b) +V S Vd - i electron V > V t + - inverion reion depletion reion (c) Another utaway View Thank to National entral Univerity for Some imae Tranitor haracteritic Three conduction characteritic utoff eion No inverion layer in channel Id = 0 Nonaturated, or linear reion Weak inverion of the channel D Id depend on V and Vd Saturated reion Stron inverion of channel Id i independent of Vd +V S Vd A an aide, at very hih drain voltae: avalanche breakdown or punch throuh ate ha no control of Id + - Id

2 nmos utoff: V<Vt No channel I d = 0 V = 0 n+ n+ p-type body b V d d Baic N-Type MOS Tranitor ondition for the reion of operation utoff: If V < Vt, then Id i eentially 0 Vt i the Threhold Voltae Linear: If V>Vt and Vd < (V Vt) then Id depend on both V and Vd hannel become deeper a V oe up Saturated: If V>Vt and Vd > (V Vt) then Id i eentially contant (Saturated) D + Vd Id electron +V S - nmos Linear: V>Vt, mall Vd hannel form urrent flow from d to e - from to d I d increae with V d Similar to linear reitor V > V t V > V t n+ n+ p-type body b n+ n+ p-type body b V d = V d V d = 0 V > V d > V t d I d 0 < V d < V -V t Tranitor ain β i the MOS tranitor ain factor β = (με/t ox )(W/L) Proce-dependent Layout dependent μ = mobility of carrier Note that N-type i twice a ood a P-type ε = permittivity of ate inulator ε = 3.9 ε 0 for SiO (ε 0 = 8.85x0-4 F/cm) T ox = thickne of ate oxide Alo, ε/t ox = ox The oxide capacitance β = (μ ox )(W/L) = k (W/L) = KP(W/L) Increae W/L to increae ain nmos Saturation: Vd>V-Vt hannel pinche off onduction by drift becaue of poitive drain voltae Electron are injected into depletion reion I d independent of V d We ay that the current aturate Similar to current ource V > V t n+ n+ p-type body b V d < V t d I d V d > V -V t Example We will be uin a 0.6 μm proce for your project From AMI Semiconductor t ox = 00 Å.5 V = 5 μ = 350 cm / V*.5 V V t = 0.7 V = 4 V Plot I d v. V = 3 d 0.5 V = V = 0,,, 3, 4, 5 V 0 = Ue W/L = 4/ λ V d 4 W W W β = μox = ( 350) 0 μa/ V 8 L 00 0 = L L I d (ma)

3 Saturated Tranitor In the 0 < (V Vt) < Vd cae Id urrent i effectively contant hannel i pinched off and conduction i accomplihed by drift of carrier Voltae acro pinched off channel (I.e. Vd) i fixed at V Vt Thi i why you don t ue an N-type to pa! Hih voltae i deraded by Vt If Vt i.0v, 5v in one ide, 4.0v out the other 5v 4.0v S D 5v N-type Pa Tranitor 5v 4.0v 0.0v 5v Another option i a keeper tranitor fed back from the output Thi pull the internal node hih when the output i 0 But i diconnected when output i hih Make ure the ize i riht Aide: N-type Pa Tranitor A B ~S Out N-type Pa Tranitor In practice, they are ued fairly often, but be aware of what you re doin For example, read/write circuit in a eiter File * S If it weren t for the threhold drop, N-type pa tranitor (without the P-type tranmiion ate) would be nice -way Mux Example WE E0 E Write Data D0 D ead Data N-type Pa Tranitor 5v 4.0v 0.0v 5v One one hand, the deraded hih voltae from the pa tranitor will be retored by the inverter On the other hand, the P-device may not turn off completely reultin in extra power bein ued Back to the Saturated Tranitor What influence the contant Id in the aturated cae? hannel lenth hannel width Threhold voltae Vt Thickne of ate oxide Dielectric contant of ate oxide arrier mobility μ Velocity Saturation 3

4 Threhold Voltae: Vt The V voltae at which Id i eentially 0 Vt =.67v for nmo and -.9v for pmo in our proce Tiny Id i exponentially related to V, Vd Take 570/670 for ubthrehold circuit idea Vt i affected by ate conductor material ate inulator material ate inulator thickne hannel dopin Impuritie at Si/inulator interface Voltae between ource and ubtrate (Vb) Id urve nd Order Effect: Body Effect P-type Tranitor A econd order effect that raie Vt ecall that Vt i affected by Vb (voltae between ource and ubtrate) Normally thi i contant becaue of common ubtrate But, when tranitor are in erie, Vb (V Vubtrate) may be chaned Vt > Vt Vt Vt Vb = 0 Vb = 0 -V S Vd D + - i hole Baic D Equation for Id P-type Tranitor utoff eion D + V < Vt, Id = 0 Vd Id Linear eion 0 < Vd < (V Vt) +V S - Id = β[(v Vt)Vd Vd /] Note that thi i only linear if Vd / i very mall, I.e. Vd << V Vt Saturated eion 0 < (V Vt) < Vd Id = β[(v Vt) /] 4

5 P-type Tranitor Source i Vdd intead of ND V = (Vdd - Vin), Vd = (Vdd -Vout), Vt i neative utoff: (Vdd-Vin) < -Vt, Id=0 -V S Vd Linear eion D (Vdd-Vout) < (Vdd - Vin + Vt) Id = β[(vdd-vin+vt)(vdd-vout) (Vdd-Vout) /] Saturated eion ((Vdd - Vin) + Vt) < (Vdd - Vout) Id = β[(vdd -Vin + Vt) /] + - i nd Order Effect: Velocity Saturation With weak field, current increae linearly with lateral electric field At hiher field, carrier drift velocity roll off and aturate Due to carrier catterin eult i le current than you think! For a μ channel lenth, effect tart around 4v Vdd For 80nm, effect tart at 0.36v Vdd! Pa Tranitor kt nd Order Effect: Velocity Saturation V SS When the carrier reach their peed limit in ilicon hannel lenth have been caled o that vertical and horizontal EM field are lare and interact with each other V = 0 Vertical field ~ 5x0 6 V/cm n+ n+ p-type body b V d d Horiz field = ~0 5 V/cm Pa Tranitor kt nd Order Effect: Velocity Saturation V = -V tn V = V tp VDD -Vtn VDD-Vtn V - tn -V tn -V tn When the carrier reach their peed limit in ilicon Mean that relationhip between Id and V i cloer to linear than quadratic Alo the aturation point i maller than predicted For example, 80nm proce t order model =.3v eally i 0.6v V SS 5

6 nd Order Effect: Velocity Saturation nd Order Effect: Body Effect Thi i a baic difference between lonand hort-channel device The trenth of the horizontal EM field in a hort channel device caue the carrier to reach their velocity limit early Device aturate fater and deliver le current than the quadratic model predict nd Order Effect: Velocity Saturation onider two device with the ame W/L ratio in our proce (V=5v, Vdd=5v) 00/0 v 4.6/. They hould have the ame current Becaue of velocity aturation in the hortchannel device, it ha 47% le current! nd Order Effect: Body Effect onider an nmo tranitor in a 80nm proce Nominal Vt of 0.4v Body i tied to round How much doe the Vt increae if the ource i at.v intead of 0v? Becaue of the body effect, Vt increae by 0.8v to be 0.68v! nd Order Effect: Body Effect nd Order Effect A econd order effect that raie Vt ecall that Vt i affected by Vb (voltae between ource and ubtrate) Normally thi i contant becaue of common ubtrate But, when tranitor are in erie, Vb (V Vubtrate) may be chaned Vt > Vt Vt Vt Vb = 0 Vb = 0 6

7 nd Order Effect Inverter Switchin Point Inverter witchin point i determined by ratio of βn/βp If βn/βp =, then witchin point i Vdd/ If W/L of both N and P tranitor are equal Then βn/βp = μ n / μ p = electron mobility / hole mobility Thi ratio i uually between and 3 Mean ratio of W ptree /W ntree need to be between and 3 for βn/βp = For thi cla, we ll ue W ptree /W ntree = nd Order Effect Inverter Switchin Point nd Order Effect Inverter Operatin eion Linear Linear 7

8 ate Size Aume minimum inverter i Wp/Wn = / (L = Lmin, Wn = Wmin, Wp = Wn) Thi become a x inverter To drive larer capacitive load, you need more ain, more Id Increae width to et x inverter Wp/Wn i till /, but Wp and Wn are double the ize For mot ate, diminihin return after about 4x ize Inverter Noie Marin To maximize noie marin, elect loic level at: unity ain point of D tranfer characteritic V OH V OL V out 0 V tn V IL Unity ain Point Slope = - V V IH DD - V tp V in β p /β n > V in V out Inverter β atio Performance Etimation Firt we need to have a model for reitance and capacitance Delay are caued (to firt order) by delay charin and dicharin capaciter All thee layer on the chip have and aociated with them Motly thi i handled in the Spectre imulator But it ood to have an idea what oin on Inverter Noie Marin How much noie can a ate ee before it doen t work riht? Loical Hih Output ane Loical Low Output ane Output haracteritic Input haracteritic V OH NM H V IH Indeterminate V eion IL NM L V OL ND Loical Hih Input ane Loical Low Input ane eitance = (ρ/t)(l/w) = (L/W) ρ = reitivity of the material t = thickne = heet reitance in Ω/quare Typical value of Min Typ Max M M, M Poly Silicide 3 6 Diffuion Nwell k k 5k 8

9 apacitance Three main form: ate capacitance (ate of tranitor) Diffuion capacitance (drain reion) outin capacitance (metal, etc.) d D S b db b ubtrate = b + + d Approximated by = oxa ox = thin oxide cap A = area of ate Wire Delay Example = 0Ω/q = 4 x 0-4 pf/um L = mm K = 0.7 T = kl / T = (0.7) (0) (4 x 0-5 )(000) / delay =. n outin apacitance Firt order effect i layer->ubtrate Approximate uin parallel plate model = (ε/t)a ε = permittivity of inulator t = thickne of inulator A = area Frinin field increae effective area apacitance between layer become very complex! rotalk iue Wire/Buffer Delay Example Now plit into mm ement with a buffer T = x (0.7)(0)(4x0-5 )(000) )/+ Tbuf = 5.6n + Tbuf Aumin Tbuf i le than 5.6n (which it will be), the plit wire i a win Ditributed on Wire Wire look like ditributed delay Lon reitive wire can look like tranmiion line Inertin buffer can really help delay Tn = n(n+)/ T = kl / a the number of ement become lare K = contant (I.e. 0.7) = reitance per unit lenth = capacitance per unit lenth L = lenth of wire Another Example: lock 50pF clock load ditributed acro 0mm chip in um metal lock lenth = 0mm = 0.05Ω/q, = 50pF/0mm T = (0.7)(/)L = (6.5X0-7 )(0,000) = 7.5n 0mm 9

10 Different Ditribution Scheme Propaation Delay Put clock driver in the middle of the chip Widen clock line to 0um wire lock lenth = 0mm = 0.05Ω/q, = 50pF/0mm T = (0.7)(/)L = (0.3X0-7 )(0,000) = 0.n educe by a factor of 0, L by Increae 0mm a tiny bit um v 0um apacitance Dein uide Invertin Propaation Delay et a table of typical capacitance per unit quare for each layer apacitance to round apacitance to another layer Add them up See, for example, Table 4.8, 4.9 in your book Wire Lenth Dein uide Non-Invertin Delay How much wire can you ue in a conductin layer before the delay approache that of a unit inverter? Metal3 =,500u Metal =,000u Metal =,50u Silicide = 50u Poly = 50u Diffuion = 5u 0

11 Where to Meaure Delay? Proce orner When part are pecified, under what operatin condition? Temp: three rane ommercial: 0 to 70 Indutrial: -40 to 85 Military: -55 to 5 Vdd: Should vary ± 0% 4.5 to 5.5v for example Proce variation: Slow N Fat P Slow N Slow P Each tranitor type can be low or fat Fat N Fat P Fat N Slow P Example Non-Invertin ate What Ele Affect ate Delay? What Affect ate Delay? Inv_Tet Schematic Environment Increain Vdd decreae delay Decreain temperature decreae delay Fabrication effect, fat/low device Uually meaure delay for at leat three cae: Bet - hih Vdd, low temp, fat N, Fat P Wort - low Vdd, hih temp, low N, Slow P Typical - typ Vdd, room temp (5), typ N, typ P

12 loeup of Inv-Tet Note the ize I ued for thi example Delay Model Ue equivalent circuit for MOS tranitor Ideal witch + capacitance and ON reitance Unit nmos ha reitance, capacitance Unit pmos ha reitance, capacitance apacitance proportional to width eitance inverely proportional to width d d k /k k k k d k k k /k d k Analo Simulation Output Note different waveform for different ize of tranitor Value apacitance = = = d = ff/μm of ate width Value imilar acro many procee eitance 6 KΩ*μm in 0.6um proce Improve with horter channel lenth Unit tranitor May refer to minimum contacted device (4/ λ) Or maybe μm wide device Doen t matter a lon a you are conitent Effective eitance Shockley model have limited value Not accurate enouh for modern tranitor Too complicated for much hand analyi Simplification: treat tranitor a reitor eplace I d (V d, V ) with effective reitance I d = V d / averaed acro witchin of diital ate Too inaccurate to predict current at any iven time But ood enouh to predict delay A Inverter Delay Etimate Etimate the delay of a fanout-of- inverter Y

13 Inverter Delay Etimate What a Standard Load? Etimate the delay of a fanout-of- inverter A Y Y A Inverter Delay Etimate Etimate the delay of a fanout-of- inverter Y Y What About ate in Serie Baically we want every ate to have the delay of a tandard inverter Standard inverter tart with / P/N ratio ate in erie? Sum the conductance to et the erie conductance βn-eff = /( /β + /β + /β3) βn-eff = βn/3 Effect i like increain L by 3 ompenate by increain W by 3 A Inverter Delay Etimate Etimate the delay of a fanout-of- inverter Y d = 6 Y Power Diipation Three main contributor:. Static leakae current (P ). Dynamic hort-circuit current durin witchin (P c ) 3. Dynamic witchin current from charin and dicharin capacitor (P d ) Becomin a HUE problem a chip et bier, clock et fater, tranitor et leakier! Power typically et diipated a heat 3

14 Static Leakae Power Small tatic leakae current due to: evere bia diode leakae between diffuion and ubtrate (PN junction) Subthrehold conduction in the tranitor Leakae current can be decribed by the diode current equation I o = i (e qv/kt ) Etimate at 0.nA 0.5nA per device at room temperature Short-ircuit Diipation So, with hort-circuit current on every tranition of the output, interate under that current curve to et the total current It work out to be: Pc = B/(Vdd Vt) 3 (Trf / Tp) Aume that Tr = Tf, Vtn = -Vtp, and Bn = Bp Note that Pc depend on B, and on input waveform rie and fall time Static Leakae Power That the leakae current For tatic power diipation: P = SUM of (I X Vdd) for all n device For example, inverter at 5v leak about - nw in a.5u technoloy Not much but, it et MUH wore a feature ize hrink! Dynamic Diipation harin and dicharin all thoe capacitor! By far the laret component of power diipation Pd = L Vdd f Watch out for lare capacitive node that witch at hih frequency Like clock Short-ircuit Diipation When a tatic ate witche, both N and P device are on for a hort amount of time Thu, current flow durin that witchin time Total Power Thee are pretty rouh etimate It hard to be more precie without AD tool upport It all depend on frequency, averae witchin activity, number of device, etc. There are proram out there that can help But, even a rouh etimate can be a valuable dein uide P total = P + P c + P d 4