f max = GHz I ave PartAData 2 :=

Transcription

1 NTU 6342 / EE 24 Homework #3 SOLUTIONS Problem #: Delay time: t p_fo4_2 :=.424n t p_fo4_ := 2.2n Simulation value: T min := 2 t p_fo4_2 T max := 2 t p_fo4_ T min =.848 n T max = 4.24 n f max := T min Part a: f min := T max f max =.7 GHz f min = MHz PartAData:= READPRN ("inverter_delay_fo4_2.txt" PuleWidth PartAData := Vdd :=.V I ave PartAData 2 := A Frequency:= 2 PuleWidth P ave := ( I ave V dd 3 Power [uw] Clock Period [n] Average Power

2 25 2 Current [ua] Clock Period [n] Average Current 3 Power [uw] Frequency [MHz] Average Power

3 Part b: PartBData:= READPRN ("inverter_delay_fo4_2_vdd.txt" SupplyVoltage PartBData := V tp PartBData 4 := Propagation Delay [n] Supply Voltage [V] Interpolating the delay-vdd curve to get the needed Vdd for a given delay: V dd_opt := for n.. x linterp n V t PuleWidth p SupplyVoltage n,, V V dd_opt =.63 V PuleWidth = n

4 VddOptData:= READPRN ("inverter_delay_fo4_2_vdd_opt.txt" I ave_opt VddOptData 4 := A t p_opt VddOptData 7 := freq opt := P ave_opt :=.. 2 t p_opt x I n ave_optn V dd_optn x Power [uw] 3 2 We can ee from the graph that reducing the upply voltage reduce the peed to the amount required. Thi reult in a quadratic reduction in power a oppoed to a linear decreae with only frequency caling Frequency [MHz] Scaled Vdd Vdd =. V 3 Current [ua] Clock Period [n] Scaled Vdd Vdd =. V

5 Part c: BodyBiaData:= READPRN ("inverter_delay_fo4_2_vbb.txt" BodyBia BodyBiaData 3 := V BodyDelay:= BodyBiaData Propagation Delay [n] 5 We can ee that the inverter propagation delay decreae a the threhold voltage i increaed (revere body bia and increae when the threhold voltage i decreaed (forward body bia. From thi graph, we can determine the required body bia needed to achive the deired propagation delay Body Bia [V] V body_opt := for n.. x linterp BodyDelay PuleWidth BodyBia n, n, V V V body_opt =.7 V PuleWidth = n

6 VbbOptData:= READPRN ("inverter_delay_fo4_2_vbb_opt.txt" I ave_vbb_opt VbbOptData 4 := A t p_vbb_opt VbbOptData 7 := V dd =. V freq opt_vbb := P ave_opt_vbb :=.. 2 t p_vbb_opt x I n ave_vbb_optn V dd 3 x Power [uw] 2 We can ee from thi curve that we can increae the threhold voltage by varying the ubtrate bia, lowing down the tranitor. The increaed threhold voltage alo reult in decreaed leakage current, thu reducing the overall power Frequency [MHz] Scaled Vdd Vdd =. V Scaled Body Bia (contant Vdd 25 2 Current [ua] Clock Period [n] Scaled Vdd Vdd =. V Scaled Body Bia (contant Vdd

7 Part d: Forward biaing the tranitor bulk: VddVbbNegData := VddVbbNegData := VddVbbNegData := 2 VddVbbNegData := 3 VddVbbNegData := 4 VddVbbNegData := 5 VddVbbNegData := 6 READPRN ("inverter_delay_fo4_2_vdd_vbb_neg.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg2.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg3.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg4.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg5.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg6.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg7.txt" Delay db_neg := for x x n n.. 4 ( VddVbbNegData n 5 V dd_db_neg:= VddVbbNegData V ( V bb_db_neg := V

8 Note that by forward biaing the bulk of the tranitor, the threhold voltage i reduced, increaing drive current and therefore peed. We can ue thi additional lack to further reduce the upply voltage, and conequently the power. Delay [n] Supply Voltage [V] Vbb = V Vbb =.5 V (forward bia Vbb =.3 V (forward bia Vbb =.45 V (forward bia Vbb =.6 V (forward bia

9 Finding the correponding Vdd and Vbb pair for a given operating frequency: V dd_body_opt ( delay := for n.. 4 x linterp n V Delay db_negn V dd_db_neg delay,, V.. Uing thi data, we can then imulate the inverter chain and find the optimal Vdd-Vbb pair for each frequency point that will reult in the lowet power. Supply Voltage [V] Body Bia (forward bia [V] f = 278 MHz f = MHz f = 45 MHz f = 7 MHz f = 8 MHz f = 85 MHz f = 74 MHz f = 66 MHz f = 6 MHz f = 54 MHz

10 VddVbbNegOptData := VddVbbNegOptData := VddVbbNegOptData := 2 VddVbbNegOptData := 3 VddVbbNegOptData := 4 VddVbbNegOptData := 5 VddVbbNegOptData := 6 VddVbbNegOptData := 7 VddVbbNegOptData := 8 VddVbbNegOptData := READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt2.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt3.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt4.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt5.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt6.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt7.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt8.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt.txt" READPRN ("inverter_delay_fo4_2_vdd_vbb_neg_opt.txt" V upply := for x n n.. ( VddVbbNegOptData n V ubtrate := for x n n.. ( VddVbbNegOptData n 2 V V I ave_inv2 :=.. x VddVbbNegOptData n ( n 4 A t delay :=.. x VddVbbNegOptData n ( n I ave_nbulk :=.. x VddVbbNegOptData n ( n 5 A I ave_pbulk :=.. x VddVbbNegOptData n ( n 6 A P upply :=.. x V n upplyn I ave_inv2n x ( P nbulk :=.. x V n ubtraten I ave_nbulkn x P pbulk := P total :=.. x P n upplyn + P nbulkn + P pbulkn x.. x V n upplyn V ubtraten x (( I ave_pbulkn (

11 . 4 Note that a the ubtrate i forward biaed, we can reduce the upply voltage. We expect the ubtrate current to increae with forward bia.. 3 However, a een from the plot, the power tart to increae a the S/D junction i biaed in the forward active region. Total Power [uw] Thi can be attributed to the fact that the ubtrate current i tart to dominate the overall power. Thu we ee that the minimum power occur when the bulk i forward-biaed at around.3 volt. Thi buy enough timing lack to reduce the upply voltage but till drawing a mall enough current through the S/D junction Body Bia (forward bia [V] f = 278 MHz f = MHz f = 45 MHz f = 7 MHz f = 8 MHz f = 85 MHz f = 74 MHz f = 66 MHz f = 6 MHz f = 54 MHz

12 From thee graph, we can ee the turn-on voltage of the S/D junction: N-Bia Power [nw] P-Bia Power [nw] Body Bia (forward bia [V] f = 278 MHz f = MHz f = 45 MHz f = 7 MHz f = 8 MHz f = 85 MHz f = 74 MHz f = 66 MHz f = 6 MHz f = 54 MHz Body Bia (forward bia [V] f = 278 MHz f = MHz f = 45 MHz f = 7 MHz f = 8 MHz f = 85 MHz f = 74 MHz f = 66 MHz f = 6 MHz f = 54 MHz

13 Problem #2: Part a: The two circuit tyle compared in the paper are the tandard CMOS inverter circuit and the Charge Recovery (or Adiabatic logic. The delay and energy model for each can be expreed a: C V dd C V dd D CMOS = = = R CMOS C I k ( V dd V th 2 E CMOS = 2 C V dd 2 π D CR = + R CR C E CR = ω d 2 C V2 e π α ω d α = R CR 2 L SInce both energy expreion are dependent on the quare of the upply voltage (or in the cae of CR, a fraction of the upply voltage, we can ue voltage caling to quadratically reduce the energy. Part b: Without conidering witching power, CMOS logic diipate le energy until the voltage i caled down to V. The point where CR tart to conume le energy ha a X reduction in frequency and a 5X reduction in power. With witching power conidered, CMOS logic now diipate le energy over a wider range. The voltage croover point i reduced from V to voltage cloe to the tranitor threhold voltage. Thu, with witching power conidered, CR tart to conume le energy when the power i reduced 25X at a frequency of X the peak. Part c: For low power deign with increaed computation requirement uch a portable phone, computer, PDA, and the like, CMOS logic will be the better choice. However, for ultra-low power, very low performance requirement, uch a watche, imple enor without much computational requirement, medical and biological implant, and the like, CR logic might be the logic yle of choice.

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