Parameter Analysis of the Low-Power MCML

Transcription

1 20 International Conference on Circuit, Sytem an Simulation IPCSIT ol.7 (20) (20) IACSIT Pre, Singapore Parameter Analyi of the Low-Power MCML Dan Zhang, Wei Wu 2 an Yifei Wang 3 College of Science, Shanghai Unierity Abtract. By analyzing certain parameter, we hae realize that the power conumption of Mo Current Moe Logic (MCML) circuit can be reuce by controlling threhol oltage of correponing tube. We hae alo tuie mutual relation between power iipation, oltage gain, banwith, an elay. By comparing the tructure of one-leel MCML circuit with that of two-leel MCML circuit, we notice change in parameter when builing more leel. Keywor: Mo Current Moe Logic, MCML, inerter, D-latch, low power eign. Introuction In realm of eigning portable eice [] like cell phone an implantable meical eice that require many year of continuou operation, the application of the circuit with low power conumption ha become more ignificant. A logic tyle that i wiely ue in high-pee circuit, optical communication ytem an high-performance microproceor [2], i MOS Current Moe Logic (MCML). The MCML circuit i promiing in both reuction power iipation an proiing an analog frienly working enironment. 2. Power conumption an parameter analyi of the inerter The latch circuit in Fig. i a typical example of a MCML circuit which i alo calle the inerter. 2.. Power conumption Fig. The inerter circuit Power conumption in MCML i expree a P = V (), thu, it can be ecreae by either reucing the upply oltage V or the bia current I. Decreaing I will egrae the performance of MCML [3], while reucing V i limite by the minimum upply oltage neee for the proper operation of the circuit. Hence, a metho to reuce V in MCML without affecting the proper working conition of the whole circuit i neee. In the inerter circuit which i hown in Fig., M houl operate in the aturation region, thu, the minimum upply oltage ( V min ) can be expree a Vmin = V + Vg (2), where V i rain-ource oltage for M an Vg i the gate-ource oltage for M, repectiely. In general, the rain-ource oltage V i V = Vg Vth (3), where V th i the threhol oltage. In the aturation region, V g can be expree a 6

2 Vg = / K + Vth (4), where K = 0.5 μ CoxW / L. Subtituting in Eq.(3), V can be written a V = / K (5). Inerting into Eq.(2) an auming that K = nk ( n > ), for the ifferential pair: V ( min = K V I ) V + K + th = K + K + th = K ( V V ) ( + ) + V 2 g th K th K K g th K th = ( V V )( + ) + V = ( + n)( V V ) + V g th th where V th an V th are threhol oltage of M an M, repectiely. It i obiouly that V min can be reuce in orer to purue low-power conumption by making V th at a high alue an ecreaing V th. By tuying the expreion that V =Φ + 2 Φ + Q / C, where th m f ep ox Φ f = ( kt / q)ln( Nub / ni), Qep = 4qε i Φ f Nub, [4] an Φm i the ifference of work function between gate an ubtrate, one can thereby control the threhol oltage by changing oping rate of the ubtrate an thickne of the oxie layer uner the gate. If Vth change to Vth Δ Vth while V th change to Vth +Δ Vth, the total power conumption will be reuce by [( + n) Δ Vth +Δ Vth ], auming that M alway work in the aturation region Voltage gain (A) uner low an high frequency For an inerter MCML circuit that i working in a LOW frequency, A i expree a: A = gmrd = 2 μncox( W ) RD (6) L Ue PSPICE to exam the tenency of the oltage gain when I rie. The imulation i bae on SPICE LEVEL moel in Table. an the reult are hown in Table 2. NMOS LEVEL= VTO=0.7 GAMMA=0.45 PHI=0.9 NSUB=9E+4 LD=0.08E-6 UO=350 LAMBDA=0. TOX=9E-9 PB=0.9 CJ=0.56E-3 CJSW=0.35E- MJ=0.45 MJSW=0.2 CGDO=0.4E-9 JS=.0E-8 V V i i2 I V0 V02 A Power Table. Simulation Moel Table 2. PSPICE Simulation reult Obiouly, a rawback occur here. The greater the bia current I, the greater the oltage gain, howeer, from Eq.(), the greater the power conumption. Accoring to Eq.(6), increaing the with to length ratio will rie the oltage gain while acrifice more chip olume. For an inerter MCML circuit that i working in a HIGH frequency, the equialent half-circuit containing capacity i hown in Fig 2. Fig 2. Equialent half-circuit of the inerter 7

3 Uing Miller Theorem, the output capacity equal Cb + ( + ) Cg Cb + Cg where C b an C g are gmr the rain-ubtrate an the gate-rain capacity of M, repectiely. Then the oltage gain uner high frequency i expree a: A = gm( R ) jωc jωc, which ecreae a frequency rie (ω i much greater when working uner high frequency) Banwith b g The pole of the inerter i: ω = / R ( C + C ) (7) g b The ban will be wier (ω to be greater) if R g b are being reuce, but at the ame time the oltage gain A will ecreae Circuit elay Fig 3. The mall ignal circuit tructure of the inerter C.4C g Cr CL = 0.69 RD( ) (8) I AI I I where C r i the capacity parallel with the loa reitance R D an C L i the output capacity. Apparently, one can reuce an at the ame time increae oltage gain by riing I, while uch approach will acrifice more power for the inerter. 3. Power conumption an parameter analyi of two-leel MCML circuit There i an extenion of the methoology [5], which i calle the two-leel MCML circuit or D-latch, for the inerter tuie aboe. Fig 4. how the topology of uch circuit. 3.. Minimum upply oltage Fig 4. The two-leel MCML circuit 8

4 Similar to the upply oltage of the inerter circuit ( V min ), the minimum V DD for the two-leel MCML circuit can be expree a V min 2 (2 + n)( Vg Vth ) + Vth, which i one oerrie oltage greater than V min, thu, accoring to Eq.(), the two-leel MCML circuit conume more power than the inerter Low frequency oltage gain of two-leel MCML A = R g g (/ g + g ) D m m4 m m4 Auming that the tranconuctance of all tube are the ame, then A gmrd /2, which i maller than Eq.(6). The oltage gain of the two-leel MCML comparing with that of the inerter i hown in Fig Banwith Fig 5. The output wae of inerter an D-latch The total output capacity ( C tot ) i greater by aing one more tructure leel, thu, the pole expree a ω = / RC, i maller than Eq.(7), which mean the two-leel MCML ha a relatiely narrower ban. tot 3.4. Circuit elay Fig 6. Equialent half-circuit of the two-leel MCML Crain Crain + Cource Cr + CL 0.69 RI D {[ +.4 ] + }, A Crain = ( Cb + Cg ) + ( Cb + Cg )ource = Cb + ( Cg3 + Cb3) + ( Cg4 + Cb4) By comparing C rain ource with C g Where Concluion, it i conpicuouly that the elay i greater than Eq.(8) Thi work preente a methoology to lower the power conumption of the inerter circuit an analyze parameter a oltage gain, banwith, an elay of the circuit. Moreoer, by comparing to the two-leel MCML, one can fin that inerter ha a greater oltage gain, wier ban, an maller elay than the twoleel MCML circuit, auming that all tube are the ame, leaing to eigning MCML circuit with more leel a tougher job. 5. Reference [] Giueppe De Vita, Giueppe Iannaccone, Ultra-low -power temperature compenate oltage reference generator, Microelectronic Journal 37, p (2006). [2] Haan, Mohab Ani, Mohame Elmary, MOS Current Moe Logic; Deign, Optimization, an Variability, IEEE, p (2004). 9

5 [3] S. Bruma, Impact of on-chip proce ariation on MCML performance, Proceeing of the IEEE International Sytem-on-Chip Conference (SOCC 03), p (2003). [4] B. Razai, Deign of Analog CMOS Integrate Deice, McGraw Hill, New York, NY, (200). [5] Giueppe Caruo, Aleio Macchiarella, Optimum Deign of Two-Leel MCML Gate, IEEE, p.4-44 (2008). 0