Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design

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1 Compact Moeling of Graphene Barristor for Digital Inteate Circuit Design Zhou Zhao, Xinlu Chen, Ashok Srivastava, Lu Peng Division of Electrical an Computer Engineering Louisiana State University Baton Rouge, LA 70803, U.S.A. {zzhao13, xchen67, eesriv, Saraju. P. Mohanty Department of Computer Science an Engineering University of North Texas Denton, TX 76207, U.S.A. Abstract Graphene barristor, in which a Schottky barrier forme between aphene layer an silicon layer can wien the bangap with the control of gate voltage, is a promising metho to enhance on/off current ratio in igital circuit esign. In this work, a theoretical stuy is presente base on analog behavior moeling in SPICE. We have evelope a compact evice moel to evaluate the performance of aphene barristors. The evice simulation results show the on/off current ratio nearly 10 5 uner the voltage variation which aees closely with the reporte experimental results. A complementary inverter is esigne using the evelope moel to prove the feasibility of aphene barristor for use in future igital VLSI esign. The energy per switching is between 1.1~0.52fJ uner voltage variation. Fig. 1. Cross section view of aphene barrister. Keywors Graphene Barristor, Schottky Barrier, Transistor Moeling, IC Design I. INTRODUCTION Graphene-base evices have been recently propose an can work uner a very low power supply with much higher mobility than the wiely use silicon evices [1, 2, 3]. However, the property of zero bangap is a major problem blocking aphene to be inteate in current igital IC esign [4]. The suitability of a transistor use for igital circuits epens on that the transistor channel to be semiconucting so as to provie a large on/off current ratio. Both aphene nanoribbon an bilayer aphene have emonstrate to be semiconucting with a esirable bangap for transistor switching action. Graphene nanoribbon FET an bilayer aphene FET have been reporte [5, 6]. The aphene nanoribbon FET can be use for the igital circuit esign for low-power operation [7]. But the current fabrication process cannot support complex nanoribbon embee into chips an the ege effect can largely influence the practical performance. Bilayer aphene FET nees high voltage to get the require bangap which is not suitable for energy saving esign. A new aphene base evice, aphene barristor, has been introuce recently [8, 9]. The ifference between a aphene barristor an a normal aphene transistor is that a Schottky barrier, forme by the aphene layer an the silicon layer, is ae to generate barrier height between the gate noe an the source noe. This barrier height can largely wien the bangap (a) (b) (c) Fig. 2. Energy ban iaam of aphene/n-type silicon uner a) zero bias, b) forwar bias an c) reverse bias.

2 Fig. 3. Equivalent circuit of a aphene barrister. so that the evice can be use for igital logic. Design an analysis of aphene barrier-base inteate circuits require a physical evice moel which can be use either in SPICE or Verilog-A for simulations. In this work, we have use analog behavior moeling in SPICE to moel the aphene barristor an its circuits. The analog behavior moeling metho can ynamically ajust each current an voltage in the evice accoring to the variation of voltage. At the same time the parasite passive evices can be change ue to voltage/current variation an at the same time increase the simulation accuracy. Using analog behavior moeling, we have evelope an accurate evice moel incluing source block an passive evices to simulate aphene barristor. We have emonstrate the feasibility of use of aphene barristers through the esign of a complementary inverter. The paper is organize as follows. Section II presents physics behin the moeling of aphene barrister, the equivalent circuit moel an analog behavior moeling in SPICE. Section III presents esign of a complementary inverter base on aphene barrister followe by the conclusion in Section IV. II. MODELING GRAPHENE BARRISTOR The cross section view of a aphene barristor is shown in Fig. 1. It can be seen that there is a aphene-silicon Schottky barrier forme aroun the source noe an the gate noe. The stuy regaring the aphene-silicon junction has been reporte in [10]. For the analysis, it is efine that forwar bias an reverse bias are positive voltage applie in aphene layer an silicon layer, respectively. Taking the aphene/n-type silicon junction as an example, the energy ban iaams uner thermal equilibrium, forwar bias an reverse bias conitions are shown in Fig. 2. When forwar bias is applie as shown in Fig. 2 (b), the built-in potential will be reuce so that electrons are easy to go from silicon to aphene generating a forwar bias current. A very ifferent phenomenon compare to the traitional metalsilicon Schottky junction is that the Fermi level of aphene in this case will be move own ue to negative charges in aphene which nee to mirror positive charges in silicon. While in the case of reverse bias, the tenency of aphene Fermi level Fig. 4. Graphene capacitor variation versus gate voltage for ifferent rain-source voltages. Current Density, A/m 2 Current Density, A/m (a) Vg=0.4V Vg=0.6V Vg=0.8V Vg=1V Vg=1V, reporte in [5] Vs, V (b) Fig. 5. The simulate current: a) gate voltage epenence an b) rain-source voltage epenence. an built-in potential are opposite. The essence of the aphene/silicon junction is formation of a ioe with two noes. To achieve a three-noe evice neee for a igital circuit, a rain noe is ae to exten the ioe to a FET-like structure. The potential of the rain can control the whole

3 Resistance, Ohms/m 2 Fig. 6. Output resistance variation versus gate voltage. current going through the evice. When the potential of the rain is the same as of source, from the view of the evice, the net current will be zero since there is no voltage ifference between the source an the rain. Thus, with the gate control an rainsource control the aphene barristor can perform like a typical FET with three noes that can be use in igital circuit esign. The following section mathematically analyzes the I-V characteristics an parasite passive evices existing in aphene barristor. We make few practical assumptions base on the imensional restriction of aphene barrister which are as follows. 1) The aphene layer in a aphene barristor is not as narrow as in a aphene nanoribbon, we can use ballistic irecte moments for 3D carriers to analyze the current transport an ignore ege effects. 2) The aphene layer of the barristor is over the silicon substrate, we can ignore the surface states an other effects like crystal efects, an traps between the interface an substrate. 3) The effective length of aphene layer forming the Schottky junction is very short. We o not take scattering effect into consieration. 4) The current through the evice is in horizontal irection. Thus, the image force existe in vertical irection can be neglecte. Accoring to Fig. 1, the equivalent circuit of aphene barristor can be shown as in Fig. 3. Once each parameter in equivalent circuit is etermine, the moel in SPICE using analog behavior moeling can be evelope. For the calculation of capacitor in a aphene barristor, first start with the charge balance consiering metal, silicon, an oxie silicon [11] which can be expresse by the Eq. (1) as follows: Qm + Q + Qsi = 0 ε m( Vg V ) Qm = tox 2 2q kt qv qv Q = ζ 1 ζ 1 π v f kt kt 2 Φ qφ qφ ni qφ qφ Qsi = 2ε siktn + exp + 1 exp 1 2 Φ kt kt N kt kt where ε m an ε si are the permittivity constants of metal contact an silicon, respectively. t ox is the thickness of silicon ioxie, V g is the external gate voltage, V is the potential of aphene surface, q is the unit electron charge, k is the Boltzmann constant, T is the temperature (efault temperature is 300K for the following analysis), is the reuce plank constant, Φ is the potential of silicon surface, v f is the Fermi velocity in aphene, n i is the intrinsic carrier concentration in silicon, N is the oping concentration in silicon. ζ 1 is the Fermi-Dirac inteal of orer one. To obtain the value of capacitor, it is obvious that in above equations both Φ an V nee to be obtaine. The function Φ with these two parameters can be expresse as follows: Φ = Φ bo V + V s (1) 3 kt 1 Nh + ζ (2) 1/ 2 3/ 2 q 2( 2.16πmokT ) Where Φ bo is the barrier height for the evice uner zero bias, an is set to 0.5V in the case of aphene/silicon junction. h is the Planck s Constant, an m o is the unit electron mass. An 1 ζ is the inverse Fermi-Dirac inteal with orer of / 2 The next step is to transfer charge value to a capacitance value. The silicon oxie capacitor is contribute by the voltage ifference between the gate an aphene layer. The aphene capacitor is contribute by the potential of the aphene layer. Using above analysis with t ox=1nm, T=300K, an N =10 22 m -3, the aphene capacitor epenence on the gate voltage for four rain-source voltages is shown in Fig. 4. We can see that aphene capacitor is below 0.25pF/µm 2 with voltage variations. The aphene capacitor is proportional to the rain-source voltage, meaning that when rain-source voltage increases, the control ability for logic switch will be stronger from the perspective of circuit esign. Another capacitor, silicon ioxie capacitor also exists in the silicon oxie layer, which epens upon the gate voltage. In the analysis regaring capacitance, we can get potentials of the aphene surface an the silicon layer, which are neee to calculate the current. The original current ensity function can be expresse as follows [11]: * 2 qφ b qv s, (3) J = A T exp exp 1 exp kt kt where A * is the effective Richarson constant. For Φ b, the barrier height, it can be expresse by the following: Φ = Φ V. (4) b bo

4 Fig. 7. Moeling of a aphene barristor. Thus, the current ensity can be shown as follows: ( Φ ) q V * 2 bo qv s J = A T exp 1 exp (5) kt kt To verify the current analysis, first we use the gate voltage as the variable uner fixe rain-source voltage to calculate the current ensity. Then take the rain-source voltage as a variable uner the fixe gate voltage to simulate the current ensity. Both results are shown in Fig. 5, which are in aeement to the reporte results in [8] from the quantitative view. It can be seen that the ratio of switch-on current to switch-off current is close to 10 5, which is a practical value to use with aphene barristor base igital circuit esign. The output resistor between the rain an the source can be obtaine by taking a erivative of current function with respect to rain-source voltage. The simulate result is shown in Fig. 6. We observe from Fig. 6 that the output resistance of aphene barristor is not sensitive to the rain-source voltage. This fact is ue to the moulation by the potential of the silicon layer an the potential of the aphene layer. The resistance of the substrate can be calculate by [12]: R 2t sub sub =, (6) qμen Acont where t sub is the thickness of substrate, μ e is the electron mobility in silicon substrate, an A cont is the effective contact area between silicon substrate an aphene layer contributing current channel. The resistance of metal/aphene contact, which connects the rain, source, an gate noes also contributes to the performance of circuit operation. We extract the experimental result from [13] for the case of monolayer aphene contacting with metal. The contact resistance is set to 800Ω for our moeling. It can be seen that I-V characteristics presente in Fig. 5 aees with the experimental results of [8] which proves the valiity of the current transport moel of aphene barrister presente in this work. The evice moeling in SPICE can be one by a controlle source (e.g. VCCS, CCCS, VCVS, an CCVS), a look-up table, an fixe passive evices. However, the controlle source provie by SPICE only can implement simple linear calculations to get approximate voltage/current results. But emerging novel evices require much non-linear analysis to accurately narrate evice characteristic. The look-up table is an efficient metho to moel a novel evice. This metho can also reuce simulation time since there is only rea an write request. Going to circuit esign, imperfect logic transferring ue to clock skew an inaequate charge/ischarge will cause large pulse currents or voltages. In this case, if an overlarge voltage or current is not store in the look-up table, the simulation will fail ue to lack of enough information to be searche. The unwante pulse current or voltage is also ranomly generate accoring to circuit structures. Thus, it is very ifficult to calculate an store all neee information in the look-up table ealing with various circuits. Analog behavior moeling [14, 15] is a moule in SPICE, which can implement complex non-linear calculations regaring both voltage an current. The etaile calculation function inclues aition, subtraction, multiplication, ivision, calculus, absolute function an exponential function, all of which can well satisfy our moeling nees accoring to the previous analysis. With the help of these calculation functions, analog behavior moeling can solve non-linear equations. Besies, analog behavior moeling has a limitation block which can restrict input signal in a reasonable range to avoi unwante signal processing reucing the simulation accuracy. For the transmission between voltage an current to achieve the voltagecontrol evice an capacitor, analog behavior moeling has an evaluate block which can transfer voltage to current uner selfefine principles. Analog behavior moeling has the function of parameter statement, which means that all constants can be state globally, an use for the entire moeling. This function largely improves the esign efficiency. For the moeling of aphene barristor with our previous analysis, we can fin both potentials of the aphene surface an the silicon surface, two important variables which are relate to aphene capacitance, silicon oxie capacitance, output resistance, an evice current. When these two parameters are solve, with the efinition of other constants an the input voltage such as gate voltage an rain-source voltage, require aphene capacitance, silicon oxie capacitance, output resistance, the evice current can be solve smoothly. For other parameters serving for moeling, substrate resistance an aphene/metal resistance, these can be easily calculate by constants without variables. In our moeling, the imension of aphene layer is set to be the same as in [9]. The length is 20nm an with is 1µm. The

5 tox (nm) Lch (nm) V (V) Table I. Comparison between aphene barristor an emerging technologies. FinFET Bilayer This work By the Year Graphene FET By the Supplie Voltage V 0.8V 0.6V N/A Ion/Ioff Cg (ff) Eswitch (fj) Power issipation, nw Fig. 8. Graphene barrister base inverter performance: power issipation epenence on frequency. thickness of the silicon oxie an the substrate are 1nm an 0.3mm, respectively. The moeling flow of aphene barristor is shown in Figure 7 an escribe as follows: 1) State all constants which will be use for the mathematical analysis. 2) Calculate both potentials of silicon surface an aphene surface. These two parameters can be solve with a set of Eq. (1) an Eq. (2). 3) Using state constants an both potentials of silicon surface an aphene surface calculate in Step 2, calculate aphene capacitance, silicon oxie capacitance, an evice current. Two kins of capacitors are outputte by the variable capacitor. The current of aphene barristor is outputte by GEVALUATE which is a block an can transfer voltage to current by a self-efine equation in SPICE. At the same time, using constants, calculate substrate resistance an aphene/metal contact resistance. 4) Combine all calculate parameters in Step 3 following the equivalent circuit moel in Fig. 3. Using moeling flow in Fig. 7, we can moel both n-type an p-type aphene barristors with ifferent oping categories. III. GRAPHENE BARRISTOR BASED CIRCUIT DESIGN The analyses of the current means that both forwar bias an reverse bias conitions have a current to achieve a igital logic. We notice that the current uner reverse bias is smaller than uner the forwar bias. An the on/off current ratio uner the forwar bias is larger than uner the reverse bias, which means that using aphene barristor uner the forwar bias is more suitable for the igital logic esign. We use both forwar bias an reverse bias operation to esign a circuit fining that even though the power issipate in reverse bias conition is smaller than in the forwar bias conition, the signal inteity in reverse bias conition is much worse than in the forwar bias conition. Thus, we choose the way of forwar biasing to buil the circuit. With this metho, the logic esign using aphene barristors is same as in traitional CMOS an FinFET, which has both pullown n-type tree an pull-up p-type tree combine to obtain a complementary topology. For low power esign, in the simulation, we set 1V, 0.8V, an 0.6V as three supply voltages cases to stuy. To evaluate the performance of igital circuit using the propose moel of aphene barristor, we esigne a complementary inverter for power issipation versus frequency epenence. Figure 8 shows the simulation results. From the simulation results, we can see that in most of the cases gate logic uner 1V supply issipates more power than uner the reuce supply voltages. To evaluate the feasibility of the propose evice, we compare few parameters, on/off current ratio, gate capacitance an switching energy with other emerging evices [16, 17, 18]. The results are summarize in Table I. From Table I, we can observe that the barristor uses relatively large channel length an I on/i off ratio is

6 within the acceptable range; an from the view of power issipation an gate capacitance, aphene barristor is a competitive caniate which can be use for the igital circuit esign. IV. CONCLUSION In this work, a compact an simple current transport moel of a aphene barristor is presente. Using analog behavior moeling, an accurate SPICE moel is propose. The propose moel can be ajuste ynamically by the voltage variation for accurate simulations. The simulation results show that aphene barristor can be use for low power igital circuit esign. The future work woul focus on the scaling of evice imension an improvement in I on/i off ratio. ACKNOWLEDGMENT Part of work is supporte uner NSF Grant No REFERENCES [1] A. K. Geim an K. S. Novoselov, The rise of aphene, Nature materials, vol. 6, pp , Mar [2] S. P. Mohanty, Nanoelectronic Mixe-Signal System Design, McGraw-Hill, 2015, ISBN-10: , ISBN- 13: [3] S. Joshi, S. P. Mohanty, an E. Kougianos, Simscape base Ultra-Fast Design Exploration: Graphene- Nanoelectronic Circuit Case Stuies, Springer Analog Inteate Circuits an Signal Processing Journal, Volume 87, Issue 3, June 2016, pp [4] F. Schwierz, Graphene transistors, Nature Nanotechnology, vol. 5, pp , May [5] M. Chouhury et al., Technology exploration for aphene nanoribbon FETs, Proc. of 45th Design Automation Conference (DAC), 2008, pp [6] J. B. Oostinga, H. B. Heersche, X. Liu, A. F. Morpurgo, an L. M. K. Vanersypen, Gate-inuce insulating state in bilayer aphene evices, Nature Materials, vol. 7, pp , Dec [7] S. Joshi, S. P. Mohanty, E. Kougianos, an V. P. Yanambaka, Graphene Nanoribbon Fiel Effect Transistor base Ultra-Low Energy SRAM Design, in Proceeings of the 2n IEEE International Symposium on Nanoelectronic an Information Systems (inis), 2016, pp [8] H. Yang et al., Graphene barristor, a trioe evice with a gate-controlle Schottky barrier, Science, vol. 336, pp , Jun [9] J. Noh, K. E. Chang, C. H. Shim, S. Kim, an B. H. Lee, Performance prospect of aphene barristor with high onoff ratio (~10 7 ), Proc. of Silicon Nanoelectronics Workshop (SNW), 2014, pp [10] D. Sinha an J. U. Lee, Ieal aphene/silicon Schottky junction ioes, Nano Letters, vol. 14, pp , Jul [11] G. Giusi an I. Giuseppe Iannaccone, Moeling of nanoscale evices with carriers obeying a three-imensional ensity of states, Journal of Applie Physics, vol. 113, Apr [12] B. L. Sharma, Metal-Semiconuctor Schottky Barrier Junctions an Their Applications, NY: Springer Science & Business Meia, [13] A. Venugopal, L. Colombo, an E. M. Vogel, Contact resistance in few an multilayer aphene evices, Applie Physics Letters, vol. 96, Jan [14] PSPICE User Guie, 2000, [online]:, Last Accesse on 03/12/2017. [15] PSPICE Reference Guie, 2000, [online]:, Last Accesse on 03/12/2017. [16] ITRS for Semiconuctor, 2013, [online]: hnology/itrs/2013/, Last Accesse on 03/12/2017. [17] ITRS for Semiconuctor, 2015, [online]: hnology/itrs/2015/0_2015%20itrs%202.0%20executive %20Report%20(1).pf, Last Accesse on 03/12/2017. [18] T. K. Agarwal et al., Bilayer aphene tunneling FET for sub-0.2 V igital CMOS logic applications, IEEE Electron Device Letters, vol. 35, pp , Dec