ELECTRONIC SYSTEMS. Real operational amplifiers. Electronic Systems - C2 28/04/ DDC Storey 1
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1 Politecnico i Torino ICT school Lesson C2 Real Op mp parameters an moel ELECTRONIC SYSTEMS C OPERTIONL MPLIFIERS C.2 Real Op mp an examples» Real Op mp parameters an moel» Static an ynamic parameters» Gain Banwith, Slew Rate» Op mp ata sheet analysis Static parameters Differential gain, output saturation, Input currents, offset voltage Dynamic parameters Gain Banwith, Slew Rate Op mp ata sheet analysis Maximum ratings Electrical characteristics 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC Real operational amplifiers 5.5 Ieal Op mp So far we have assume the use of ieal opamps these have v =, R i = an R o = 0 Real components o not have these ieal characteristics (though in many cases they approximate to them) In this section we will look at the characteristics of typical evices perhaps the most wiely use general purpose opamp is the 741 ctually I, I = 0 Ol, ifficult to get; will use TI081/2/4 Output: V O = V = (V 1 V 2 ) Gain Input currents = 0 From» V = V O / = 0» Input ifferential current (input mesh) = 0 V 1 V 2 I V I V O = V 12.3 Storey, Electronics: Systems pproach, 3 r Eition Pearson Eucation Limite /04/ ElnSysC DDC 2009 DDC 2006 Storey 1
2 ctual Op mp Moels for real Op mp Differential gain high but not infinite; ifferential input voltage V small but not 0 Input currents I, I small but not 0 Nonlinear, frequency epenent transfer function = f(v, V, ω, ) Limite banwith ( ecreases for high ω) Influence of external parameters temperature, power supply, New moels to take into account these effects Real Op mp How to get real Op mp moels: Remove the ieal assumptions one at a time:» Infinite gain / ifferential input voltage V = 0» Input currents I, I = 0» Fully balance inputs / no offset» Unlimite banwith» Linearity Define specific moels, which take into account each parameter How to evaluate behavior of real Op mp Evaluate the effects of each parameter using specific moel the various effects (linear system assumption) 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC Finite ifferential gain Feeback gain an loop gain T Rni: Gain with feeback, consiering the value of V = V U Rni 1 β = R R 2 VU 1 VI = V VE = βvu = VU β VU = = = V 1 1 I β β 1 β V I V V V E R1 V U Loop gain β T Rni Rni VU 1 1 = = V 1 I β 1 β 1 1 = β 1 1 T Check: When, also T ; Rni Ri The real feeback gain becomes the ieal feeback gain V I V V V E R1 V U 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 2
3 Ieal an actual gain Effect of in feeback circuits Gain error: 1 Ri = β 1 1 Rni = β 1 1 T 1 1 εg = = T β Ri 1 ( 1...) T Gain with real Op mp: lways lower than ieal gain Gain error proportional to 1/(β), or 1/T V I V V R1 V U Gain error proportional with 1/(β) = 1/T V V amplifiers: Output resistance Ru low but not 0: less than Ro (Op mp)» By a factor (β1) β = T (usually high) Input resistance Ri large, but not infinite: higher than Ri» By a factor (β1) β = T (usually high) Errors are small if T = β is large β is a esign spec (Ieal gain: 1/β)» with high feeback gain (small β) errors increase epens on the Op mp» the esigner can select (Op mp parameter). 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC Effects of feeback on the Gain 5.7 Offset error negative feeback reuces gain from to /(1 B) in return for this loss of gain we get consistency, provie that the openloop gain is much greater than the closeloop gain (that is, >> 1/B) using negative feeback, stanar cookbook circuits can be use greatly simplifying the esign these can be analyze without a etaile knowlege of the opamp itself Storey, Electronics: Systems pproach, 3 r Eition Pearson Eucation Limite 2006 Ieal Op mp: = 0 when Vi = 0 Real: Op mp 0 when Vi = 0» Internal an external mismatches OFFSET error V I = 0 How to evaluate an keep uner control? 28/04/ ElnSysC DDC V U Vi R DDC 2006 Storey 3
4 Input an output offset Moel for Voff Output offset: off Value of when Vi = 0 Can be moele as input unbalance (Vioff) off = Vioff x Gain Input offset: Vioff Value of Vi which makes = 0 Goal: minimum off Two techniques» Reuce causes» Correct effects» Both: reice causes an correct effects off Vioff Vi The output offset can be moele by a Voff unbalance in the input loop When Vi = Voff, Ve = 0; = 0. Voff is the voltage to apply at Vi to get = 0. (Voff) = Voff (R1)/ V I V OFF Op mp moel with input offset voltage V Ieal Op mp V E R1 V U 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC Input currents Total output offset The currents at input pins are small but not zero They contribute to the total output offset voltage How to limit the error cause by input currents? Op mps with MOSFET input have very low input V I currents negligible effects Select R3 = R1//. R3 oes not influence the transfer function V = I x R: keep value of resistors low (for actual value, check Op mp specs) R1 R3 I I V U Output offset comes from two main sources Input offset voltage (Voff)» Effect minimize by proper selection of Op mp Input currents (Iin)» Effect minimize by resistor balance an keeping low R values Voff an Iin are inepenent sources To get total output offset, a absolute values of the two terms off = (Voff) (Iin) 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 4
5 Offset recovery voi offset compensation! The offset can be correcte by aing a (low) constant voltage at the input Some integrate Op mps provie specific pins for offset recovery 15V R5 R3 15V R1 V 1 V 2 O R4 V U Ouput offset compensation Must be trimme for each circuit expensive! Cannot compensate offset variations (thermal rift, aging, power supply changes, ). Funamental rule Trimming single units is expensive an only a partial solution Better to select evices with low Voff an Ib (accoring to application nees), even if more expensive Minimize the effects of offset by applying proper esign criteria The avoitrimming rule applies to all parameters 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC Ieal Transcharacteristic Transcharacteristic with = /V (V) (V) V (V) Differential gain infinite (very high) V (µv) High gain 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 5
6 Transcharacteristic : an saturation, saturation, an offset Val Val Output swing V (µv) Linear range for input signals (fraction of mv) Val Val Output swing The (Vi) characteristic oes not cross (0,0): Offset Voff(out) Voff(in) V (µv) 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC ctual transcharacteristic Loa riving Output swing Val Voff(in) V Combine effects of soft saturation an offset V I Ro I I Increasing the output current Iu reuces the output voltage swing Rc Current flowing in the loa causes a voltage rop on Op mp internal output resistance Ro. The output swing is reuce. Val Val Val Vi 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 6
7 Example of saturation Effect of saturation on V Input an output signals for an inverting amplifier Triangular input Linear output s the Op mp output () enters saturation, the input ifferential voltage V is no longer 0 The inverting input noe is no longer virtual groun In linearity (=Vi)» V = 0 V Output with saturation Saturation occurs here In saturation ( Val)» V 0 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC Input an output ranges Lesson C2 MX Vout V L DMC MX Vin VC MX Input Output Device is amage Not feasible The evice oes not work, but is not amage OK OK OK Real Op mp parameters an moel Static parameters Differential gain, output saturation, Input currents, offset voltage Dynamic parameters Gain Banwith, Slew Rate MIN DMC MIN V L VC MIN OK OK Device is Not feasible amage Op mp ata sheet analysis Maximum ratings Electrical characteristics 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 7
8 Op mp frequency response Gain Banwith prouct The open loop response ( ) has a single pole P at F1; from here rops 20 B/ec, with 0 B crossing at F3. P position epens on actual value of. The only known parameter is gain banwith BG (GBP, GBW) (B) P 1 F F3 ω (ra/s) The Gain Banwith Prouct GBP is the same for all points in the unity slope (20B/ec) segment (B) 1 GBP = 1*F1 GBP = 2*F2 GBP = 3*F3 For 3 = 1 (0 B) 30 2 GBP = F3 F1 10 F F3 ω (ra/s) 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC High frequency effects Frequency response with feeback The open loop gain ecreases towars high frequencies, therefore β ecreases an becomes complex:» Errors increase (eviations from ieal behavior)» Rx become Zx(ω)» Gain error increases (value) For amplifiers with input: voltage current» ieal O ( ) Ri Ri = 0» real O ( finite) Zi ecreases Zi increases For amplifiers with output: voltage current» ieal O ( ) Ru = 0 Ru» real O ( finite) Zu increases Zu ecreases The iagram shows the open loop gain an 1/β Single pole at F1 Drop 20 B/ec Gain Bwth Prouct = F2 1/β not relate with frequency (resistive β) 1/β (B) F F2 ω (ra/s) 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 8
9 Banwith with feeback Ban limit with feeback Rni 1 1 = β 1 1 β for ω << ω a β >> 1 1/β << 1 rni = 1/β 1 β Same behavior as for ieal Op. mp. with feeback 1/β (B) ω << ω a 1 10 ω a ω (ra/s) Rni 1 1 = β 1 1 β for ω >> ω a β << 1 1 << 1/β rni = Same behavior as for open loop Op. mp. 1/β (B) ω a ω (ra/s) zona ω >> ω a 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 3 b response Summary of frequency response Rni = = β 1 1 β When ω = ω a β = j ω a complex β, Gain rops 3 B 1 2 1/β (B) B 1 10 ω a 3B ω (ra/s) Response with feeback If β >> 1 feeback behavior (1/β) prevails» r = 1/β if β << 1 open loop behavior () prevails» r = Banwith with feeback epens from (ω)» Gain Banwith Prouct (GBP)» (0) an pole position β» Constant for resistive feeback network zona ω << ω a zona ω >> ω a 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 9
10 Effects of feeback on opamp circuits (cont.) Effects of feeback on frequency response as the gain is reuce the banwith is increase gain banwith constant since gain is reuce by (1 B) banwith is increase by (1 B) for a 741, gain banwith 10 6 if gain = 1000 BW 1000 Hz if gain = 100 BW 10,000 Hz Slew rate The slope of the output voltage is limite because of Voltage saturation insie the amplifier Saturation of capacitance charge/ischarge currents. Slew Rate parameter: SR = V/ T With squarewave signals SR = V/Tf(o Tr) With sine signals SRmax = max(v/t) = max(ω V cosωt) = ωv Tf V V Storey, Electronics: Systems pproach, 3 r Eition Pearson Eucation Limite /04/ ElnSysC DDC Slew rate istortion Other parameters When SRsignal > SRamplier Dynamic saturation: upper boun for V/t The output becomes a triangular wave Max SR of the Op. mp. Example for increasing ω Example for increasing V Max SR of the signal t Input noise Maximum output current Limite by nonlinear protection circuitry Maximum power issipation Quiescent power consumption Input resistances: ifferential (Ri), common moe (Ric) Very high; to be consiere for special applications Frequency compensation feeback circuit can become instable Most current Op. mp are intrinsically stable 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 10
11 Real Op mp parameters an moel Static parameters Differential gain, output saturation, Input currents, offset voltage Dynamic parameters Gain Banwith, Slew Rate Op mp ata sheet analysis Maximum ratings Electrical characteristics Lesson C2 Integrate Op mp Operational amplifiers (opamps) are among the most wiely use builing blocks in electronics they are integrate circuits (ICs) often DIL or SMT /04/ ElnSysC DDC Storey, Electronics: Systems pproach, 3 r Eition Pearson Eucation Limite 2006 Data sheet structure Data sheet 1 The ata sheet escribes external characteristics of the evice (can be measure from external pins) Main features [Summary of main features] Packaging an pinout bsolute maximum ratings Electrical characteristics [Internal structure] [Use examples] [Measurement techniques of relevant parameters] 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 11
12 Data sheet 2 Packaging an pinout [package type an size, ] The same evice is available in ifferent packages» ualinline, flat pack, pingri, ballgri,...» Plastic, ceramic, metal case, The package influences electrical an mechanical features» Parasitic L an C (epen mainly from size)» Max temperature, vibration,. Pinout Specifies functional pins physical pin Can be ifferent for each package Reference tab pin 1 Numbering in counterclockwise irection (top view) 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC Data sheet 3 Maximum ratings Operating limits (bsolute maximum ratings) tensioni massime i alimentazione tensioni massime applicabili ai pieini (in e out) massima temperatura i funzionamento massima potenza issipabile massime correnti i ingresso. If crosse permanent amages may occur Insulator perforation Wire blowing 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 12
13 Data sheet 4 Electrical Parameters Electrical characteristics Normal operating conitions Specify measurement conitions» Power supply voltage,» temperature,».. Electrical parameters» Voff, Ioff, Ib,, SR,,...» Tables, graphs, Represent normal operating conitions, where the evice complies with specs 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC Typical, minimum, maximum value Example of value istribution Manufacturers cannot guarantee the exact value of electric parameters Passive components (R, C, L, ): tolerances 10% 0,01% ctive evices (Op mp, MOS..): tolerances 50% 100% R, nominal value 10 kω, tolerance 5% 9,5 kω 10 kω 10,1 kω 10,5 kω The esign must take into account these changes Nominal value (label): esign target Typical: mean value, most likely... Min/max values: guarantee limits ll evices comply with these limits Devices with outofrange parameters cannot be sol (o not respect specs). Number of evices Value of the parameter iscare min Nominal typic al iscare max Tolerance range 28/04/ ElnSysC DDC 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 13
14 Lesson C2: final test Which parameters influence the gain error? n amplifier has a voltage gain = 10 an Vioff i 3 mv. Which is the value of off (cause by Vioff)? How can we minimize the errors cause by input currents? Why offset compensation an trimming circuits shoul be avoie? Which output voltage range can we get from an Op mp with 5V an 10V power supplies? How to evaluate frequency limitations of a feeback amplifier? resistor with label value 1 kω, toler. 3% has an actual value 998 Ω. Is the evice within specs? What if the value is 1,04 kω? 28/04/ ElnSysC DDC 2009 DDC 2006 Storey 14
EMBSY - B1 16/09/ /09/ EMBSY - B DDC. Output: V O = A d V d = A d (V 1 -V 2 ) 16/09/ EMBSY - B DDC 5.3.
EMBY B 6/09/0 Politecnico i Torino CT chool B p mp an feeback circuits Electronics for Embee ystems B p mp an feeback circuits» eal operational amplifier» Negative feeback circuits» Moels of real p mp»
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