28.1 Parametric Yield Estimation Considering Leakage Variability

Transcription

1 8.1 Parametric Yiel Estimation Consiering Leakage Variability Rajeev R. Rao, Aniruh Devgan*, Davi Blaauw, Dennis Sylvester University of Michigan, Ann Arbor, MI, *IBM Corporation, Austin, TX {rrrao, blaauw, Abstract Leakage current has become a stringent constraint in moern processor esigns in aition to traitional constraints on frequency. Since leakage current exhibits a strong inverse correlation with circuit elay, effective parametric yiel preiction must consier the epenence of leakage current on frequency. In this paper, we present a new chip-level statistical metho to estimate the total leakage current in the presence of within-ie an ie-to-ie variability. We evelop a close-form expression for total chip leakage that moels the epenence of the leakage current istribution on a number of process parameters. The moel is base on the concept of scaling factors to capture the effects of within-ie variability. Using this moel, we then present an integrate approach to accurately estimate the yiel loss when both frequency an power limits are impose on a esign. Our metho emonstrates the importance of consiering both these limiters in calculating the yiel of a lot. Categories an Subject Descriptors B.8. [Performance an Reliability]: Performance analysis General Terms Performance, reliability, measurement Keywors Leakage, variability, parametric yiel 1 Introuction Continue scaling of evice imensions combine with shrinking threshol voltages has enable esigners to prouce integrate circuits (ICs that contain hunres of millions of evices. However, this has also resulte in an exponential rise of IC power issipation. This increase is substantially ue to leakage which is emerging as a significant portion of the total power consumption. It is estimate that the subthreshol leakage power will account for 50% of the total power for portable applications evelope for the 65nm technology noe [1]. In future technologies, aggressive scaling of the oxie thickness will lea to significant gate oxie tunneling current, further aggravating the leakage problem. Across successive technology generations, subthreshol leakage increases by about 5X [] while gate leakage can increase by as much as 30X. At the same time, the increase presence of parameter variability in moern esigns has accentuate the nee to consier the impact of statistical leakage current variations uring the esign process. For ±10% variation in the effective channel length of a transistor, there can be up to a 3X ifference in the amount of subthreshol leakage current [3]. Gate leakage current exhibits an even greater sensitivity to process variations, showing a 15X ifference in current for a 10% variation in Permission to make igital or har copies of all or part of this work for personal or classroom use is grante without fee provie that copies are not mae or istribute for profit or commercial avantage an that copies bear this notice an the full citation on the first page. To copy otherwise, or republish, to post on servers or to reistribute to lists, requires prior specific permission an/or a fee. DAC 004, June 7-11, 004, San Diego, California, USA Copyright 004 ACM /04/ $5.00. Figure 1. Leakage an frequency variations (Source: Intel oxie thickness in a 100nm BPTM process technology [4]. Hence, consierable variability in chip level leakage current is expecte an measure variations as high as 0X have been reporte in the literature [5]. In current esigns, the yiel of a lot is typically calculate by characterizing the chips accoring to their operating frequency. The subsets of ies that o not meet the require performance constraint are rejecte, making this aspect of the esign process very important from a commercial point of view. However, it has been observe [5] that among the goo chips that meet the performance constraint, a substantial fraction issipate very large amounts of leakage power an thus are unsuitable for commercial usage. This is ue to the inverse correlation between circuit elay an leakage current. Devices with channel lengths smaller than the nominal value have reuce elay while at the same time incurring vastly increase leakage current resulting in higher leakage issipation for chips with high operating frequencies. This inverse correlation is illustrate in Figure 1, which shows the istribution of chip performance an leakage base on silicon measurements over a large number of samples of a high-en processor esign [5]. Both the mean an variance of the leakage istribution increase significantly for chips with higher frequencies. This tren is particularly troubling since it substantially reuces the yiel of esigns that are both performance an leakage constraine. Hence, there is a nee for accurate leakage yiel preiction methos that moel this epenency. Several statistical methos have been suggeste to estimate the full chip leakage current. In [6], the authors consier within-ie threshol voltage variability to estimate the full chip subthreshol leakage current. A compact current moel is use in [7] to estimate the total leakage current. In [8], the authors present analytical equations to moel subthreshol leakage as a function of the channel length of the transistor. A moment-base approximation approach is use to estimate the mean an variance of leakage current in [9] an [3]. However, none of these methos provie exact mathematical equations to express the chip leakage an furthermore, they o not consier the epenence of leakage on frequency. In this paper we evelop a complete stochastic moel for leakage current that inclues the effects from multiple sources of variability an captures the epenence of the leakage current istribution on operating frequency. We consier the contribution from both inter- an intra-ie process variations an moel total leakage as consisting of both subthreshol an gate oxie tunneling leakage. The within-ie 44

2 component of variability is moele using a scaling factor. We erive a close-form expression for the total leakage as a function of all relevant process parameters. We also present an analytical equation to quantify the yiel loss when a power limit is impose. This metho preclues the nee to use circuit simulation to characterize the leakage current of a chip an enables the esigner to buget for yiel loss before the chip is sent to prouction. The propose analytical expression is then compare with Monte-Carlo simulation using SPICE simulation of a large circuit block to emonstrate its accuracy. Finally, we construct yiel curves to accurately estimate the number of chips that satisfy both power an frequency constraints. The remainer of this paper is organize as follows. In Section, we present the moel for full chip total leakage. The moels for subthreshol an gate leakages are presente separately. In Section 3 we erive analytical equations to escribe the yiel preiction of a lot base on our leakage moel. In Section 4 we present results an in Section 5 we conclue the paper. Full Chip Leakage Moel In this section we present an analytical moel to etermine the total leakage current of a chip. We moel the leakage current as a function of ifferent process parameters. First, we note that the total leakage is a sum of the subthreshol an gate leakages: I tot = I sub + I gate (EQ 1 Recently, it has been note that other types of leakage current, such as Ban-to-Ban Tunneling (BTBT, may become prominent in future process technologies [7]. Although we o not moel this type of leakage in this paper, our analysis can be easily extene to inclue aitional leakage components. In the subsequent sections, we moel each type of leakage separately. We express both types of leakage current as a prouct of the nominal value an a multiplicative function that represents the eviation from the nominal ue to process variability. I leakage = I nominal f( P, (EQ where P is the process parameter that affects the leakage current I leakage. In general, f is a non-linear function. Since estimation methos base irectly on BSIM moels [10] are often overly complex, we use carefully chosen empirical equations in our analysis to provie both efficiency an accuracy. We further ecompose parameter P into two components: P = P global + P local, (EQ 3 where P global moels the global (ie-to-ie or inter-ie process variations while P local represents the local (within-ie or intra-ie process variations. In a typical manufacturing process, both P global an P local are generally moele as inepenent normal ranom variables making P also a normal ranom variable. Since we are only ealing with the eviation from nominal, P is a zero mean variable. If P is the effective channel length, then P local is the so-calle Across Chip Length Variations (ACLV. For simplicity of notation, we let P global =P g an P local =P l..1 Subthreshol Leakage Subthreshol leakage current (I sub refers to the source-to-rain current when the transistor has been turne off. As is well known, I sub has an exponential relationship with the threshol voltage V th of the evice as shown below in EQ4. f( V th I sub I nominal = (EQ 4 For the 0.13um technology noe, even small variations in V th can result in leakage numbers that iffer by 5-10X from the nominal value. Threshol voltage is a technology-epenent variable that must be expresse as a function of a number of parameters. The stanar BSIM4 escription [10] expresses V th as a function of several process parameters incluing effective channel length (L eff, oping concentration (N sub, an oxie thickness (T ox. Among these parameters, the variation in L eff has the greatest impact as note in [8]. A secon orer, but still significant portion of the variation in V th occurs ue to fluctuations in oping concentration that result in ifferent values of the flat ban voltage V fb for ifferent transistors on the chip [3]. Finally, oxie thickness is a fairly well-controlle process parameter an oes not influence subthreshol leakage significantly. In our approach we moel L eff an V th,nsub as inepenent normal ranom variables since they are inepenent physical parameters. The variation in V th is expresse as an algebraic sum of two terms: 1. f( L eff = the variation in effective channel length of the evice. f( V th, Nsub = the variation in V th ue to oping concentration f( V th f( L eff + f( V th, Nsub = (EQ 5 While there is a minor epenency between these functions, the amount of error introuce as a result of this inepenence assumption was foun to be negligible. Previously, leakage was moele as a single exponential function of the effective channel length [6], but as the authors show in [8] a polynomial exponential moel is much more accurate in capturing the epenence of leakage on effective channel length. Hence, we use a quaratic exponential moel to express f( L eff. Οn the other han, for f( V th,nsub we etermine from circuit simulations that a linear exponential moel is sufficient. For simplicity of notation, let L eff =L an V th,nsub =V. Using this we can rewrite EQ4: f( L eff ( L + c L c 3 = f( V c th, Nsub = ---- V 1 L + c L + c 3 V I sub = I sub, nom (EQ 6 Here,, c, c 3, are fitting parameters an I sub,nom is the subthreshol leakage of the evice in the absence of any variability. The negative sign in the exponent is inicative of the fact that transistors with shorter channel lengths an lower threshol voltage prouce higher leakage current. Using EQ3 we ecompose L an V into local (L l, V l an global (, components an we write the I sub equation as follows: + c +c 3 L l + λ L l +λ 3 V l λ 1 I sub = I sub, nom (EQ 7 I sub is the subthreshol leakage of a single evice with unit with. The mapping from c i to λ i (for i=1,,3 is given by λ i =ψc i where ψ = 1 ( 1 + c. To calculate the total subthreshol leakage for a chip we nee to a the leakages evice-by-evice, consiering that each evice has unique ranom variables L l an V l, while sharing the same ranom variables an with all other evices. We first focus on the variability in 443

3 local process parameters L l an V l, assuming that an are fixe values. EQ7 suggests the well-known fact that the subthreshol leakage istribution of a single transistor has a lognormal istribution. The total subthreshol leakage is then a sum of all these iniviual epenent lognormals an if the number of lognormals is large enough, the variance of their sum approaches zero. Consequently, we use the Central Limit Theorem [11] to approximate the istribution of this sum of lognormals by a single number - the mean of the istribution. Moern CMOS esigns contain millions of evices that are istribute over a relatively large area on the chip. Thus, we can substitute the sum of leakages over all evices with the mean value of I sub over the complete range of L l. This mean value is a simple scaling factor that escribes the relation between I sub an L l. Local variations are often spatially correlate, meaning that evice that are posititione close together have positive correlation. However, as long as there are sufficient inepenent regions on a ie (as is typically the case the Central Limit Theorem can be applie. We use a similar metho to calculate the scaling factor for the local variability of each process parameter. To calculate the scaling factor, we nee to fin an exact expression for the expecte value (mean of I sub by consiering it as a function of the two (inepenent ranom variables (V l, L l. We write a ouble integral to calculate the mean: EI [ sub ] = gl ( l PDF( L l L l L + g c gl ( l = I sub, nom c gv ( l = e gv ( l PDF( V l V l L + l λ L l λ 1 λ 3 V l λ 1 (EQ 8 In this equation, the terms containing an are constant for a given chip. The above integrals can be solve in close-form an result in the expressions given in EQ1 an EQ3 of the Appenix. We obtain I sub E[I sub ] = S L S V I Lg,Vg where S L, S V are scale factors introuce ue to local variability in L an V. I Lg, Vg correspons to the subthreshol leakage as a function of global variations. I sub EI [ sub ] = S L S V I Lg, Vg λ S L = σ λ Ll 1 σ Ll λ 3 σvl λ 1 S V = e + c I Lg, Vg = I sub, nom e λ 1 + 4σ Ll λ1 λ c e (EQ 9 EQ9 provies the average value of subthreshol leakage for a unit with evice. To compute the total chip subthreshol leakage, we nee to perform a weighte sum of the leakages of all evices by consiering the evice withs to be the weights. For complex gates (transistor stacks, registers, a scale factor (k moel [6] is use to preict the effect of the total evice with. I csub, S L S V ( W k I Lg, Vg = (EQ 10 Here the term ( W k I Lg, Vg represents the chip level subthreshol leakage as a function of the global process parameters (,.. Gate Leakage When the oxie thickness of a evice is reuce there is an increase in the amount of carriers that can tunnel through the gate oxie. This phenomenon leas to the presence of gate leakage current (I gate between the gate an substrate as well as the gate an channel. I gate is linearly epenent on the area of the evice an has a highly exponential relationship with the oxie thickness (T ox. Since the variation in T ox has by far the greatest impact on gate leakage, we moel I gate as: f( T ox I gate I nominal = (EQ 11 From circuit simulations, we foun that it is sufficient to express f( T ox as a simple linear function. A suitable value for a single parameter β 1 efficiently captures the highly exponential relationship. Let T ox =T an using EQ3, we again ecompose T into global (T g an local (T l components. f( T ox T = β 1 ( T g β 1 ( T l β 1 I gate = I gate, nom e e (EQ 1 I gate is the gate leakage current of a single evice with unit with. I gate,nom is the nominal gate leakage an both T g an T l are zero mean ranom variables. We see that the relationship between I gate an T l is similar to the single exponential relationship between I sub an V l. Similar to S V, we compute the scale factor S T ue to T l : I gate EI [ gate ] = S T I Tg σ β Tl 1 S T = e ( T g β 1 I Tg = I gate, nom (EQ 13 Base on the withs of the evices, the chip level gate leakage can be calculate in a similar manner as the subthreshol leakage:.3 Total Leakage I cgate, S T ( W I Tg = (EQ 14 The total leakage is the sum of the subthreshol an gate leakage currents of all the evices. In EQ10 an EQ14 we note that I Lg,Vg an I Tg are share by all the evices on the chip. Hence we can write the equation for total chip leakage as: I ctot, W S S L V I k Lg, Vg + S T I Tg = (EQ 15 This equation can be use to calculate the total leakage for ifferent types of evices such as NMOS/PMOS an low/high-v th transistors. The ifferences will be in the fitting parameters an the scale factor k. The sum total over all evices gives the total leakage of the chip. 3 Yiel Analysis Traitional parametric yiel analysis of high-performance integrate circuits is one using the frequency (or spee binning metho [1]. For a given lot, each chip is characterize accoring to its operating frequency an figuratively place in a particular bin accoring to this value. As was illustrate in Figure 1, ue to the inverse correlation between leakage an circuit elay chips in the fast corner prouce vast amounts of leakage current compare to the other chips. In current technologies this is a major concern since a significant number of these chips leak more than the acceptable value an must be iscare [13]. 444

4 Thus, parametric yiel loss is exacerbate since ies are lost at both the low an high spee bins, further narrowing the acceptable process winow. In this section we escribe a metho to calculate the yiel of a lot when both frequency an power limits are impose. We first show that chip frequency is most strongly influence by global gate length variability an hence, as is stanar inustry practice, each frequency bin correspons to a specific value of. We then compute the yiel ue to the impose leakage limit on a bin-by-bin basis. 3.1 Frequency Depenence on Process Parameters In principle processor frequency epens on many process parameters, such as gate length, oping concentration, an oxie thickness. However, we emonstrate from SPICE simulations that circuit elay is primarily impacte by gate length variations. For this purpose, we simulate a 17-stage ring oscillator for ifferent process conitions using the BPTM 100nm process technology as shown in Figure. At this point, we restrict our analysis to the elay impact of global variations. Although local variations also impact the circuit elay, their effect tens to average out over a circuit path which lessens the impact as compare to global variations [14]. The impact of local variations will be consiere in future extensions of this work. From the plot in Figure, we see that variations in significantly influence the elay of the ring oscillator (about ±15%. Variations in T g an have little or no impact on the elay an thus can be ignore. This is consistent with current practices where a one-to-one corresponence is often assume between frequency bins an specific gate length values. 3. Yiel Estimate Computation We now iscuss the metho to compute the expecte yiel for a particular frequency bin base on an impose leakage limit. For a particular bin, the value of is available an using the expressions for I Lg,Vg (EQ9 an I Tg (EQ13 we rewrite the equation for total chip leakage EQ15 as follows: Plot of RO Delay vs. n-sigma variation in process parameter Normalize Delay of Ring Oscillator ( k v ( T g k t I tot = A s + A g A s W S S L L V g + c L g = I k sub, nom A g = W S T I gate, nom k v = ( c 3 k t = β 1 T g Sigma Variation Figure. Comparison of the relative contribution of parameter variations on ring oscillator elay (EQ 16 Here we simplifie the notation for the fitting parameters an expresse this equation in terms of the new constants k v an k t. The values for k v an k t are generally expresse in terms of σ Vg an σ Tg. A s represents the total chip subthreshol leakage at a value of an inclues the scale factors ue to the local variability. Similarly, A g represents the total chip gate leakage at a given value of. However, since I c,gate is inepenent of, A g is not influence by changes in the value of. In a plot of total leakage vs., we first compute A s an A g at particular values of an then calculate the istribution of I tot at each of these points. For every evice type, I tot is the sum of two lognormal variables each of which represents a type of leakage current. By our formulation there is no parameter that affects both these terms simultaneously. Thus, we can consier these terms as inepenent ranom variables. We moel the sum of this pair of lognormals as another lognormal ranom variable. Using the inepenence conition, we set the sums of the means an variances to be equal to the mean an variance of the new lognormal. From EQ1 in the Appenix we get: I tot = X 1 + X X 1 LN( log( A s, ( σ Vg k v X LN( log( A g, ( σ Tg k t 1 σ Vg µ Itot = exp log( A s k v σ Itot σ Vg exp log( A s k v = σ Tg exp log( A g k t + exp 1 σ Tg log( A g k t [ exp( σ Vg k v 1] + [ exp( σ Tg k t 1] (EQ 17 EQ in the Appenix is then use to obtain the mean an variance (µ N,Itot, σ N,Itot of the normal ranom variable corresponing to this lognormal. From these values, we can express the PDF of the total leakage using the stanar expression for the PDF of a lognormal ranom variable. PDF( I tot 1 4 µ NItot, = -- log[ µ Itot ( µ Itot + σ Itot ] σ N, Itot = log[ 1 + ( σ Itot µ Itot ] 1 log ( I tot µ N, Itot = xp I tot πσ σ NItot, N, Itot (EQ 18 Finally, to obtain exact yiel estimates we require the quantile numbers for the lognormal istribution escribe by I tot, i.e., the confience points of I tot that correspon to the specifie leakage limit. Since the exponential function that relates LN(µ Itot, σ Itot with N(µ N,Itot, σ N,Itot is a monotone increasing function, the quantiles of the normal ranom variable are mappe irectly to the quantiles of the lognormal ranom variable. Using this fact, we can write the expression for the CDF of a lognormal variable: CDF( I tot F x ( I tot 1 log ( I tot µ N, Itot erf σ N, Itot = = (EQ 19 Here erf( is the error function. By setting F x ( to a particular confience point on the normal istribution, we can obtain the corresponing value on the lognormal istribution (see Table 1. In Table 1 the 0- sigma point correspons to the meian of the istribution Conversely, if we are given a limit for I tot, we can use EQ19 to compute CDF(I tot an etermine the number of chips that meet the leakage limit in a particular performance bin. Thus, in a given frequency bin an for a given leakage limit, [CDF(I tot *100]% is the fraction of chips 445

5 Table 1. Value of I tot for an n-sigma point n F x (I tot I tot exp(µ N,Itot exp(µ N,Itot σ N,Itot exp(µ N,Itot σ N,Itot exp(µ N,Itot +.878σ N,Itot that meet both the spee an power criteria. Hence, by repeating this computation for each frequency bin that meets the frequency specification, the total percentage of chips that meet both the leakage an performance constraints can be foun. Normalize Total Circuit Leakage Scatter Plot of Total Circuit Leakage 14X 3X Sim ulation Data Sigma = Global L eff Variation 4 Results In this section we use our analytical metho from the previous section to preict the yiel of a lot. Our circuit of choice is a fairly large 64-bit aer written for the Alpha architecture. We assume that all ies in the lot consist of this circuit an a small ring oscillator circuit is use to characterize the frequency of the chip with the variation in. We use the 100nm (L eff =60nm Berkeley Preictive Technology moel [4] for our SPICE Monte Carlo simulations. We also employ a gate leakage moel base on the BSIM4 equations [10]. The variability numbers for L eff, V th,nsub an T ox are base on estimates obtaine from an inustrial 90nm process. We first present a quantitative comparison between SPICE ata an our analytical metho. In Table we consier three cases (a No variability in any parameter (b Only ie-to-ie variability an (c Both within-ie an ie-to-ie variability in all three parameters. The mile three columns correspon to the sigma variation values corresponing to each parameter. Thus, for the case when both types of variability are present, the global variability values for all three parameters are set to - 1σ from the nominal while the local variability is set to be ±3σ. We see from this table that for all the cases the ifference between the experimental ata an the analytical expressions is less than 5%. Further, we note that the presence of local variability increases the amount of total chip leakage by about 15%. Figure 3 gives the scatter plot for 000 samples of the total circuit leakage generate using SPICE. The y-axis in the plot has been normalize to the sample mean of the leakage currents. We see that for a ±3σ variation in there is a 14X sprea in the leakage. Aitionally, for a given, there is a wie local istribution in leakage. For instance, given = 0σ, the normalize value of total circuit leakage is between 0.5 an 1.7. In EQ16, we observe that even for small values of (V/k v an (T/k t, the exponential terms increase rapily an contribute a larger portion to the total leakage value. As a result, the istribution in an T g (for each value of, prouces a ban-like curve for the scatter plot of total circuit leakage (instea of a single curve. This is significant since for a given value of (an hence a given operating frequency, a large portion of the chips may be about 3X the nominal leakage value. A chip that operates at an acceptable frequency may still Table. Comparison of experimental an analytical ata Cases Parameter sigma (σ values Mean Leakage (µa (, L l (, V l (T g, T l Exp Ana No variation (0, 0 (0, 0 (0, Only ie-to-ie (-1, 0 (-1, 0 (-1, Both variations (-1, ± 3 (-1, ± 3 (-1, ± Figure 3. Scatter plot showing the istribution of the total circuit leakage have to be iscare because the variability in, T g pushes its leakage consumption over the tolerable limit. Thus, we see that the seconary variations, T g play a major role in etermining the yiel of a lot. In Figure 4 we superimpose the analytically compute sigma contour lines on top of the same leakage scatter plot. For each value of, we calculate (µ N,Itot, σ N,Itot an then use Table 1 to construct the contour lines. From the plot we see that there are a fair number of samples outsie the 1σ range. This is especially true for gate lengths close to the nominal. For shorter channel lengths, since the contour value is quite large there are only a small number of chips outsie this range. For larger channel lengths, since the absolute value of the leakage is quite small, there are practically no chips outsie the σ range. We now present an example calculation for the yiel. For the lot presente here, we impose a frequency limit of +1σ an a normalize power limit (P lim of This is inicate in Figure 5. Further, the frequency bins are specifie to be at the n-sigma bounaries. First, we see that ue to the performance (frequency limit all chips that operate at frequencies smaller than the +1σ value are iscare. As we can see from the plot, although all of these chips meet the power criteria they are iscare since they are too slow. Next, we procee bin-bybin an calculate the yiel for each bin. To illustrate the yiel computation, we present the numbers for only the cases when = [-3σ,- σ,...,+1σ]. For each such, we calculate the CDF values using EQ16-EQ19. [CDF(I tot *100]% is the number of goo chips that satisfy both the power an performance criteria. Table 3 summarizes these CDF numbers for three ifferent values of P lim. Normalize Total Circuit Leakage Scatter plot with sigma contour lines Simulation Data Meian 50% 1-Sigma 68% -Sigma 95% 3-Sigma 99% Sigma = Global L eff Variation Figure 4. Scatter plot of total circuit leakage with the sigma contour lines ae 446

6 Scatter Plot with the Power/Performance Limits Specifie 3.5 Normalize Total Circuit Leakage Reject (Too Slow Reject (Too Leaky Sigma = Global L eff Variation Figure 5. Scatter plot with power an performance limits specifie Traitional parametric yiel analysis oes not consier power as a criterion an hence overestimates the number of chips that are actually goo/sellable. For instance, if P lim =1.75, we see from Table 3 that for =-σ only 7.6% of the chips meet the power criterion. Thus, even if the chip esigner bugets for 1.75 times the nominal leakage power, there is a loss of 7.4% of the chips operating in the fast corner. Furthermore, even for the nominal value of =0σ, about.5% of the chips are lost since they lie outsie the power limit. While a typical frequency binning metho woul preict that 100% of the chips with =- σ are goo, our metho captures the fact that over 5% cannot be markete uner a leakage limit of This is particularly important since fast bin evices are highly profitable. We fin that our approach always preicts a lower yiel percentage compare to the metho that assumes inepenence of the limiting factors of power an performance. By preserving the correlation between frequency an leakage we are able to obtain more accurate estimates for the yiel. 5 Conclusions In this paper we presente an analytical framework that provies a close-form expression for the total chip leakage current as a function of relevant process parameters. Separate scaling factors (associate with each parameter express the effects of local variability. Using this expression we estimate the yiel of a lot when both power an performance constraints are impose. We presente an example calculation for yiel that shows the compoune loss that occurs ue to chips that operate at low frequencies as well as chips that prouce excessive amounts of leakage. Our metho exemplifies the nee to consier both limiters when calculating the yiel of a lot. 6 Appenix Given a Normal (Gaussian ranom variable X~N(µ x,σ x, the PDF of X is given by [11]: PDF( x f X ( x Table 3. Yiel for ifferent values of P lim an P lim 1 x µ x xp πσ σ x x = = (EQ 0 ( X a 1 The function Y = g( X = e is a Lognormal ranom variable. n-sigma Using the values for (µ x,σ x we can express the mean an variance of Y in close form. ( µ x a 1 + σ x a1 µ y = e ( µ x a 1 + σ x a1 σ y = e σ x a1 e 1 (EQ 1 Conversely, given the values for the mean an variance of the Lognormal ranom variable (µ y,σ y, we can compute the mean an variance of the corresponing Normal ranom variable to obtain (µ x,σ x. (We have normalize Y by setting a 1 = µ x = -- log[ µ y ( µ y + σ y ] σ x = log[ 1 + ( σ y µy ] X+ a X a1 (EQ For the ranom variable Z = h( X = e where X is a zero mean normal ranom variable, it is possible to obtain close-form expressions for the mean an variance. a σ x a 1 + 4σ x a1 a EZ [ ] = µ z = σ a x 1 EZ [ 4a σ x a 1 + σx a1 a ] = σ a x 1 σ z = 7 Acknowlegements EZ [ ] µ z (EQ 3 We woul like to thank Vivek De from Intel for proviing us with Figure 1. This work was supporte in part by NSF, SRC, GSRC/ DARPA, IBM, an Intel. 8 References [1] S. Narenra, D. Blaauw, A. Devgan an F. Najm, Leakage issues in IC esign: Trens, estimation an avoiance, Tutorial, ICCAD 003. [] S. Borkar, Design challenges of technology scaling, IEEE Micro, 19(4, pp. 3-9, Jul [3] S. Mukhopahyay, K. Roy, Moeling an estimation of total leakage current in nano-scale CMOS evices consiering the effect of parameter variation, ISLPED 003. [4] [5] S. Borkar, T. Karnik, S. Narenra, J. Tschanz, A. Keshavarzi, V. De, Parameter variations an impact on circuits an microarchitecture, DAC 003. [6] S. Narenra, V. De, S. Borkar, D. Antoniais, A. Chanrakasan, Full-chip subthreshol leakage power preiction moel for sub-0.18um CMOS, ISLPED 00. [7] S. Mukhopahyay, A. Raychowhury, K. Roy, Accurate estimate of total leakage current in scale CMOS circuits base on compact current moeling, DAC 003. [8] R. Rao, A. Srivastava, D. Blaauw, D. Sylvester, Statistical estimation of leakage current consiering inter- an intra-ie process variation, ISLPED 003. [9] A. Srivastava, R. Bai, D. Blaauw, D. Sylvester, Moeling an analysis of leakage power consiering within-ie process variations, ISLPED 00. [10] [11] A. Papoulis, Probability, Ranom Variables an Stochastic Processes, McGraw-Hill Inc., New York [1] B. Cory, R. Kapur, B. Unerwoo, Spee binning with path elay test in 150-nm technology, IEEE Design an Test of Computers, 0(5, pp , Oct 003 [13] A. Keshavarzi, K. Roy, C. Hawkins, V. De, Multiple-parameter CMOS IC testing with increase sensitivity for I DDQ, IEEE Trans. on VLSI Systems, 11(5, pp , Oct 003. [14] A. Agarwal, D. Blaauw, V. Zolotov, S. Vruhula, Computation an refinement of statistical bouns on circuit elay, DAC