FET Inrush Protection
|
|
- Patience Spencer
- 6 years ago
- Views:
Transcription
1 FET Inrush Protection Chris Pavlina CC0 1.0 Universal Abstract It is possible to use a simple one-transistor FET circuit to provie inrush protection for low voltage DC circuits. With the aition of only one more FET, reverse-polarity protection can also be provie. Suggeste applications inclue USB evices (as the USB specification is strict about inrush) an anything requiring significant bulk ecoupling. TL;DR: If you on t care how this circuit works, feel free to skip to section 6 (Design equations) an section 7 (Gotchas). Contents 1 What not to o 2 2 Better, but not quite 2 3 Debugging 3 4 The working circuit 4 5 Deriving the esign equations 4 6 Design equations 6 7 Gotchas 7 8 Worke example 8 1
2 1 What not to o There is a circuit that is occasionally seen[4], that as a single capacitor onto the familiar MOS reverse-polarity protection circuit: Figure 1: Don t o this! It shoul be fairly obvious why this won t work. The mechanism of the reverse-polarity circuit is that the boy ioe conucts until the loa is almost fully powere, an then the voltage at the loa provies enough V GS bias to the FET to turn it on completely. There is nothing we can o to control the behavior of the boy ioe, so clearly nothing can be built onto this circuit to slow the current. Flipping the FET aroun so the boy ioe is no longer in circuit (losing the reverse protection behavior) won t work either! The FET has very high voltage gain, so using an RC circuit to ramp its gate voltage won t o much. The output voltage will still spike up quickly, allowing a large inrush. This just elays startup. 2 Better, but not quite What is neee is something a bit more clever: = 100nF 1MΩ 1MΩ 100nF Figure 2: More clever, but still on t o it! Imagining the FET as a ifferential amplifier, we can see that the circuit is actually an integrator. When the input power is connecte, the waveform seen at the input is a step, an the integral of a step is a ramp perfect! If we can control the slope of that ramp, we can easily control the inrush into our circuit s capacitance. 2
3 3 Debugging Let s buil an test the circuit, with a 12 V source an a 1000 µf capacitor as a loa. The inrush current of this circuit, as will be seen later in the esign equations, shoul be on the orer of 120 ma. 12V 100nF 1MΩ 1000µF Figure 3: The circuit we re going to test. Figure 4: Test of faulty circuit. Channels: 1 = input, 2 = output, 3 = gate voltage, 4 = inrush current The inrush current spikes very high, saturating the oscilloscope at well over 1.4 A for about 1 ms, an sits at about 200 ma for about 14 ms until it tails off. The problem is that the FET only behaves as an integrator when it is in its linear region of operation. The 100 nf timing capacitor hols the gate to the rain as the input voltage is steppe, an the source quickly rises high enough for this to put it in saturation. Theoretically, any number of components can be ae between the input noe of an integrator an a fixe voltage without changing the behavior of the integrator. Taking avantage of this, we ll a a much larger capacitor between the FET s gate an source to swamp this effect. 3
4 4 The working circuit 1µF 100nF 12V 1MΩ 1000µF Figure 5: A secon capacitor is ae to prevent immeiate saturation. Figure 6: Test of goo circuit. Channels: 1 = input, 2 = output, 3 = gate voltage, 4 = inrush current This one works! The aitional capacitor elays startup by about 250 ms, at which point V GS reaches the threshol point an the FET begins to integrate the voltage step. The voltage rises at about 57 V/s, giving an inrush current of at most about 55 ma. 5 Deriving the esign equations The circuit is essentially just an integrator: 4
5 C START C TIME R TIME C R TIME CTIME C START C Figure 7: The full circuit an its equivalent integrator. Note that the equivalent integrator circuit sees the input step as the negative of the input voltage. This is because the noninverting input (the FET s source) sits at the positive rail, an the timing resistor runs to the negative rail. The behavior of an integrator is[1, p. 230]: V out (t) = 1 V in (t) t const R C For a steppe input voltage, we can rearrange this to get the slope of the output: t V out(t) = 1 R C V in(t) In the ieal integrator circuit above, the voltage across C START will be zero at all times, so it can be ignore. Therefore, the slope of the output voltage will be: t V out(t) = R TIME C TIME A capacitor behaves accoring to i = C v [1, p. 19], so we can fin the current into the t capacitor: I = C t V OUT = C R TIME C TIME The ramp time will be equal to the input voltage ivie by the slope: t RAMP = 5 t V OUT
6 We must compute the power issipation in the FET to select an appropriate one. The instantaneous power issipation is: The average over the pulse is: P = 1 p(t) = (v out v in ) i out t RAMP ((v out v in ) i out ) t i out is constant, an v out v in is a linear slope, making the area uner this curve triangular. The integral can be compute geometrically: A triangle = 1 (w h) 2 P = 1 t RAMP 1 2 ( t RAMP I OUT ) P = 1 2 ( I OUT ) Now, we must erive C START. At inrush, C START an C TIME behave as a capacitive voltage ivier, an these must keep V GS between zero an the threshol voltage at all times. C TIME V GS = C TIME C START ( ) VIN C START = C TIME 1 V GS(th) This equation escribes the critical case, so for error margin we want: ( ) VIN C START > C TIME 1 V GS(th) 6 Design equations C START C TIME R TIME C Figure 8: The full circuit with parts labele. Unknowns are in boxes. 1. The input voltage an the loa capacitance C are known as part of your application. 6
7 2. Determine I INR, the esire inrush current. 3. Compute the resulting output voltage slope, t V OUT: t V OUT = I INR C 4. Select R TIME an C TIME. Note that either one of them can be freely chosen, an the other one compute: R TIME C TIME = 5. Compute the power issipation an ramp time: t V OUT t RAMP = P = 1 2 (I IN ) t V OUT = R TIME C TIME 6. Select a MOSFET. Ensure that its V DS rating can hanle the supply voltage, its R DS(on) is low enough for your application, an that its FBSOA (forwar-bias safe operating area) allows for a pulse of the above compute amplitue an uration. Note its minimum V GS(th) for the next part. 7. Compute C START. For error margin, it shoul be at least ouble the compute value, but o not make it too big, or the startup elay will be unnecessarily long: C START > C TIME ( VIN V GS(th) ) 7 Gotchas This circuit isn t perfect. There are few traps an rawbacks: As presente, the MOSFET must have a V GS(max) rating in excess of. If this is impractical, a secon resistor R LIMIT can be place in parallel with C START, forming a voltage ivier to set the final gate voltage. Perhaps counter-intuitively, this oes not change the timing resistance to be the Thévenin equivalent of R LIMIT an R TIME, for the same reason that C START oes not affect the timing. This circuit only limits capacitive inrush. If your inrush is for other reasons, for instance V DD ramp inrush of a large igital evice like an FPGA, it may actually worsen it. Min the maximum ramp times of the evices you are powering. If you have voltage regulators ownstream, it may be esirable to a an RC elay to their enable inputs to start them after this circuit has stabilize. 7
8 This is not a precision circuit! For the example above, I INR shoul have been C 1000 µf 12 V 1 MΩ 100 nf R TIME C TIME = = 120 ma, but it was actually 55 ma, a massive 54% error! Note that SPICE simulation verifies the accuracy of these equations, so other real-worl effects were at play here. When using more ieal components (accurate ceramic capacitors with low C(V) epenence, in particular), the real measurements will be closer to the preicte values. This circuit oes not provie reverse-polarity protection. It can be moifie with one aitional FET, though ual MOSFETs with both evices in the same package are hany here: R LIMIT C TIME C START R TIME C Figure 9: The full circuit with aitional RPP. 8 Worke example As an example, we ll esign an inrush limiter for a USB evice. Specifications are: : 5 V nominal C : 220 µf I OUT at startup: 20 ma Maximum I IN : 113 ma [3] C IN : min. 1 µf, max. 10 µf [3] 1. The input voltage an the loa capacitance C are known as part of the application. 2. I IN must not excee 113 ma, an the loa will raw I OUT = 20 ma at startup, so I INR must not excee 113 ma 20 ma = 93 ma. 8
9 3. Compute the resulting output voltage slope, t V OUT: t V OUT = t V OUT = 93 ma 220 µf I INR C = 423 V/s 4. Select R TIME an C TIME. It is likely that the system will alreay contain 100 nf capacitors, so we ll set C TIME = 100 nf. R TIME = R TIME C TIME = C TIME t V OUT t V OUT = 118 kω 120 kω 5. Compute the power issipation an ramp time. Note that this uses I IN, the total input current, not I INR, the inrush current to the capacitor. P = 1 2 (I IN ) P = 1 (5 V 113 ma) = 283 mw 2 t RAMP = t V OUT = R TIME C TIME t RAMP = (120 kω) (100 nf) = 12 ms 6. Select a MOSFET. I m going to use International Rectifier s IRLML6402, which has a low R DS(on) of 65 mω, a minimum V GS(th) of 400 mv, an fits the above power issipation nicely into its FBSOA[2]. 7. Compute C START. For error margin, it shoul be at least ouble the compute value, but o not make it too big, or the startup elay will be unnecessarily long: C START > C TIME C START > (100 nf) ( VIN C START > 1.25 µf V GS(th) ) ( ) 5 V 0.4 V A 2.2 µf capacitor woul be reasonable for C START an give some error margin. 9
10 8. The USB example is unique in that it has a minimum input capacitance, of 1 µf. The input capacitance of this circuit itself is the series combination of C START, C TIME, an C, which is 96 nf. We ll a a secon 2.2 µf at the input, which places the total input capacitance at about 2.3 µf. V BUS IRLML6402 C TIME 100nF C IN 2.2µF C START 2.2µF R TIME 120kΩ C 220µF GND Figure 10: Example with values Figure 11: Simulate example References [1] P. Horowitz an W. Hill, The art of electronics, 3r e. Cambrige [Englan]: Cambrige University Press,
11 [2] International Rectifier, IRLML6402PbF HEXFET Power MOSFET, [Online]. Available: irlml6402pbf.pf. [Accesse: 23 Nov 2015]. [3] USB Implementers Forum, Universal Serial Bus Specification, rev , pp Available: ocs/. [4] J. Walker, FET Supplies Low-Voltage Reverse-Polarity Protection, ElectronicDesign.com, [Online]. Available: fet-supplies-low-voltage-reverse-polarity-protection. [Accesse: 23 Nov 2015]. 11
Designing Information Devices and Systems I Spring 2018 Lecture Notes Note 16
EECS 16A Designing Information Devices an Systems I Spring 218 Lecture Notes Note 16 16.1 Touchscreen Revisite We ve seen how a resistive touchscreen works by using the concept of voltage iviers. Essentially,
More informationElectronic Devices and Circuit Theory
Instructor s Resource Manual to accompany Electronic Devices an Circuit Theory Tenth Eition Robert L. Boylesta Louis Nashelsky Upper Sale River, New Jersey Columbus, Ohio Copyright 2009 by Pearson Eucation,
More informationCapacitors. Chapter How capacitors work Inside a capacitor
Chapter 6 Capacitors In every device we have studied so far sources, resistors, diodes and transistors the relationship between voltage and current depends only on the present, independent of the past.
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationChapter7. FET Biasing
Chapter7. J configurations Fixed biasing Self biasing & Common Gate Voltage divider MOS configurations Depletion-type Enhancement-type JFET: Fixed Biasing Example 7.1: As shown in the figure, it is the
More informationCapacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009
Wilfrid Laurier University June 4, 2009 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists of two conductive
More informationPRACTICE 4. CHARGING AND DISCHARGING A CAPACITOR
PRACTICE 4. CHARGING AND DISCHARGING A CAPACITOR. THE PARALLEL-PLATE CAPACITOR. The Parallel plate capacitor is a evice mae up by two conuctor parallel plates with total influence between them (the surface
More informationDesigning Information Devices and Systems I Spring 2017 Official Lecture Notes Note 13
EES 6A Designing Information Devices an Systems I Spring 27 Official Lecture Notes Note 3 Touchscreen Revisite We ve seen how a resistive touchscreen works by using the concept of voltage iviers. Essentially,
More informationLinear First-Order Equations
5 Linear First-Orer Equations Linear first-orer ifferential equations make up another important class of ifferential equations that commonly arise in applications an are relatively easy to solve (in theory)
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete ata sheet, please also ownloa: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic
More informationMICROELECTRONIC CIRCUIT DESIGN Second Edition
MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113
More informationDesigning Information Devices and Systems II Spring 2019 A. Sahai, J. Roychowdhury, K. Pister Midterm 1: Practice
EES 16B Designing Information Devices an Systems II Spring 019 A. Sahai, J. Roychowhury, K. Pister Miterm 1: Practice 1. Speaker System Your job is to construct a speaker system that operates in the range
More informationSMPS MOSFET. Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )
pplications Reset Switch for ctive Clamp Reset C-C converters Lead-Free l l SMPS MOSFET P - 95293 IRF626PbF HEXFET Power MOSFET V SS R S(on) max I -50V 0.240W@V GS =-V -2.2 Benefits l Low Gate to rain
More informationECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution
ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More informationModule 2. DC Circuit. Version 2 EE IIT, Kharagpur
Moule 2 DC Circuit Lesson 9 Analysis of c resistive network in presence of one non-linear element Objectives To unerstan the volt (V ) ampere ( A ) characteristics of linear an nonlinear elements. Concept
More informationFIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL SAMEER SHARMA
FIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL By SAMEER SHARMA Bachelor of Science in Electrical Engineering Punjab Engineering College Chanigarh, Inia 1994 Master of Science in Electrical
More informationSMPS MOSFET. V DSS R DS(on) max(mw) I D
P- 9330F SMPS MOSFET IRF743 HEXFET Power MOSFET pplications l High frequency C-C converters V SS R S(on) max(mw) I 30V @V GS = V 2 Benefits l Low Gate to rain Charge to Reduce Switching Losses l Fully
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More informationEE 330 Lecture 15. Devices in Semiconductor Processes. Diodes Capacitors MOSFETs
EE 330 Lecture 15 evices in Semiconuctor Processes ioes Capacitors MOSFETs Review from Last Lecture Basic evices an evice Moels Resistor ioe Capacitor MOSFET BJT Review from Last Lecture Review from Last
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th
More informationECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION
ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationEE 330 Lecture 14. Devices in Semiconductor Processes. Diodes Capacitors MOSFETs
EE 330 Lecture 14 Devices in Semiconuctor Processes Dioes Capacitors MOSFETs Reminer: Exam 1 Friay Feb 16 Stuents may bring one page of notes (front an back) but no electronic ata storage or remote access
More information1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)
HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn
More informationEE105 Fall 2014 Microelectronic Devices and Circuits
EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)
More informationID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom
ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.
More informationELECTRONICS IA 2017 SCHEME
ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8
More informationAN6783S. IC for long interval timer. ICs for Timer. Overview. Features. Applications. Block Diagram
IC for long interval timer Overview The is an IC designed for a long interval timer. It is oscillated by using the external resistor and capacitor, and the oscillation frequency divided by a - stage F.F.
More informationSYNCHRONOUS SEQUENTIAL CIRCUITS
CHAPTER SYNCHRONOUS SEUENTIAL CIRCUITS Registers an counters, two very common synchronous sequential circuits, are introuce in this chapter. Register is a igital circuit for storing information. Contents
More informationAt point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
More informationV DSS R DS(on) max I D. 100V GS = 10V 7.3A. 58 P A = 25 C Maximum Power Dissipation 2.5 Linear Derating Factor
P - 95288 HEXFET Power MOSFET pplications High frequency C-C converters Lead-Free l l V SS R S(on) max I 0V 22m:@V GS = V 7.3 Benefits l Low Gate to rain Charge to Reduce Switching Losses l Fully Characterized
More informationE40M Capacitors. M. Horowitz, J. Plummer, R. Howe
E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast
More informationEE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
More informationDepartment of Electrical Engineering and Computer Sciences University of California, Berkeley. Final Exam Solutions
Electrical Engineering 42/00 Summer 202 Instructor: Tony Dear Department of Electrical Engineering and omputer Sciences University of alifornia, Berkeley Final Exam Solutions. Diodes Have apacitance?!?!
More informationElectronics Capacitors
Electronics Capacitors Wilfrid Laurier University October 9, 2015 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists
More informationSMPS MOSFET. V DSS R DS(on) max(mw) I D
P - 95308 SMPS MOSFET IRF7460PbF pplications l High Frequency Isolated C-C Converters with Synchronous Rectification for Telecom and Industrial Use l High Frequency Buck Converters for Computer Processor
More informationPURPOSE: See suggested breadboard configuration on following page!
ECE4902 Lab 1 C2011 PURPOSE: Determining Capacitance with Risetime Measurement Reverse Biased Diode Junction Capacitance MOSFET Gate Capacitance Simulation: SPICE Parameter Extraction, Transient Analysis
More information55:041 Electronic Circuits The University of Iowa Fall Exam 2
Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.
More informationAN3400 Application note
Application note Analysis an simulation of a BJT complementary pair in a self-oscillating CFL solution ntrouction The steay-state oscillation of a novel zero-voltages switching (ZS) clampe-voltage (C)
More informationE40M. Op Amps. M. Horowitz, J. Plummer, R. Howe 1
E40M Op Amps M. Horowitz, J. Plummer, R. Howe 1 Reading A&L: Chapter 15, pp. 863-866. Reader, Chapter 8 Noninverting Amp http://www.electronics-tutorials.ws/opamp/opamp_3.html Inverting Amp http://www.electronics-tutorials.ws/opamp/opamp_2.html
More informationCHAPTER 7 - CD COMPANION
Chapter 7 - CD companion 1 CHAPTER 7 - CD COMPANION CD-7.2 Biasing of Single-Stage Amplifiers This companion section to the text contains detailed treatments of biasing circuits for both bipolar and field-effect
More informationChapter 13 Small-Signal Modeling and Linear Amplification
Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationFeatures A, -25 V. R DS(ON) Symbol Parameter Ratings Units
FG34P igital FET, P-Channel July FG34P General escription This P-Channel enhancement mode field effect transistor is produced using Fairchild Semiconductor s proprietary, high cell density, MOS technology.
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling
More informationMA 2232 Lecture 08 - Review of Log and Exponential Functions and Exponential Growth
MA 2232 Lecture 08 - Review of Log an Exponential Functions an Exponential Growth Friay, February 2, 2018. Objectives: Review log an exponential functions, their erivative an integration formulas. Exponential
More informationNDS8947 Dual P-Channel Enhancement Mode Field Effect Transistor
March 996 NS8947 ual P-Channel Enhancement Mode Field Effect Transistor General escription Features These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary,
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley
More informationCircuit Theory Chapter 7 Response of First-Order RL and R Circuits
140310 Circuit Theory Chapter 7 Response of First-Orer RL an R Circuits 140310 Circuit Theory Chapter 7 Response of First-Orer RL an RC Circuits Chapter Objectives Be able to etermine the natural response
More informationSMPS MOSFET. V DSS R DS(on) max (mω)
P- 94094A SMPS MOSFET IRF7477 Applications l High Frequency Synchronous Buck Converters for Computers and Communications Benefits l Ultra-Low Gate Impedance l Very Low R S(on) l Fully Characterized Avalanche
More informationEE 330 Lecture 13. Devices in Semiconductor Processes. Diodes Capacitors Transistors
EE 330 Lecture 13 evices in Semiconuctor Processes ioes Capacitors Transistors Review from Last Lecture pn Junctions Physical Bounary Separating n-type an p-type regions Extens farther into n-type region
More informationCompact Modeling of Graphene Barristor for Digital Integrated Circuit Design
Compact Moeling of Graphene Barristor for Digital Inteate Circuit Design Zhou Zhao, Xinlu Chen, Ashok Srivastava, Lu Peng Division of Electrical an Computer Engineering Louisiana State University Baton
More informationCCS050M12CM2 1.2kV, 50A Silicon Carbide Six-Pack (Three Phase) Module Z-FET TM MOSFET and Z-Rec TM Diode
CCS5M2CM2.2kV, 5A Silicon Carbide Six-Pack (Three Phase) Module Z-FET TM MOSFET and Z-Rec TM Diode Features Ultra Low Loss Zero Reverse Recovery Current Zero Turn-off Tail Current High-Frequency Operation
More informationSwitching circuits: basics and switching speed
ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationSummary Notes ALTERNATING CURRENT AND VOLTAGE
HIGHER CIRCUIT THEORY Wheatstone Bridge Circuit Any method of measuring resistance using an ammeter or voltmeter necessarily involves some error unless the resistances of the meters themselves are taken
More information(d) describe the action of a 555 monostable timer and then use the equation T = 1.1 RC, where T is the pulse duration
Chapter 1 - Timing Circuits GCSE Electronics Component 2: Application of Electronics Timing Circuits Learners should be able to: (a) describe how a RC network can produce a time delay (b) describe how
More informationLecture 23: NorCal 40A Power Amplifier. Thermal Modeling.
Whites, EE 322 Lecture 23 Page 1 of 13 Lecture 23: NorCal 40A Power Amplifier. Thermal Modeling. Recall from the last lecture that the NorCal 40A uses a Class C power amplifier. From Fig. 10.3(b) the collector
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationOutcomes. Unit 14. Review of State Machines STATE MACHINES OVERVIEW. State Machine Design
4. Outcomes 4.2 Unit 4 tate Machine Design I can create a state iagram to solve a sequential problem I can implement a working state machine given a state iagram 4.3 Review of tate Machines 4.4 TATE MACHINE
More informationECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3
ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o
More informationV DSS R DS(on) max Qg. 30V GS = 10V 30nC. 170 P A = 25 C Power Dissipation 2.5 P A = 70 C Power Dissipation Linear Derating Factor
pplications l Synchronous MOSFET for Notebook Processor Power l Synchronous Rectifier MOSFET for Isolated C-C Converters Benefits l Very Low R S(on) at 4.5V V GS l Ultra-Low Gate Impedance l Fully Characterized
More informationUnit #6 - Families of Functions, Taylor Polynomials, l Hopital s Rule
Unit # - Families of Functions, Taylor Polynomials, l Hopital s Rule Some problems an solutions selecte or aapte from Hughes-Hallett Calculus. Critical Points. Consier the function f) = 54 +. b) a) Fin
More informationChapter 6. Electromagnetic Oscillations and Alternating Current
hapter 6 Electromagnetic Oscillations an Alternating urrent hapter 6: Electromagnetic Oscillations an Alternating urrent (hapter 31, 3 in textbook) 6.1. Oscillations 6.. The Electrical Mechanical Analogy
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationVectors in two dimensions
Vectors in two imensions Until now, we have been working in one imension only The main reason for this is to become familiar with the main physical ieas like Newton s secon law, without the aitional complication
More informationCircle the one best answer for each question. Five points per question.
ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions
More informationNDS9953A Dual P-Channel Enhancement Mode Field Effect Transistor
February 996 NS99A ual P-Channel Enhancement Mode Field Effect Transistor General escription Features These P-Channel enhancement mode power field effect -.9A, -V. R S(ON) =.Ω @ V = -V. transistors are
More informationFDC6301N Dual N-Channel, Digital FET
September FC6N ual N-Channel, igital FET General escription These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild 's proprietary, high cell density, MOS
More informationFDC6322C Dual N & P Channel, Digital FET
November 997 FC6C ual N & P Channel, igital FET General escription These dual N & P Channel logic level enhancement mode field effec transistors are produced using Fairchild's proprietary, high cell density,
More information= 25 o C unless other wise noted Symbol Parameter N-Channel P-Channel Units. Drain-Source Voltage V. Gate-Source Voltage 8-8 V I D
November 998 FG63C ual N & P Channel igital FET General escription These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density,
More informationRefinements to Incremental Transistor Model
Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for non-ideal transistor behavior Incremental output port resistance Incremental changes
More informationCAPACITANCE: CHAPTER 24. ELECTROSTATIC ENERGY and CAPACITANCE. Capacitance and capacitors Storage of electrical energy. + Example: A charged spherical
CAPACITANCE: CHAPTER 24 ELECTROSTATIC ENERGY an CAPACITANCE Capacitance an capacitors Storage of electrical energy Energy ensity of an electric fiel Combinations of capacitors In parallel In series Dielectrics
More informationELECTRONIC SYSTEMS. Real operational amplifiers. Electronic Systems - C2 28/04/ DDC Storey 1
Politecnico i Torino ICT school Lesson C2 Real Op mp parameters an moel ELECTRONIC SYSTEMS C OPERTIONL MPLIFIERS C.2 Real Op mp an examples» Real Op mp parameters an moel» Static an ynamic parameters»
More informationDynamic Models for Passive Components
PCB Design 007 QuietPower columns Dynamic Models for Passive Components Istvan Novak, Oracle, February 2016 A year ago the QuietPower column [1] described the possible large loss of capacitance in Multi-Layer
More informationIt's often useful to find all the points in a diagram that have the same voltage. E.g., consider a capacitor again.
17-7 (SJP, Phys 22, Sp ') It's often useful to fin all the points in a iagram that have the same voltage. E.g., consier a capacitor again. V is high here V is in between, here V is low here Everywhere
More informationChapter 11: Feedback and PID Control Theory
Chapter 11: Feeback an D Control Theory Chapter 11: Feeback an D Control Theory. ntrouction Feeback is a mechanism for regulating a physical system so that it maintains a certain state. Feeback works by
More informationDesigning Information Devices and Systems II Fall 2017 Note Theorem: Existence and Uniqueness of Solutions to Differential Equations
EECS 6B Designing Information Devices an Systems II Fall 07 Note 3 Secon Orer Differential Equations Secon orer ifferential equations appear everywhere in the real worl. In this note, we will walk through
More informationA Novel Decoupled Iterative Method for Deep-Submicron MOSFET RF Circuit Simulation
A Novel ecouple Iterative Metho for eep-submicron MOSFET RF Circuit Simulation CHUAN-SHENG WANG an YIMING LI epartment of Mathematics, National Tsing Hua University, National Nano evice Laboratories, an
More informationRC, RL, and LCR Circuits
RC, RL, and LCR Circuits EK307 Lab Note: This is a two week lab. Most students complete part A in week one and part B in week two. Introduction: Inductors and capacitors are energy storage devices. They
More informationV DSS R DS(on) max Qg. 30V GS = 10V 30nC. Thermal Resistance Parameter Typ. Max. Units Junction-to-Drain Lead g 20 Junction-to-Ambient f
pplications l Synchronous MOSFET for Notebook Processor Power l Synchronous Rectifier MOSFET for Isolated C-C Converters Benefits l Very Low R S(on) at 4.5V V GS l Ultra-Low Gate Impedance l Fully Characterized
More informationV DSS R DS(on) max I D. 100V GS = 10V 7.3A. 58 P A = 25 C Maximum Power Dissipation 2.5 Linear Derating Factor
P - 94683C HEXFET Power MOSFET Applications l High frequency C-C converters V SS R S(on) max I 0V 22m:@V GS = V 7.3A Benefits l Low Gate to rain Charge to Reduce Switching Losses l Fully Characterized
More informationFDV301N Digital FET, N-Channel
FVN igital FET, N-Channel General escription This N-Channel logic level enhancement mode field effect transistor is produced using ON Semiconductor's proprietary, high cell density, MOS technology. This
More information2N7000 / 2N7002 / NDS7002A N-Channel Enhancement Mode Field Effect Transistor
N7000 / N700 / NS700A N-Channel Enhancement Mode Field Effect Transistor Features High ensity Cell esign for Low R S(ON) Voltage Controlled Small Signal Switch Rugged and Reliable High Saturation Current
More informationFET Small-Signal Analysis
CHAPTER FET mall-ignal Analysis 9 9.1 INTROUCTION Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of a high input impedance. They are also considered low-power
More informationCCS050M12CM2 1.2kV, 25mΩ All-Silicon Carbide Six-Pack (Three Phase) Module C2M MOSFET and Z-Rec TM Diode
CCS5M2CM2.2kV, 25mΩ All-Silicon Carbide Six-Pack (Three Phase) Module C2M MOSFET and Z-Rec TM Diode Features Ultra Low Loss Zero Reverse Recovery Current Zero Turn-off Tail Current High-Frequency Operation
More informationExperiment 2, Physics 2BL
Experiment 2, Physics 2BL Deuction of Mass Distributions. Last Upate: 2009-05-03 Preparation Before this experiment, we recommen you review or familiarize yourself with the following: Chapters 4-6 in Taylor
More informationChapter 11: Feedback and PID Control Theory
Chapter 11: Feeback an D Control Theory Chapter 11: Feeback an D Control Theory. ntrouction Feeback is a mechanism for regulating a physical system so that it maintains a certain state. Feeback works by
More informationFigure Circuit for Question 1. Figure Circuit for Question 2
Exercises 10.7 Exercises Multiple Choice 1. For the circuit of Figure 10.44 the time constant is A. 0.5 ms 71.43 µs 2, 000 s D. 0.2 ms 4 Ω 2 Ω 12 Ω 1 mh 12u 0 () t V Figure 10.44. Circuit for Question
More informationTO-247-3L Inner Circuit Product Summary I C) R DS(on)
Silicon Carbide Power MOSFET N-CHANNEL ENHANCEMENT MODE TO-247-3L Inner Circuit Product Summary V DS I D(@25 C) R DS(on) 1200V 20A 120mΩ Features u Low On-Resistance u Low Capacitance u Avalanche Ruggedness
More informationFDG6322C Dual N & P Channel Digital FET
FG6C ual N & P Channel igital FET General escription These dual N & P-Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor's proprietary, high cell density,
More informationDesign Engineering MEng EXAMINATIONS 2016
IMPERIAL COLLEGE LONDON Design Engineering MEng EXAMINATIONS 2016 For Internal Students of the Imperial College of Science, Technology and Medicine This paper is also taken for the relevant examination
More informationEE 330 Lecture 12. Devices in Semiconductor Processes. Diodes
EE 330 Lecture 12 evices in Semiconuctor Processes ioes Review from Last Lecture http://www.ayah.com/perioic/mages/perioic%20table.png Review from Last Lecture Review from Last Lecture Silicon opants in
More informationChapter 11: Feedback and PID Control Theory
Chapter 11: Feeback an D Control Theory Chapter 11: Feeback an D Control Theory. ntrouction Feeback is a mechanism for regulating a physical system so that it maintains a certain state. Feeback works by
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open
More informationChapter 11: Feedback and PID Control Theory
Chapter 11: Feeback an ID Control Theory Chapter 11: Feeback an ID Control Theory I. Introuction Feeback is a mechanism for regulating a physical system so that it maintains a certain state. Feeback works
More informationECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationDISCRETE SEMICONDUCTORS DATA SHEET. BLF245 VHF power MOS transistor
DISCRETE SEMICONDUCTORS DATA SHEET September 1992 FEATURES High power gain Low noise figure Easy power control Good thermal stability Withstands full load mismatch. DESCRIPTION Silicon N-channel enhancement
More informationThermal runaway during blocking
Thermal runaway uring blocking CES_stable CES ICES_stable ICES k 6.5 ma 13 6. 12 5.5 11 5. 1 4.5 9 4. 8 3.5 7 3. 6 2.5 5 2. 4 1.5 3 1. 2.5 1. 6 12 18 24 3 36 s Thermal runaway uring blocking Application
More information