Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment

Transcription

1 Common-Centroi FinFET Placement Consiering the Impact of Gate Misalignment Po-Hsun Wu, Mark Po-Hung Lin 2, X. Li 3, an Tsung-Yi Ho 4 epartment of Computer Science an Information Engineering, National Cheng Kung University, Tainan, Taiwan 2 epartment of Electrical Engineering an AIM-HI, National Chung Cheng University, Chiayi, Taiwan 3 epartment of Electrical an Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 523, USA 4 epartment of Computer Science, National Chiao Tung University, Hsinchu, Taiwan evilangel@ea.csie.ncku.eu.tw; marklin@ccu.eu.tw; xinli@cmu.eu; tyho@cs.nctu.eu.tw ABSTRACT The FinFET technology has been regare as a better alternative among ifferent evice technologies at 22nm noe an beyon ue to more effective channel control an lower power consumption. However, the gate misalignment problem resulting from process variation base on the FinFET technology becomes even severer compare with the conventional planar CMOS technology. Such misalignment may increase the threshol voltage an ecrease the rain current of a single transistor. When applying the FinFET technology to analog circuit esign, the variation of rain currents will estroy the current matching among transistors an egrae the circuit performance. In this paper, we present the first FinFET placement technique for analog circuits consiering the impact of gate misalignment together with systematic an ranom mismatch. Experimental results show that the propose algorithms can obtain an optimize common-centroi FinFET placement with much better current matching. Categories an Subject escriptors B.7.2 [Integrate Circuits]: esign Ais - Placement an Routing; Layout. General Terms Algorithms, esign. Keywors Analog placement; FinFET; gate misalignment; common centroi.. INTROUCTION In moern system-on-chip (SoC) esign, the voltage of a transistor has been aggressively operate from the traitional superthreshol region to the sub/near-threshol region to effectively reuce power consumption of integrate circuits [4]. As the conventional planar CMOS technology scales own to the 22nm noe an beyon, it becomes more an more challenging to effectively control short channel effects (SCEs) []. As a result, high leakage This work was partially supporte by the Ministry of Science an Technology of Taiwan, uner Grant No s. NSC E-94-6, NSC E MY2, an NSC I Permission to make igital or har copies of all or part of this work for personal or classroom use is grante without fee provie that copies are not mae or istribute for profit or commercial avantage an that copies bear this notice an the full citation on the first page. Copyrights for components of this work owne by others than ACM must be honore. Abstracting with creit is permitte. To copy otherwise, or republish, to post on servers or to reistribute to lists, requires prior specific permission an/or a fee. Request permissions from permissions@acm.org. ISP 5, March 29 April, 25, Monterey, CA, USA. Copyright c 25 ACM /5/3... $5.. current an threshol voltage variation will significantly affect the circuit performance, power issipation, an reliability of circuits. To overcome the ifficulty of planar CMOS scaling, several new evice technologies have been evelope as alternatives of the bulksilicon MOSFET structure for improve reliability. Among those evice technologies, the Fin Fiel Effect Transistor (FinFET) has been regare as one of the most promising technologies to substitute the bulk-silicon MOSFET for ultimate scaling [2]. As the three-imensional (3-) structure of FinFETs can better control the rain-source channel, the leakage current can be significantly reuce ue to the alleviation of SCEs. In aition, the threshol voltage variation can also be reuce by near-intrinsic channel oping ue to ranom opant fluctuations [2]. Owing to the reuction of both leakage current an threshol voltage base on the Fin- FET technology, it ha been suggeste to esign analog integrate circuits with FinFETs for greater improvement of power, performance, an chip area [25]. : Expecte position of the printe gate : The printe gate with rain-sie misalignment : The printe gate with source-sie misalignment Gate Source rain Source rain (nm) (nm) Figure : An example of gate misalignment of a FinFET [24]. An ieal FinFET without gate misalignment. A real Fin- FET with either rain-sie or source-sie gate misalignment. Although the FinFET technology can effectively minimize the impact from SCEs an benefit power, performance, an chip area of integrate circuits, some lithography-inuce process variation, such as gate misalignment, becomes even more severe. ue to the gate misalignment, the position of the printe gate of a FinFET may be eviate from the expecte position after a set of lithography processes, which will increase the threshol voltage an ecrease the rain current of the FinFET [5, 23, 24]. Figure illustrates an example of gate misalignment. Ieally, the gate of a FinFET is expecte to be locate at the center between source an rain, as shown in Figure. However, the printe gate is usually misaligne ue to process variation, as shown in Figure. Accor- 25

2 ing to [24], the misaligne istance can be as large as 5nm either to the source sie or the rain sie for a nm process technology. Sarangia et al. [23] reporte that the threshol voltage of a Fin- FET, V th, is more sensitive with source-sie misalignment than with rain-sie misalignment. When the gate is misaligne to the rain sie of a FinFET by 5nm in the worst case, V th will be increase by.v. On the other han, when the gate is misaligne to the source sie a FinFET by 5nm, V th will be increase by.5v. Such increment will significantly egrae the rain current of the FinFET by 4% with a supply voltage of V. As most of the analog builing blocks, such as current mirrors an ifferential pairs, are very sensitive to the current variation or current mismatch, it is essential to consier the impact of gate misalignment uring the layout esign of those builing blocks. It shoul be note that uring IC fabrication, the irection an istance of gate misalignment of ifferent FinFETs on the same chip are usually the same. What esigners nee to o is to carefully arrange the orientations of all FinFETs within a current mirror or a ifferential pair such that the ratio of the rain current among ifferent transistors in a current mirror or a ifferential pair can be perfectly matche [5]. To generate a matche layout of the transistors in a current mirror or a ifferential pair, all the previous works [3, 4, 6, 8, 9, 26, 27, 28] simply followe the general common-centroi rules, incluing coincience, symmetry, ispersion, an compactness [6]. None of them consiere the impact of gate misalignment arising from the FinFET technology. Although Long et. al. [6] mentione the chirality conition of transistors within a common-centroi structure, such chirality conition cannot achieve the best current matching with the impact of gate misalignment. Other recent works [7, 8, 9,,, 2] focus on the optimization of common-centroi capacitor placement, but the capacitors in these works are still not associate with the FinFET technology. ifferent from all the previous works, we present the first problem formulation in the literature for common-centroi FinFET placement with the consieration of the impact of gate misalignment. Our contributions are summarize as follows: We propose a novel common-centroi FinFET placement formulation which simultaneously consiers all the conventional common-centroi rules, incluing coincience, symmetry, ispersion, an compactness, an the impact of gate misalignment for next generation analog layout esign. We erive a new quality metric for evaluating the matching quality of rain currents of ifferent transistors in a current mirror on the existence of gate misalignment within a common-centroi FinFET array. Base on the quality metric an the spatial correlation moel, we present the common-centroi FinFET placement flow an algorithms to optimize the orientations of all sub-transistors an maximize the ispersion egree of a common-centroi FinFET array. Our experimental results show that the propose commoncentroi FinFET placement approach can achieve much better current matching among transistors in a current mirror on the existence of gate misalignment while maintaining high ispersion egree. The rest of this paper is organize as follows: Section 2 introuces the common-centroi FinFET placement of a current mirror, an reviews the spatial correlation moel for evaluating the ispersion egree of a common-centroi FinFET placement. Section 3 emonstrates the current mismatch resulting from the impact of gate misalignment. Section 4 etails the propose commoncentroi FinFET placement algorithms. Section 5 shows the experimental results, an Section 6 conclues this paper. 2. PRELIMINARIES A current mirror, as shown in Figure 2, is one of the most important basic builing blocks in many analog circuit components. It prouces a constant replicate current, I Copy, flowing through a scale transistor regarless of its loaing by copying the reference current, I Ref, flowing through another reference transistor. If the size, or the channel with, of the scale transistor is n times larger than that of the reference transistor, I Copy will be also scale by a factor of n with respect to I Ref. A current mirror may have several replicate currents with ifferent scaling factors. : Gate : Fin : iffusion : Metal I Ref I Copy M M 2 M M 2 S M2 S M Figure 2: A current mirror, where the size of the transistors, M an M 2, are the same. An example common-centroi FinFET placement of the current mirror in, where M an M 2 are split into two sub-transistors with the same number of fins, respectively. When generating a common-centroi placement of a current mirror, it is require to optimize the matching quality among the reference transistor an all the other scale transistors for accurate scaling factors. Accoring to [], the mismatch occurs ue to process variation can be ivie into two categories: systematic mismatch an ranom mismatch. To reuce systematic mismatch, each transistor is split into several smaller sub-transistors of the same size, an each sub-transistor shoul be place symmetrically with respect to a common center point, as shown in Figure 2, where each transistor in Figure 2 is ivie into two sub-transistors. On the other han, ranom mismatch is mainly relate with statistical fluctuations in processing conitions or material properties. Because these fluctuations are in ranom mechanisms, all sub-transistors of each transistor shoul be istribute throughout a layout to reuce ranom mismatch. In other wors, all sub-transistors shoul exhibit the highest egree of ispersion in a common-centroi subtransistor array [22]. A spatial correlation moel [, 7] ha been propose in the literature to measure the ispersion egree of a common-centroi placement. Assume that a set of sub-transistors of all transistors are arrange in an r c matrix. For any two sub-transistors, st i an st j, which are locate at the entries in the r th i row an c th j Equation (). row an c th i column an the rj th column, their correlation coefficient ρ ij is efine in ρ ij = ρ (i,j) u, () where < ρ u <, an (i, j) = (r i r j) 2 + (c i c j) 2 l. l epens on process an size of transistors. Accoring to [7], 26

3 they assume that ρ u =.9 an l = to observe the relation between correlation an mismatch. Let L enotes the overall correlation coefficient, or the ispersion egree, of a common-centroi placement. For n transistors, L is the summation of all correlation coefficients of a pair of transistors an is efine as Equation (2). L = n n i= j=i+ R ij, (2) where R ij is the correlation coefficient of two transistors, t i an t j. Assume that t i consists of n i sub-transistors an t j consists of n j sub-transistors. R ij can be calculate by Equation (3). ni nj a= b= R ij = ρ ab, (3) X Y where X = n i + 2 n i a= an Y = n j + 2 n j a= ni b=a+ ρ ab, nj b=a+ ρ ab. Base on the above mathematical moel, we want to generate common-centroi placement with larger L for higher ispersion egree. 3. CURRENT MISMATCH UE TO GATE MISALIGNMENT As mentione in Section, the gate misalignment problem base on the FinFET technology may have great impact on rain currents among ifferent transistors in a current mirror. In aition to maximizing the ispersion egree of a common-centroi placement for minimizing ranom mismatch, it is require to stuy how to evaluate the matching quality of current ratios resulting from a commoncentroi placement with known orientations of all sub-transistors within a common-centroi FinFET array on the existence of gate misalignment. In this section, we will first erive the quality metric for evaluating the current mismatch of a current mirror on the existence of gate misalignment within a common-centroi FinFET array, an then give a case stuy to show the importance of etermining the orientation of each transistor uring common-centroi placement for minimizing the impact of gate misalignment. 3. Evaluation of Current Mismatch We are given a set of k transistors an each transistor, t i, contains n i sub-transistors with etermine orientations. ue to the impact of gate misalignment, the threshol voltage of the sub-transistors with rain-sie misalignment is Vth an the threshol voltage of the sub-transistors with source-sie misalignment is Vth. s The resulting current ratio, I n : I n2 :... : I nk, of these transistors with the impact of gate misalignment can be expresse, as given in Equation (4): I n : I n2 :... : I nk = n : n 2 :... : n k = (n f(v th) + n s (n 2 f(v th) + n s 2 (n k f(v th)) : th)) :... : th)), where n i enotes the number of sub-transistors of t i with rainsie misalignment, an n s i enotes the number of sub-transistors of t i with source-sie misalignment (i.e., n i = n i + n s i ), an f(x) is a function of rain current base on given voltage x. (4) Base on the multiplication property of equality, we can erive the expression in Equation (5): n (n f(v th) + n s n 2 (n 2 f(v th) + n s 2 n k (n k f(v... = th)). After splitting the Equation (5), we can obtain a set of k (k ) equalities, as shown in Equation (6): n (n f(vth) + n s n 2 (n 2 f(vth) + n s 2 n (n f(vth) + n s n 3 (n 3 f(vth) + n s 3 n k 2 (n k 2 f(v 2 n k (n k f(v n k (n k f(v n k (n k f(v th)), th)),..., th)), th)). By substituting n i = n i + n s i into the above equalities an simplifying the equalities, a set of equations can be erive, as shown in Equation (7): f(vth) s f(vth) n n s 2 n 2 n s = ɛ 2, n n 2 f(vth) s f(vth) n n s 3 n 3 n s = ɛ 3,..., n n 3 f(vth) s f(vth) n k n s k n k n s k = ɛ (k ) (k), n k n k (7) where ɛ i j enotes the current mismatch between two transistors, t i an t j, an ɛ i j. If the resulting current ratio equals to the expecte current ratio (i.e., no current mismatch), ɛ i j will be equal to. Consequently, the overall current mismatch among ifferent transistors in a current mirror, ɛ, can be obtaine by summing up all ɛ i j, as seen in Equation (8): ɛ = ɛ 2 + ɛ ɛ (k ) (k) k k = = i= j=i+ k k i= j=i+ ɛ i j ( f(v th) f(v s th) n i n s j n j n s i n i n j ). 3.2 A Case Stuy We conuct a case stuy, as emonstrate in Figure 3, for the following purposes: () comparing ifferent common-centroi placements with an without consiering the impact of gate misalign- (5) (6) (8) 27

4 Table : Comparisons of the simulate current ratios, current mismatch (ɛ) an ispersion egree (L) for ifferent common-centroi placements in Figures 3 (). Test Case # of Sub-transistors Simulate Current Ratio ɛ L Figure 3. :.93 : 2.7 : Figure 3(c) 2, 2, 4, 8. :.93 :.93 : Figure 3(). :. : 2. : ment an ispersion, (2) evaluating the resulting current mismatch an ispersion egree of each common-centroi placement, an (3) justifying the correctness of Equation (8) base on circuit simulation. I Ref M M 2 M 3 M 4 *2- -3* *4- -4* -3* *4- -4* *- -* *4- -4* *3- -4* *4- -3* *2- I Copy I 2 I 3 I 4 *3- -4* *2- -4* -4* *3- -4* *- -* *4- -3* *4- -4* *2- -4* *3- (c) *: rain -: Source *4- -3* *2- -4* -* -4* *4- -3* *3- -4* *4- *- *4- -2* *3- -4* () Figure 3: Comparisons of ifferent common-centroi FinFET placements. A current mirror with the iea current ratio, I Ref : I 2 : I 3 : I 4 is : : 2 : 4. A common-centroi Fin- FET placement for the current mirror in without consiering both gate misalignment an ispersion. (c) A commoncentroi FinFET placement for the current mirror in with the consieration of ispersion. () A common-centroi Fin- FET placement for the current mirror in with the consierations of both gate misalignment an ispersion. The current mirror in Figure 3 consists of four transistors. The reference current, I Ref, flows through the reference transistor, M, an the replicate currents, I 2, I 3, an I 4, are copie from I Ref to other three transistors, M 2, M 3, an M 4 with ifferent scaling factors. The scaling factors, or the number of sub-transistors of M, M 2, M 3, an M 4 are 2, 2, 4, an 8, respectively, so the ieal current ratio, I Ref : I 2 : I 3 : I 4, is : : 2 : 4. Figures 3 () give three ifferent common-centroi FinFET placements for the current mirror in Figure 3 with an without consiering gate misalignment an ispersion. For each common-centroi placement in Figure 3, we evaluate the ispersion egree an current mismatch base on Equations (2) an (8), an observe the resulting rain current of each transistor by performing SPICE simulation base on the BSIM- CMG moel [5]. Without loss of generality, we assume that the printe gates of all sub-transistors in each common-centroi placement are misaligne to the right sie, so the printe gate of a subtransistor will have either rain-sie or source-sie misalignment accoring to its orientation. As mentione in Section, in the worst case, V th is increase by.v with rain-sie misalignment an increase by.5v with source-sie misalignment base on a nm FinFET technology with V supply voltage, an hence the function, f(vth f(vth), s in Equation (8) is equal to.69 (A). We also aopt these settings to ajust the threshol voltage of each sub-transistor for SPICE simulation. Table reports the resulting simulate current ratio, current mismatch (ɛ), an ispersion egree (L) for each common centroi placement in Figures 3 (). Accoring to the Table, the commoncentroi FinFET placement in Figure 3 without consiering both gate misalignment an ispersion results in worse ispersion egree an current ratio matching. The common-centroi FinFET placement in Figure 3(c), with the only consieration of ispersion an without consiering the impact of gate misalignment, results in better ispersion egree, but the worst current ratio matching. The common-centroi FinFET placement in Figure 3() with the consierations of both gate misalignment an ispersion results in the best ispersion egree an current ratio matching. Consequently, it is very important to consier both gate misalignment an ispersion to effectively reuce the current mismatch an to maximize the ispersion egree. The current mismatch ue to gate misalignment can be eliminate if the orientation of each sub-transistor is carefully arrange. 4. COMMON-CENTROI FINFET PLACE- MENT ALGORITHMS Base on the evaluation metrics of ispersion egree an current mismatch in Equations (2) an (8), in this section, we propose our algorithms to generate an optimize common-centroi FinFET placement with the consierations of the impact of gate misalignment an ispersion. Our approach starts with the etermination of sub-transistor orientations, which is etaile in Section 4.. Base on the etermine orientations, an initial common-centroi FinFET placement is then generate by maximizing iffusion sharing an ispersion egree in each row, which is illustrate in Section 4.2. A final placement refinement is one by a shortest path formulation for maximizing the ispersion egree among sub-transistors in ifferent rows, which is escribe in Section etermination of Sub-transistor Orientations As explaine in the previous section, to reuce the current mismatch, the orientation of the sub-transistors must be properly etermine. We formulate the problem as fining the minimum-weight clique [3] in an unirecte graph to simultaneously etermine the orientation of all sub-transistors. Each vertex in the graph represents one configuration of the sub-transistor orientations of a transistor, t i, which has n s i sub-transistors with source-sie misalignment an n i sub-transistors with rain-sie misalignment, respectively. There exists an ege between two vertices if the vertices correspon to two ifferent transistors, t i an t j. The ege weight, ɛ i j, which can be calculate by Equation (7), enotes the current mismatch between t i an t j base on the configurations of sub-transistor orientations represente by the vertices. We enumerate all possible configurations (i.e., a k-finger FinFET have k+ configurations whose orientations are the combination of sourcesie misalignment an rain-sie misalignment) of sub-transistor orientations for each transistor in the graph. Figure 4 shows an minimum-weight-clique formulation for a current mirror with three 28

5 transistors, A, B, an C, where each transistor has 2, 2, an 3 possible configurations of sub-transistor orientations, respectively. By fining the minimum-weight clique in the unirecte graph, the best configuration of sub-transistor orientations for each transistor can be etermine such that the minimum current mismatch can be achieve. n A2s, n A2 n As, n A n Bs, n B A2-C B-C3 n B2s, n B2 n Cs, n C n C2s, n C2 n C3s, n C3 Figure 4: An example minimum-weight-clique formulation for a current mirror with three transistors, A, B, an C, where each transistor has 2, 2, an 3 possible configurations of subtransistor orientations, respectively. 4.2 Common-Centroi FinFET Placement Consiering ispersion an iffusion Sharing After etermining the sub-transistor orientations, we want to generate a common-centroi FinFET placement while maintaining the sub-transistor orientations an maximizing the ispersion egree. When generating an m-row common-centroi FinFET placement, we first evenly istribute all sub-transistors of each transistor to the m rows such that the ispersion egree of a common-centroi FinFET placement can be effectively maximize in the subsequent steps. Given a set of n i sub-transistors of a transistor, t i, we assign n i sub-transistors into each row. If ni is less than m, we ranomly assign the sub-transistors into ifferent rows while keeping m the numbers of sub-transistors in ifferent rows the same. S C B S S C A S S B C S (c) : Transistor A : Transistor B : Transistor C S S C B S C A S B C S Figure 5: An example of constructing the iffusion graph. A set of sub-transistors with fixe orientation. The corresponing iffusion graph of. (c) The generate row placement by searching the iffusion graph in. Once all sub-transistors are assigne into ifferent rows, we shoul consier the iffusion-sharing for transistors. We construct the iffusion graph of the sub-circuit in each row, an then we fin the Euler paths on the iffusion graph [2]. However, the iffusion graph we use in this paper is ifferent from [2]. As escribe in the previous subsection, we have etermine the orientation of all sub-transistors. To avoi egraing the current mismatch, the orientations of all sub-transistors cannot be change uring searching the Euler path. Therefore, the constructe iffusion graph is a irecte graph instea of a unirecte graph use in [2], where the number of irecte eges originate from source noe (S) to rain noe () equals to the number of sub-transistors with rainsie misalignment, an vice versa. For example, given a set of sub-transistors with fixe orientation as shown in Figure 5, a irecte iffusion graph can be create as given in Figure 5. In this example, for simplification, we assume that the source terminal/rain terminal of ifferent sub-transistors can be merge. If the source/rain terminals of some sub-transistors cannot be merge, extra source/rain noes in the iffusion graph is create. Accoring to the spatial correlation moel in Section 2, to effectively maximize the ispersion egree of a common-centroi Fin- FET placement, all sub-transistors belonging to the same transistor shoul be properly separate while the sub-transistors belonging to ifferent transistors shoul be as close as possible. For clear presentation, we efine ifferent kins of sub-transistors in efinition. EFINITION. Two sub-transistors are calle unrelate transistors (relate transistors), if they belong to ifferent transistors, t i an t j (the same transistor, t i). To effectively maximize the ispersion egree of a commoncentroi FinFET placement, we set a maximum separation (minimum separation) constraint, as efine in efinition 2, for two unrelate transistors (relate transistors) to constrain the selection of ege uring fining the Euler paths such the ispersion egree can be effectively maximize. EFINITION 2. A maximum separation constraint (minimum separation constraint) is the maximum (minimum) allowable istance between two neighboring unrelate transistors (relate transistors) when fining the Euler paths, which is enote by max_sep ( min_sep). The istance between two neighboring sub-transistors refers to the number of sub-transistors between the neighboring sub-transistors. uring searching the Euler path, we only choose the ege satisfying both maximum an minimum separation constraints to properly istribute ifferent sub-transistors while maximizing the ispersion egree. Initially, min_sep is set to an max_sep is set to the number of sub-transistors in the row to start the proceure of searching the Euler paths. By iteratively increasing min_sep an ecreasing max_sep uring the proceure of searching the Euler path until an extra iffusion gap is require, the ispersion egree of the resulting row placement can be effectively maximize. After obtaining the Euler paths, the sub-transistors on the same Euler path are merge with iffusion sharing. For example, starting from the source noe, as seen in Figure 5, an optimize row placement, as shown in Figure 5(c) can be obtaine by iteratively searching the Euler paths with ecreasing the maximum separation constraint an increasing the minimum separation constraint. In this example, the iteration stops when max_sep = 3 an min_sep =, which oes not incur an extra iffusion gap. Since the sub-transistors in (m i+) th row are symmetrical to that in i th row for a m-row common-centroi FinFET placement, its placement can be erive by placing merge sub-transistors in (m i + ) th row in the reverse orer of that in i th row. By performing the above steps for each row, we can obtain a final 29

6 common-centroi FinFET placement such that the iffusion sharing an the ispersion egree among all sub-transistors in each row is maximize. 4.3 ispersion egree Maximization After obtaining an initial common-centroi FinFET placement with optimize iffusion sharing an ispersion egree of the subtransistors in each row, we further maximize the ispersion egree of sub-transistors in ifferent rows by ajusting the relative positions of ifferent sub-transistors among ifferent rows. We first perform placement rotation for each row by iteratively moving the sub-transistor at the en of the row to the beginning of the row. For example, given a row placement, as shown in Figure 6, after iteratively moving the sub-transistor at the en of the row to the beginning of the row, we can erive other three row placements, as shown in Figure 6 (). *4- -3* *2- -4* (c) -4* *4- -3* *2- *2- -4* *4- -3* -3* *2- -4* *4- Figure 6: An example of placement rotation in a row. An initial row placement. () Three erive row placements after placement rotation. After performing placement rotation for each row, we nee to etermine the best placement of each row with the largest ispersion egree of the sub-transistors in ifferent m rows. The simultaneous selection of the best placement of ifferent rows can be formulate as the shortest path (SP) problem. Initially, a source noe (S) an a sink noe (T) are create, respectively. For a respective row, a group noe is create, where a set of element noes representing the possible row placements are containe in the group noe, as emonstrate in Figure 7. Once the group noes an element noes are create, we then a a set of irecte eges from S to each element noe in the group noe corresponing to the first row, an a set of irecte eges from each element noe in the group noe corresponing to the last row to T, where the weight of these eges are all zero. For two ajacent rows, there is a irecte ege from an element noe in the group noe corresponing to the i th row to an element noe in the group noe corresponing to the (i + ) th row, where i < m. The weight of each ege is calculate base on Equation (8), which inicates the current mismatch. By fining the shortest path from S to T, the best placement of each row can be etermine an the ispersion egree of the whole commoncentroi FinFET placement can be further maximize. Figure 7 shows an example of the SP formulation for a 4-row common-centroi FinFET placement. Each row has three possible row placements after placement rotation. After solving the SP problem, the 2 n, st, 3 r, an 2 n placements of the st, 2 n, 3 r, an 4 th rows are selecte to achieve the best common-centroi Fin- FET placement with the maximum ispersion egree. 5. EXPERIMENTAL RESULTS We implemente the propose common-centroi FinFET placement methoology in the MATLAB programming language on a 3.4GHz Winows machine with 6GB memory. To emonstrate the effectiveness of our approach, we create a set of testcases of current mirrors, CM, CM2,..., CM8, with ifferent with ratios of the transistors as shown in the secon column of Table 2. () S R 3 R2 3 R R2 R 2 R 3 : Group noe R2 2 R3 R3 2 R2 3 R3 3 Rij : Element noe R4 R4 2 R4 3 Weight Figure 7: An example of the shortest-path (SP) formulation for a 4-row common-centroi FinFET placement. We compare our approach with Lin et al. s approach [4], which is known to be the most recent work in the literature hanling common-centroi transistor placement with the consierations of iffusion sharing an ispersion. For each common-centroi Fin- FET placement generate by both approaches, we performe SPICE simulation base on the BSIM-CMG moel [5] to obtain the rain current of each transistor in the current mirror. We also evaluate the current mismatch base on Equation (8) an the ispersion egree base on Equation (2). TABLE 3 show the experimental comparisons of Lin et al. s approach an ours. The results show that our approach results in much better current matching an even better ispersion egree in all test cases. We i not compare the placement area because the area resulting from both approaches for each test case is the same. The runtime base on our approach is longer because we aitionally optimize sub-transistor orientations for minimizing the impact of gate misalignment. Consequently, it is very important to consier the impact of gate misalignment an ispersion uring common-centroi FinFET placement. Table 2: Benchmark statistics. Circuits # of Sub-transistors CM, CM2,, 2 CM3,, 2, 4 CM4,, 2, 4, 8 CM5,, 2, 4, 8, 6 CM6,, 2, 4, 8, 6, 32 CM7,, 2, 4, 8, 6, 32, 64 CM8,,2, 4, 8, 6, 32, 64, CONCLUSIONS In this paper, we have introuce the impact of gate misalignment to the rain current of ifferent common-centroi FinFET placements. We have propose a novel common-centroi FinFET placement approach to generate the common-centroi FinFET placements while consiering the impact of gate misalignment an ispersion. Experimental results show that the propose commoncentroi FinFET placement methoology can effectively reuce the S 3

7 Table 3: Comparisons of simulate current ratios, current mismatch (ɛ), an ispersion egree (L), base on Lin et al. s an our approaches. Circuits Lin et al. s approach [4] Our approach Comparison (%) Simulate Current Ratio ɛ/l Time (s) Simulate Current Ratio ɛ / L Time (s) ɛ / L Time CM :.93.7 /.9. :. /.9. -/.. CM2 : :.85.4 / : : 2. / /.. CM3 : :.85 : / : :.93 : / / CM4 : :.85 : 3.92 : / : :.93 : 3.93 : / / CM5 : :.85 : 3.77 : 8. : 5..4 / : :.93 : 3.86 : 7.78 : / / CM6 :.93 :.92 : 3.85 : 7.48 : 5. : / : :.93 : 3.93 : 7.63 : 5.33 : / / CM7 : :.85 : 3.85 : 7.92 : 5.63 : 3. : / : :.93 : 3.86 : 7.7 : 5.26 : 3.8 : / / CM8 :.93 :.85 : 3.85 : 7.55 : 5.48 : 3.26 : 6.77 : / : :.93 : 3.86 : 7.7 : 5.48 : 3.96 : 6.92 : / / impact of gate misalignment to the rain current an maximize the ispersion egree of a common-centroi FinFET placement. 7. REFERENCES [] International Technology Roamap for Semiconuctors, 22. [2] T. Chiarella, L. Witters, A. Mercha, C. Kerner, M. Rakowski, C. Ortollan, L.-ÃĚ. Ragnarsson, B. Parvais, A. e Keersgieter, S. Kubicek, A. Reolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, an T. Hoffmann. Benchmarking SOI an bulk FinFET alternatives for PLANAR CMOS scaling succession. Soli-State Electron., 54(9):855 86, Sept. 2. [3] T. H. Cormen, C. E. Leiserson, R. L. Rivest, an C. Stein. Introuction to Algorithms. MIT Press an McGraw-Hill Book Co., 2 eition, 2. [4] R. reslinski, M. Wiekowski,. Blaauw,. Sylvester, an T. Muge. Near-threshol computing: reclaiming MooreâĂŹs law through energy efficient integrate circuits. In Proceeings of the IEEE, pages , 2. [5] M. Fule, A. Mercha, C. Gustin, B. Parvais, V. Subramanian, K. von Arnim, F. Bauer, K. Schruefer,. Schmitt-Lansieel, an G. Knoblinger. Analog esign challenges an trae-offs using emerging materials an evices. In Proceeings of IEEE European Soli State evice Research Conference, pages 23 26, 27. [6] A. Hastings. The Art of Analog Layout. Prentice Hall, 2 eition, 26. [7] C.-C. Huang, C.-L. Wey, J.-E. Chen, an P.-W. Luo. Optimal common-centroi-base unit capacitor placements for yiel enhancement of switche-capacitor circuits. ACM T ES AUTOMAT EL, 9():7: 7:3, ec. 23. [8] Y. Li, Z. Zhang,. Chua, an Y. Lian. Placement for binary-weighte capacitive array in SAR AC using multiple weighting methos. IEEE Trans. Comput.-Aie esign Integr. Circuits Syst., 33(9): , Sept. 24. [9] C.-W. Lin, C.-L. Lee, J.-M. Lin, an.-j. Chang. Analytical-base approach for capacitor placement with graient error compensation an evice correlation enhancement in analog integrate circuits. In Proceeings of IEEE/ACM International Conference on Computer-Aie esign, pages , 22. [] C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, an S.-J. Chang. Mismatch-aware common-centroi placement for arbitrary-ratio capacitor arrays consiering ummy capacitors. IEEE Trans. Comput.-Aie esign Integr. Circuits Syst., 3(2):789 82, ec. 22. [] M. P.-H. Lin, Y.-T. He, V. W.-H. Hsiao, R.-G. Chang, an S.-Y. Lee. Common-centroi capacitor layout generation consiering evice matching an parasitic minimization. IEEE Trans. Comput.-Aie esign Integr. Circuits Syst., 32(7):99 2, July 23. [2] M. P.-H. Lin, V. W.-H. Hsiao, an C.-Y. Lin. Parasitic-aware sizing an etaile routing for binary-weighte capacitors in charge-scaling AC. In Proceeings of ACM/IEEE esign Automation Conference, pages 6, 24. [3] M. P.-H. Lin, H. Zhang, M.. F. Wong, an Y.-W. Chang. Thermal-riven analog placement consiering evice matching. In Proceeings of ACM/IEEE esign Automation Conference, pages , 29. [4] M. P.-H. Lin, H. Zhang, M.. F. Wong, an Y.-W. Chang. Thermal-riven analog placement consiering evice matching. IEEE Trans. Comput.-Aie esign Integr. Circuits Syst., 3(3): , Mar. 2. [5] W. Liu, X. Jin, J. Chen, M-C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P.K. Ko, an Chenming Hu. Bsim 3v3.2 mosfet moel users manual. Technical Report UCB/ERL M98/5, EECS epartment, University of California, Berkeley, 998. [6]. Long, X. Hong, an S. ong. Optimal two-imension common centroi layout generation for MOS transistors unit-circuit. In Proceeings of the IEEE International Symposium on Circuits an Systems, pages , 25. [7] P.-W. Luo, J.-E. Chen, C.-L. Wey, L.-C. Cheng, J.-J. Chen, an W.-C. Wu. Impact of capacitance correlation on yiel enhancement of mixe-signal/analog integrate circuits. IEEE Trans. Comput.-Aie esign Integr. Circuits Syst., 27():297 2, Nov. 28. [8] Q. Ma, L. Xiao, Y. C. Tam, an E. F. Y. Young. Simultaneous hanling of symmetry, common centroi, an general placement constraints. IEEE Trans. Comput.-Aie esign Integr. Circuits Syst., 3():85 95, Jan. 2. [9] Q. Ma, E. F. Y. Young, an K. P. Pun. Analog placement with common centroi constraints. In Proceeings of ACM/IEEE International Conference on Computer-Aie esign, pages , 27. [2] R. Naiknaware an T.S. Fiez. Automate hierarchical CMOS analog circuit stack generation with intramoule connectivity an matching consierations. IEEE J. Soli-State Circuits, 34(3):34 33, Mar [2] S. H. Rasouli, K. Eno, an K. Banerjee. Variability analysis of FinFET-base evices an circuits consiering electrical confinement an with quantization. In Proceeings of IEEE/ACM International Conference on Computer-Aie esign, pages 55 52, 29. [22] B. Razavi. esign of Analog CMOS Integrate Circuits. McGraw-Hill Book Co., 2. [23] S. Sarangia, S. Bhushana, A. Santraa, S. ubeyb, S. Jitb, an P. K. Tiwari. A rigorous simulation base stuy of gate misalignment effects in gate engineere ouble-gate (G) MOSFETs. Superlattices Microstruct., 6(): , Aug. 23. [24] R. Valin, C. Sampero, M. Alegune, A Garcia-Loureiro, N. Seoane, A Gooy, an F. Gamiz. Two-imensional monte carlo simulation of GSOI MOSFET misalignment. 59(6):62 628, June 22. [25] P. Wambacq, B. Verbruggen, K. Scheir, J. Borremans, M. ehan,. Linten, V. e Heyn, G. Van er Plas, A Mercha, B. Parvais, C. Gustin, V. Subramanian, N. Collaert, M. Jurczak, an S. ecoutere. The potential of FinFETs for analog an RF circuit applications. IEEE Trans. Circuits Syst. Regul. Pap., 54(): , Nov. 27. [26] L. Xiao an E. F. Y. Young. Analog placement with common centroi an - symmetry constraints. In Proceeings of ACM/IEEE Asia an South Pacific esign Automation Conference, pages , 29. [27] T Yan, S. Nakatake, an T. Nojima. Formulating the empirical strategies in moule generation of analog MOS layout. In Proceeings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies an Architectures, pages 44 49, 26. [28] L. Zhang, S. ong, Y. Ma, an X. Hong. Multi-stage analog placement with various constraints. In Proceeings of IEEE International Conference on Communications, Circuits an Systems, pages , 2. 3