FIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL SAMEER SHARMA

Transcription

1 FIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL By SAMEER SHARMA Bachelor of Science in Electrical Engineering Punjab Engineering College Chanigarh, Inia 1994 Master of Science in Electrical an Computer Engineering Oklahoma State University Stillwater, Oklahoma December, 003 Submitte to the Faculty of the Grauate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of DOCTOR OF PHILOSOPHY May, 008

2 FIRST ORDER QUASI STATIC MOSFET CHANNEL CAPACITANCE MODEL Dissertation Approve: Dr. Louis G. Johnson Dissertation Aviser Dr. George Scheets Dr. James E. Stine, Jr. Dr. H. K. Dai Dr. Goron Emslie Dean of the Grauate College ~ii~

3 TABLE OF CONTENTS CHAPTER PAGE I. INTRODUCTION MODELING PROCESS SCOPE OUTLINE... 5 II. LITERATURE REVIEW MEYER S MODEL CHARGE BASED MODELS TRANS-CAPACITIVE MODEL MEHMET MODEL III. FIRST ORDER QUASI-STATIC CHANNEL CAPACITANCE MODEL STEADY STATE OPERATION QUASI-STATIC OPERATION MODELING EQUATIONS... 1 IV. MOSFET POWER SOURCES OF POWER DISSIPATION POWER AND ENERGY MODELING ISSUES POWER MEASUREMENT TECHNIQUES POWER EQUATIONS ENERGY FUNCTION CALCULATION V. FIRST ORDER CURRENT COMPONENTS AND CAPACITANCE CALCULATION ~iii~

4 CHAPTER PAGE 5.1 FIRST ORDER CURRENT COMPONENTS CAPACITANCE DERIVATION EQUIVALENT CIRCUIT VI. COMPARISON AND DISCUSSION MODEL VERIFICATION AND ADVANTAGES ENERGY PUMPING TOTAL FIRST ORDER POWER SIMULATION EXAMPLE... 5 VII. DEPENDENCE OF THE BSIM ABULK PARAMETER ON THE SOURCE POTENTIAL EVALUATION OF EXTRA CURRENT COMPONENTS SIMULATION EXAMPLE CONCLUSION REFERENCES APPENDICES... 7 ~iv~

5 LIST OF TABLES TABLE PAGE Table 3.1 NMOS Zero an First Orer Charges an Currents.. 5 Table 4.1 Power Equations. 37 Table 4. Energy Function. 39 Table 5.1: Storage an Dissipative Current Components... 4 Table 5.3: Total Capacitances.. 44 Table 5.4: Conserve Capacitances. 45 Table 5.5: Dissipative Capacitances 46 ~v~

6 LIST OF FIGURES FIGURE PAGE Figure 1.1: Energy Imbalance. 3 Figure.1: Meyer Capacitance Moel. 8 Figure.: Channel Current Calculations 9 Figure.3: Current Representation in Meyer s Moel. 11 Figure.4: Channel Charge approximation using War s Moel 1 Figure.5: Trans-capacitance Approximation 15 Figure.6: Small Signal Representation of Mehmet s Moel. 17 Figure 3.1: Bulk an SOI CMOS Structures Figure 3.: Voltage, Charge an Current Waveforms... 0 Figure 3.3: Four terminal MOSFET Structures Figure 4.1: Leakage Current Components 8 Figure 4.: Dynamic Power. 30 Figure 4.3: Transient Waveforms. 31 Figure 4.4: Capacitor base Power Measurement Technique 34 Figure 4.5: Power Dissipation in MOS Transistor.. 34 Figure 4.6: MOS Channel Power Calculation Figure 5.1: First orer issipative an conserve current components Figure 5.: Total, Conserve an Dissipative Capacitances vs v s. 44 Figure 5.3: Equivalent Circuit 47 ~vi~

7 FIGURE PAGE Figure 6.1: Terminal capacitances vs v s Figure 6.: Capacitance vs v s Figure 6.3: Gate pumping action Figure 6.4: Average conserve gate an channel power vs frequency. 51 Figure 6.5: Iealize voltage waveforms.. 53 Figure 6.6: Total power vs. frequency. 54 Figure 6.7: Current plots.. 55 Figure 6.8: Power plots Figure 7.1: Terminal capacitances vs v s.. 59 Figure 7.: Extra power issipation Figure 7.3: Threshol voltage an bulk charge parameter.. 61 Figure 7.4: Zero orer currents Figure 7.5: First orer currents... 6 ~vii~

8 LIST OF SYMBOLS SYMBOLS NAMES q c.. channel charge per unit length q c 0 q c 1 q s.. zero orer channel charge per unit length.. first orer channel charge per unit length.. source charge per unit length q.. rain charge per unit length q g. gate charge per unit length L W c ox. channel length. channel with. oxie capacitance per unit length v fb. flat ban voltage v t 0 v t φ t ox. threshol voltage at zero source bias. threshol voltage. fermi potential. oxie thickness v cb. channel terminal voltage v gb. gate terminal voltage v sb. source terminal voltage ~viii~

9 SYMBOLS NAMES v b. rain terminal voltage k 1. boy effect coefficient k. boy effect coefficient I c 0 I D. zero orer (static) current. static rain current I S. static source current I G. static gate current I B. static substrate current I() t i 1 i s 1 i g 1 i b 1. total channel current. first orer rain current. first orer source current. first orer gate current. first orer substrate current i. first orer conserve rain current 1, cons i. first orer conserve source current s 1, cons i. first orer issipative rain current 1, iss i. first orer issipative source current s 1, iss P c 0 P P c. average power. total instantaneous power. instantaneous channel power P c 0. static power ~ix~

10 SYMBOLS NAMES P. first orer issipative channel power c 1, iss P. first orer conserve channel power c 1, cons P. first orer gate power g 1, cons C L. externally loa capacitor C gb. gate to bulk capacitance C gs. gate to source capacitance C g. gate to rain capacitance C sb. source to bulk capacitance C sg. source to gate capacitance C s. source to rain capacitance C b. rain to bulk capacitance C g. rain to gate capacitance C s. rain to rain capacitance C csb. conserve source to bulk capacitance C csg. conserve source to gate capacitance C cs. conserve source to rain capacitance C cb. conserve rain to bulk capacitance C cg. conserve rain to gate capacitance C cs. conserve rain to rain capacitance C sb. issipative source to bulk capacitance ~x~

11 SYMBOLS NAMES C sg. issipative source to gate capacitance C s. issipative source to rain capacitance C b. issipative rain to bulk capacitance C g. issipative rain to gate capacitance C s. issipative rain to rain capacitance P. BSIM first orer issipative channel power c 1, iss, B P. BSIM first orer conserve channel power c 1, cons, B P. BSIM first orer gate power g 1, cons, B P.. extra first orer channel conserve power g 1, cons Extra P.. extra first orer channel issipative power c 1, iss Extra P 1, cons. extra first orer conserve power Extra ~xi~

12 ACKNOWLEDGMENTS I woul like to express sincere thanks to my avisor Dr. Louis G. Johnson for his guiance, encouragement an the research opportunity. I woul also like to exten appreciation to my committee members Dr. George Scheets, Dr. Yumin Zhang, Dr. James E. Stine Jr. an Dr. H. K. Dai for their invaluable knowlege an guiance. Aitional thanks go to all my colleagues in VLSI Design Group for helpful iscussions on circuit simulation, evice moeling an power estimation. Finally, I woul like to acknowlege the support from my wife Srijana an two aughters Vihi an Tanya for their patience an encouragement throughout my stuies. ~xii~

13 CHAPTER I I. INTRODUCTION 1.1 MODELING PROCESS Moeling is a process of accurately representing the behavior of a evice to be use in a circuit simulator. Designers nee these reliable an accurate moels for circuit evelopment. With the growth of CMOS technology, MOSFET moeling has taken a centre stage an the accurate moeling of MOS transistor channel capacitance has been an ongoing effort. First, Meyer s [1.1] reciprocal gate-capacitive moel, then War s [1.] charge-base, non-reciprocal capacitance moel have been use. Many papers have also been written on the comparison of these moels. Some [ ] claim that Meyer s moel fails ue to charge non-conservation which justifies the usage of charge-base moels while others claim [ ] that the charge non-conservation is mainly ue to the faulty mathematical moeling of the simulation software. As pointe out by Fossum [1.10], it is not clear whether we have explore all other possibilities. We may be able to achieve a better result with a ifferent channel partition or may be with no partition at all. Recent papers on fiel-epenent mobility [1.33] an laterally asymmetrical oping [1.34] have now shown inconsistencies in War s moel, which artificially partitions the channel charge into the source an the rain components. Many ieas have also been suggeste for estimation of energy an power taking into consieration the input slew epenency [1.11], propagation elay [1.1], short circuit power [1.13] an supply current measurements [ ]. One of the most popular an wiely aapte, Berkeley Short-Channel IGFET (BSIM) Capacitive Moel [1.17, 1.18] has trie to inclue many of the above mentione moeling techniques to estimate the behavior of Insulate Gate Fiel Effect Transistors (IGFET). However, the BSIM ~1~

14 capacitive moel fails to inclue the first orer trans-capacitive currents ue to the charge reistribution in the channel that causes the actual output waveform an the elay to eviate from the BSIM stimulation results [1.19]. In reality, the MOS evice is a highly nonlinear four terminal evice an moeling it as a simple energy storage evice leaves a lot to be esire. When the inversion layer is forme, the I-R rop from the resistive components an charge reistribution current causes power issipation in the channel. This makes the assumption that the capacitive moel oes not contribute any net power issipation in the channel inconsistent for use in energy preiction. If the BSIM moel is not consistent, one may ask as why it is still being use? The reason is: the BSIM quasi-static moels are analog frienly, continuous an have goo I-V characteristic. These I-V moels are erive from the channel charge that is calculate correctly to the first orer. Power is also erive from the channel charge. The problem, however, is that the power is erive only to zero orer. In other wors, the BSIM capacitive moel calculates static power issipation, which is nothing but the multiplication of zero orer current an steay state voltage. Though the BSIM capacitive moel inclues first orer corrections in ynamic power calculation, it leaves out some important terms. We can think the process of ynamic power calculation of the BSIM moel as being nothing but an easy way of calculating the zero orer power by using the change in the energy of the capacitors uring charging an ischarging. The BSIM capacitive moel assumes that the first orer terms are the energy storage terms (like capacitors an inuctors) that o not issipate energy, which in reality is not the case. Hence it is not appropriate to look at the change in the energy of the capacitors in the channel as there is no energy function for the channel. It causes an error an gives a ifferent number for power from the supply power than the issipate power from all the evices, clearly a violation of energy conservation principles. This effect is pointe out in Fig. 1.1 which is a plot of switching frequency an the energy imbalance for ifferent with ratios of transistors in a inverter. As seen, for higher switching frequencies (small rise/fall times) the energy imbalance is more pronounce. ~~

15 In reality, it is very ifficult to estimate the usefulness of SPICE simulation in the power estimation of a real circuit. In igital applications, it is well known that the glitches can contribute half the power, an how accurately we can preict the power spike epens on how accurately we can preict the glitches. Therefore, it i not make a whole lot of ifference, as SPICE was not preicting the power accurately anyway. Even if it were able to preict the power, it is not possible to extrapolate to a real circuit with glitches that are not exactly the same as SPICE calculate. However, in the worl of Pentiums [1.0], Core Duos [1.1] an Quanti-Spee Architecture processors [1.], where the gates are switching aroun 300 billion times a secon [1.3], it becomes essential to calculate the higher orer transients to accurately preict the evice power an switching ynamics. % Error Error (10 Wp) Error (4Wp) Error (Wp) Error( Wp/) Error (Wp) Rise/Fall time in psec Figure 1.1: Energy Imbalance It shoul also be pointe out that scholars working in the MOS evice-moeling are aware of the transport current components flowing in the channel. Many papers [ ] an chapters [ ] have been written about the charging an transport current components. However, all of them assume that it is not possible to separate the issipative an energy storage components an have come up with many theories an moels to envision the transient effects. One of the moels by Lim-Fossum [1.31, 1.3] has the first orer transient trans-capacitive current an ~3~

16 suggests the ifference between non-reciprocal capacitive elements to be responsible for these transport currents. This however has some rawbacks. First, if these were the total transcapacitive currents, its prouct with the rain to source voltage shoul have been the total issipative power, which is not the case. Secon, Lim-Fossum use War s charge partition moel to fin the source an rain charge components, which makes their moel epenent on the accuracy of the charge partition. 1. SCOPE The object of the research is to realize the inconsistency in the current MOSFET moeling an evelop efficient moels for accurate intrinsic capacitance an power issipation estimation. An ieal moel woul be to consier all non linear effects an solve a complete non-linear ifferential equation for the channel in three imensions. In that case, we see a packet of charge traveling own the channel as a function of time. Although such moels are valuable, from the simulation perspective, the process is ineffective as the simulation times are very long. To be computationally efficient, we nee compact moels that escribe the electrical behavior analytically an are able to represent the non-linear channel in a reasonable time without sacrificing moeling accuracy. Furthermore, the fast scaling of frequency for semiconuctor integrate circuits that was seen in the last few ecaes has been saturating. One of the reasons is the increase in power issipation. Power limits the scaling. The high power issipation ue to small evice geometry has thrown off course the roamap of future evelopment of semiconuctor technologies. When the evices are switching rapily, the power issipation per unit area goes up causing excessive heating. Unless a sophisticate cooling system is implemente, the evice may no longer be operational. The reality is: we have reache a power limite scaling regime. Scaling now is no longer etermine by the evice size, but by how much power the chip can issipate at a particular working frequency. However, the lack of suitable evice moels to measure this power issipation has provie a plethora of research avenues. The conventional MOSFET moels have some inherent issues an are not consistent for power an energy preiction as they: ~4~

17 Fail to inclue the first orer power issipation ue to channel charge reistribution Give a net non-zero power in the channel that has no physical basis from the terms that shoul be conserve This makes the MOSFET moeling very important going forwar into the nanometer regime. Given that the accuracy of the simulation epens on the physical representation of the evice, it is very important that we have a reliable mathematical moel that is able to represent the evice behavior. Designers nee these accurate moels for circuit evelopment. 1.3 OUTLINE The outline of the issertation is as follows: Chapter escribes the conventional MOSFET moels use in transient analysis an computer simulation. The analysis of these moels gives a general overview an a goo backgroun on evice moeling. Some of these moels are still being use for evice simulation. The Meyer s moel, War s charge partition moel, Mehmet moel an Trans-capacitance moels an its effectiveness are consiere. Some of the avantages an the shortcomings are also iscusse. Chapter 3 escribes a one imensional MOSFET current moel with current continuity equations. These equations have been use to compute the channel currents an channel charges as well as currents at the source an the rain terminals for a charge conserving, quasi-static, channel capacitance moel. The calculation of channel currents without charge partition allows the computation of the instantaneous channel power, which further helps in separating the issipating an energy conserving current components. Chapter 4 escribes the etails of power estimation. Zero an the first orer instantaneous power is compute by integrating the power ensity over the entire channel. This leas to the erivation of close-form analytical expressions for the conserve an issipative current components from the first orer rain an source currents. The energy function calculations from the first orer ~5~

18 conserve power components are also shown. Chapter 5 escribes the erivation of capacitances from the first orer rain (i 1 ) an source (i s1 ) current components. These capacitances are then separate into conserve an issipative components. An improve equivalent circuit is also evelope by following the metho use by Lim-Fossum. The results are verifie using the BSIM Capacitive an Lim-Fossum fully eplete SOI moels for currents an charges in chapter 6. Even though these moels use a charge partition instea of solving exactly as we have, all moels preict the same source an rain currents, an hence the same terminal capacitances. However, we are able to separate out these capacitances into conserve an issipative components. Chapter 7 escribes the inconsistencies of the BSIM capacitive moel for energy an power preiction. We have shown that the epenence of the BSIM bulk charge parameter on the source potential causes extra power issipation in the channel that has no physical basis. This leas to an inconsistent power moel where energy supplie from the gate oes not balance out with the energy generate at the channel. ~6~

19 CHAPTER II II. LITERATURE REVIEW This chapter escribes some of the MOS moels that have been use in circuit simulators to analyze the transient response. Historically, MOS evices have been moele with capacitor an over the last few ecaes, many such capacitive moels have been propose to effectively represent the charges at the four terminals of a FET evice. The problem however is the ifficulty in representing the terminal charges by a single moel. This is because; MOS transistors not only conuct current in a steay state but also conuct when the terminal voltages are varying. The time epenence of currents an voltages of a MOSFET makes representation using steay state (DC) conitions insufficient. A solution is possible by superimposing zero orer steay state DC (I-V) representation over a capacitance (C-V) moel to characterize the transients as v It () = I ( v) + i ( v, ) c0 c1 t where I () 0 v is the steay state (DC) current an epens only on the instantaneous terminal c voltages. i () t is the transient transport component an is zero uner steay state conitions. c1 For simulation purposes, the capacitance (C-V) moel is evelope by expaning the transient current as q v i () t = = c c1 t t In the subsequent sections, some of these moels have been iscusse in chronological orer of the history of evice moeling. ~7~

20 .1 MEYER S MODEL In 1971, Meyer [.1] propose the first large signal moel for MOS transistors in terms of physical evice parameters. Figure.1: Meyer Capacitance Moel The moel represents the charge storing property of MOS transistors using three nonlinear voltage epenent capacitors, as shown in Fig. [.1]. These capacitors are efine in terms of the total gate charge Q g. Meyer s moel is a simple charge conservation moel as it restricts the sum of the gate charge Q g an channel charges Q c o be zero, an is base on the following five assumptions. The total gate charge Q g is a function of the terminal voltage uner steay state conitions. The gate capacitances are foun as: Q Q Q g g g C = C = C = (.1) gs v g v gb v gs g gb C = C + C + C gg gs g gb Where v gs, v g an v gb are the gate to source, gate to rain an gate to bulk voltages. The rain to bulk, source to bulk an rain to source capacitances are assume to be zero. C = C = C = 0 s b sb C = C = C = 0 s b bs ~8~

21 It is assume that the capacitance matrix is symmetrical, which is necessary to conserve energy. C g = C C = C C = C g gs sg gb bg The total source, rain an bulk capacitances are calculate as: C = C + C + C s g b C = C + C + C ss sg s sb C = C + C + C bb bs b bg These five assumptions give the capacitance matrix as shown below; C + C + C C C C g gs gb g gs gb C C 0 0 g g C 0 C 0 gs gs C 0 0 C gb gb To calculate the total gate charge ( Q g ), a graual channel approximation is use. The charge per unit area at any position x along the channel is given in by Qx ( ) = C ( V V V( x)) ox gb t Figure.: Channel Current Calculation where V is the gate voltage, V is the threshol voltage, V( x) is the potential at position x along gb t the channel, an C ox is the gate oxie capacitance per unit area. The steay state rain current ~9~

22 I is foun using c 0 V ( x) I = WQ( x) μ c0 x where W is the channel with an μ is the mobility. Integrating from source (x=0) to rain (x=l); W I = μc ( V V ) (.) c0 ox L gs g where L is the channel length. Gate charge is given by Q g ( V V ) 3 ( V V ) 3 g t gs t = WLC 3 ox ( V V ) ( V V ) ( V V ) ( V V ) g t gs t g t gs t (.3) Using (.1) an (.), capacitances are calculate as ( V V ) g t C = WLC 1 gs 3 ox ( V V V V ) + gs t g t (.4) C g ( V V ) gs t = WLC 1 3 ox ( V V V V ) + gs t g t (.5) C = 0 gb Finally, current through each capacitor is compute as V gs I = C gs gs t V g I = C g g t V gb I = C gb gb t Fig..4 shows the current representation of Meyer s moel. Currents I1 an I in the channel are assume to be biirectional, one being epenent on gate-to-source an other being epenent on gate-to-rain. This is also known as Two-current-source MOS moel. ~10~

23 Figure.3: Current Representation in Meyer's moel The major rawback of Meyer s moel is the exclusion of the source to bulk an rain to bulk capacitances resulting from substrate charges.. CHARGE BASED MODELS War [.-.4] claime that Meyer s moel faile the charge conservation test for circuits that require charge storage. They ientifie the presence of nonlinear reciprocal capacitances an exclusion of the source to bulk an rain to bulk capacitances as being the source of charge nonconservation in the circuit simulation. They base their finings using current equation V gs it () = Cv ( ) (.6) t Here the capacitance term is epenent on the terminal voltages of the source, rain an the gate an has been evaluate at some appropriate voltage i.e. C(v) is not efine as a time epenent variable an can follow any path an as a result may lea to some arbitrary charge value. The best possible solution with average value of capacitor taken at two time intervals may also lea to an incomplete charge preiction. Integrating from the present time point t 0 to the next time point t 1, equation (.6) can be written as t v( t ) 1itt () = 1 Cvv ( ) t (.7) v( t ) 0 0 If C(v) is consiere a constant, equation (.7) reuces to t 1 itt () = Cv ( )[ Vt ( ) Vt ( )] (.8) t ~11~

24 The capacitance value for Cvthat s () been use here is compute at time t 0. War assumes this being the reason for charge pumping, as there may be some resiual charge at time t 0. He suggests that even if the capacitive values are calculate at time t 1 or smaller time steps, it will not guarantee charge conservation. To overcome the assume charge neutrality limitations, he suggeste the charge-partition moel [.]. The charge-partition moel is base on the fixe charge istribution in the MOSFET terminals. The moel tries to split the total channel charge Q c into source (Q s ) an rain (Q ) charges rather than splitting the total istribute capacitance into reciprocal gate-to-source an gate-to-rain capacitances. The current is then compute as the erivative of charge as i( t) = Q( t) t Using similar integration approach as equation (.7) t 1 itt () = Qt ( ) Qt ( ) (.9) t Though Qt ( ) an Qt ( ) 0 1 voltage at that instant. are complex functions of time, it can be obtaine at any time by terminal Figure.4: Channel Charge Approximation using War's moel The emphasis of the charge moel was the use of charge as a state variable for the computation of charge at the MOSFET terminals. War was also able to put in perspective a current continuity equation I ( yt, ) Qyt (, ) = W y t with the bounary conitions on V(y) as V(0) = V an V( L) s = V ~1~

25 to calculate the source an rain charges together with the source an rain currents, an the transport current. Using the current continuity equation, the current at any point y on the channel is evaluate as y Qyt (, ) I( yt, ) I ( t) = W y s 0 t (.10) where I () t = I(0,) t is the source current, an L is the length of the channel. Consiering only rift s current for I( yt, ) an solving for I () t, equation (.10) reuces to two current components s V( y, t) I( y, t) = μwq( y, t) y an (.11) W L V( y, t) L y I () t = ( ytqyt,) (,) y W (1 ) Qyty (,) s μ + L 0 y t 0 L (.1) Substituting y=l to obtain the rain current W L V( y, t) L y I ( t) = ( ytqyt, ) (, ) y W ( ) Qyty (, ) μ + L 0 y t 0 L (.13) Since the rain an source current can be assume to have transport an charge components, they can be represent using Q () t I () t = I () t + s (.14) s T t Q () t I () t = I () t + (.15) T t From equations (.13) (.14) an (.15), L y Q = W (1 ) Qy s (.16) 0 L L y Q = W ( ) Qy (.17) 0 L Many moifications have been mae since War propose the original charge moel in Almost all these moels consier charge as a state variable an use non-reciprocal capacitors. Some moels have partitione the channel charge into rain an source components in the ratio ~13~

26 of 40/60 while others use a 50/50 moel. However, none of these moels aresses the actual cause of charge non-conservation. Yang, Berton an Chatterjee [.5], while investigating the charge conservation problem, observe that the non-conservation of charge in circuit simulator SPICE is ue to the integration problem inepenent of evice physics. They think the error is ue to the choice of voltage as a state variable for simulation, an also ue to the nonlinearities in the MOS capacitances an its epenence on four ifferent terminal voltages. Sakallah, Yen an Greenberg [.6] also support the view that the charge non-conservation in the Meyer capacitance moel has nothing to o with the evice physics or a faulty capacitive moel, rather by the mathematical error of characterizing a multiimensional function by an incomplete subset of its partial erivatives. They conclue that the charge non-conservation can be eliminate if circuit simulators are given non trivial moels. They also followe moeling using War s approach an proceee by splitting total channel charge into source an rain instea of splitting total istribute capacitance between the gate an the channel into reciprocal gate-tosource an gate-to-rain capacitances. As mentione earlier, the charge splitting techniques have been revise many a time, an have been classifie into two groups with respect to the bulk charges inclue in the moel [.7] for efficient MOSFET moeling. They are I. Depletion Charge Moel (DSM) II. Simplifie Charge Moel (SCM) In DCM, bulk charge is consiere to be proportional to the square root of a voltage, while SCM is a more simplifie DCM moel, with slight compromise in bulk to rain an bulk to source capacitances. Although charge-base moels provie an alternate way to moel MOSFET s, it was still not able to explain the charge non-conservation of the Meyer capacitance moel. Roots an Hughes [.8] in 1988 an Snier [.9] in 1995 suggeste a trans-capacitance moel, which came close in ientifying the conservation problem. ~14~

27 .3 TRANS-CAPACITIVE MODEL Roots an Hughes [.8] in 1988 an later Snier [.9] was able to explain the charge nonconservation of the Meyer capacitance moel using the concept of trans-capacitance. Accoring to them, a capacitive gate to source MOS elements that epens on both gate to source an gate to rain voltages woul transport a non-zero charge. They preicte the violation of charge conservation ue to the omission of recharging effect of capacitances an trie to compensate the charge by aing an extra element in the circuit an calle it a trans-capacitance element. Their moel conclue that: 1. Current equation V I = C alone oes not account for all the currents in MOS transistors t as capacitances are controlle by more than one source.. These capacitances appear to issipate energy if trans-capacitance terms are ignore. Figure.5: Trans-capacitance Approximation.4 MEHMET MODEL In 1989, Mehmet A. Cirit [.10] was able to show the root cause of charge non-conservation in the gate-capacitance moel propose by Meyer. He points out that the Meyer moel is a firstorer inaccurate approximation to MOS capacitances. Since the MOS capacitance is epenent on several variables, faults in the moeling of such an element causes the SPICE simulator to neglect non-linear first orer capacitive terms. Consiering the gate to source transient current equation i = C v gs gs t gs ~15~

28 its partial erivative gives i = C δv C V gs gs gs + δ gs gs. (.0) Since gate capacitance is epenent on gate to source, gate to rain an gate to bulk voltages, incluing these effects, equation (.0) can be moifie as δc δc δc V V gs V gs V gs δi = C δ gs + gs δv + gs δvg + gs δv (.1) gs gs δv gs δv δv gb gs g gb If α is 1/h, where h is the time interval, an voltage varies by an amount δv, the corresponing change in its time erivative V can be estimate asδ V = αδv. Substituting these values in equation (.1), equation (.1) can be rewritten as δc δc δc V gs V gs V gs δi = C αδv + gs δv + gs δvg + gs δv (.) gs gs δv gs δv δv gb gs g gb Similarly, gate to rain an gate to substrate current can be written as δc δc δc V g V g V g δi = C αδv + g δv + g δvg + g δv (.3) g g δv gs δv δv gb gs g gb δc δc δc V gb V gb V gb δi = C αδv + gb δv + gb δvg + gb δv (.4) gb gb δv gs δv δv gb gs g gb The first term in (.-.4) is frequency epenent, while rests of the terms are ue to non-linear capacitances an look like resistors in the channel. As circuit simulators only consiere the frequency epenent terms for circuit evaluation, Mehmet assume that this incomplete representation was the root cause of charge pumping in circuit simulators, an propose a moel to inclue ignore non-linear terms that cause an extra charge in the channel. ~16~

29 Figure.6: Small Signal Representation of Mehmet Moel Fig. 7 shows a small signal representation of Mehmet moel for C gs where δ C gs C = gsgs δv gs C gsg δc gs = δv g δ C gs C = (.5) gsgb δv gb δ C g C = ggs δv gs C gg δ C g = δv g δ C g C = (.6) ggb δv gb δ C gb C = gbgs δv gs C gbg δ C gb = δv g δ C gb C = (.7) gbgb δv gb Mehmet use this moel in the circuit simulator Lspice an observe the charge conservation. He conclue that the Meyer gate capacitance moel can be mae to conserve charge by consiering all first orer terms. He also pointe out that the substrate charges might be easily inclue in the Meyer capacitance moel to simulate the MOS evices more accurately. It shoul be note that in any MOSFET moel, charge or capacitance, the charge neutrality conition is built into the erivation [.11] an may seem unreasonable to come up with a charge non-conservation problem. Whichever moeling techniques are use, the main goal is to come up with an analytical escription of MOS evice behavior with emphasis on equations that are continuous in all regions of evice operation. ~17~

30 CHAPTER III III. FIRST ORDER QUASI-STATIC CHANNEL CAPACITANCE MODEL This chapter escribes the mathematical equations use to analyze the MOS transistor for the research work. The current continuity equations are presente without the channel charge partition to compute the steay state an ynamic current components. These currents then become the basis for I-V an C-V moels to be use in the circuit simulators. 3.1 STEADY STATE OPERATION In the steay state, the gate an substrate are assume to have no irect conuctive path to the channel. Leakage through the gate oxie as well as recombination current between the substrate an the channel are neglecte. Figure 3.1: BULK an SOI CMOS Structures It is very important that the boy charges are properly moele [3.1, 3., 3.3] an its effects are inclue for steay state an the transient simulations. These effects cause an uneven istribution of channel charge between the source an the rain regions, an the regions in between, which in turn causes uneven istribution of the gate an substrate charges. To moel all these skewe istributions, it will be convenient to escribe the charges by its ensity per unit length. Consiering only the intrinsic part of the MOS transistor, which is responsible for all the transistor action, the zero orer charge per unit length at the terminals can be written as ~18~

31 q = f( v, v ) where j = g, c (3.1) jb0 gb cb In terms of rift current, current flow in the evice can be seen ue to the transport of electrons from the source to the rain terminal. Taking steay state values, I = I (3.) c0 D I S = I (3.3) D I = 0 (3.4) G I = 0 (3.5) B where I c0 is the steay state channel current, which becomes I D at the rain en an I S at the source en. The steay state gate I G an substrate currents I B are zero as the transistors are assume to be leakage free. These terminal currents can be expresse as some function of terminal voltages an can be written as I = f( v, v, v, v ) (3.6) c0 D G S B 3. QUASI-STATIC OPERATION Equation (3.4) was calculate with the assumption that the terminal voltages were steay. In a real circuit, transistors operate uner ynamic conitions where terminal voltages are varying. To calculate the charge uner such conitions, quasi-static operations are assume. The voltages are allowe to vary slowly in quasi-static operation. Though the gate, substrate an the channel charges are still the functions of instantaneous voltages an can be represente using equation (3.1), however, the currents can not be preicte using equation (3.6). With similar assumption of leakage free gate oxie an negligible recombination current, the first orer gate (i g1 ) an substrate (i b1 ) currents are no longer zero. They are given at any location x along the channel by the gate (q g ) an bulk (q b ) charge ensities as: i ( x, t) q ( x, t) g = t g (3.7) ~19~

32 i ( x, t) q ( x, t) b = t b (3.8) In the quasi-static operation, even though the charge istribution in the channel remains the same, there exists a conucting path between the source an the rain terminals. Charge enters from the source terminal an leaves the rain terminal, which makes channel partition schemes misleaing to unerstan the evice physics. It is also challenging to represent the channel charge an compute the first orer source (i s1 ) an rain (i 1 ) terminal currents ue to two reasons: It is unrealistic to consier the charges in the channel as being partitione between source an rain an Charge reistribution causes extra issipation in the channel. The unrealistic partition can be resolve by solving for the total charge in the channel instea of separating it into source an rain charges. Fig. 3. shows a voltage, charge magnitue an current waveforms. The current waveforms show a pair of first orer components together with a steay state DC component. The origin of these first orer components not preicte by DC operation can be explaine using a test quasi-static voltage at the gate terminal. Figure 3.: Voltage, Charge an Current Waveforms ~0~

33 A rising input at the gate terminal from time t 0 to t 1 causes the first orer currents. Compare to first orer rain current (i 1 ), first orer source current (i s1 ) is more in this interval as more electrons are pumpe from the source terminal an fewer electrons are remove from the rain. Between the intervals t 1 to t, current settles into a steay state value of I c0. On the other han, for a falling waveform between the interval t to t 3, first orer rain current becomes more than the first orer source current as more electrons are sucke out from the rain terminal. These transients that show up uring the switching are also responsible for the channel charge reistribution, which in turn also contributes to power issipation. To properly analyze the MOS transistors an evelop C-V moels to be use in circuit simulators, we then nee to consier these first orer currents together with the steay state values. As mentione above, the charge reistribution also contributes to the power issipation, which suggests the presence of first orer issipative an conserve components. We have been able to ientify an separate out these components. This is explaine in etail in chapter 4 with erivations. 3.3 MODELING EQUATIONS In orer to obtain an analytical solution, the current flow is consiere in one imension parallel to the surface of the evice. The equations for both Bulk an SOI processes are evelope with some assumptions. The boy charge is assume to have square root epenence for the Bulk process, while the charge expressions for SOI MOSFET assumes that the region uner the channel is completely eplete of mobile charges. These simplifie assumptions helps us to make use of a linear relationship between the boy an the surface potential to compute the energy function without partitioning the channel charge. The linear boy-surface relation also provies a simplifie charge moel an terminal currents. It shoul be note that solving the moel involves complicate algebraic calculations that are practically impossible without moern mathematics tools like Mathematica [3.4]. ~1~

34 Figure 3.3: Four terminal (a) BULK NMOSFET an (b) SOI NMOSFET Structure Fig. 3.3 shows NMOS BULK an SOI transistors. The charge per unit length ( q c ) at a position x along the channel is given by q ( x) = c ( v v v ( x) φ + q ( x)/ c ) (3.9) c ox gb fb cb b ox Similarly, the bulk charge (back gate) per unit length ( q ) at x can be written as b c ( k + k v ( x)), SOI ox 1 cb q b ( x) = c ( k φ + ( 1)( ( ) )), ox 1 v + sb Abulk v cb x v sb BULK (3.10) where v fb, v gb an v cb are flat ban, gate an channel voltages with respect to the boy. Abulk [3.13] is the bulk charge coefficient, k 1 an k are boy effect coefficients. c = w( c / A) is the oxie capacitance per unit length an w is the channel with. The bulk ox ox charge is approximate using first two terms of Taylor s expansion aroun the source terminal v sb. The linear epenence of back gate for a fully eplete SOI MOSFET is inclue in the k 1 term. Charge conservation is insure by efining the gate charge per unit length qg as q = ( q + q ) (3.11) g b c It will be convenient to efine the channel charge per unit length at the source (x=0) q s an the rain (x=l) q an their time erivatives as q = c v an (3.1) s ox gst ~~

35 q = c v (3.13) t s ox t gst where v = v v v (3.14) gst gb t sb In equation (3.14), v t is the threshol voltage. The boy effect parameters are inclue by consiering the epenence of source terminal on the threshol voltage [3.5, 3.6] by efining v + k v, SOI t0 sb v ( v ) = t sb v + k ( φ+ v φ), BULK t0 1 sb (3.15) where v + k + φ, SOI fb 1 v = t 0 v + k φ + φ, BULK fb 1 (3.16) At the rain en, q = c v an ox gt (3.17) q = c v t ox t gt where (3.18) v v v (1 + k ) ( v v ), SOI gb t sb b sb v ( x) = gt v v v Abulk( v v ), BULK gb t sb b sb (3.19) It is assume that positive current flows into the rain an velocity saturation effects are neglecte. The erivative of Abulk with v sb is assume to be negligible. These assumptions are necessary for energy conservation [3.7] an simplifie capacitance equations [3.8]. Even though the equations are simplifie, accuracy is not significantly compromise [3.8]. The results are expecte to be accurate for a substrate reference system [3.9]. Drift current at a istance x along the channel can be written as i ( x, t) = q ( x, t) μ v ( x) (3.0) c c x cb Charge conservation is assure using the continuity equation i ( x, t) q ( x, t) x c = t c (3.1) ~3~

36 where q = q + q c c0 c1 In equation (3.1), q c 0 is a function of terminal voltages an q is a function of first orer time c 1 erivatives of terminal voltages. Using (3.0) in (3.1) gives [ q (,) x t v ()] x q (,) x t x c μ x cb = t c (3.) Taking the spatial erivatives of charge per unit length as a function of potential along the channel, equation (3.9) an (3.10) reuces to (1 + k ), SOI q ( x, t) = C v ( x); C = c K; K x c c x cb c ox = Abulk, BULK (3.3) Substituting v ( x ) x cb in (3.) an rearranging terms gives [ (, ) (, )] C q x t q x t = c q ( x, t) (3.4) x c x c μ t c Equation (3.4) can be solve iteratively to compute the current an the charge in the channel. In terms of the steay state (zero orer) charge per unit length at any position x along the channel, equation (3.4) reuces to ( q q ) = 0 (3.5) x c0 x c0 Performing integration from source(x=0) to rain (x=l), zero orer charge along the channel becomes q = ( q (1 x/ L) + q x/ L (3.6) c0 s an the steay state rift current component simplifies to μ I = q q (3.7) 0 C c0x c0 c Equation (3.7) gives the usual equation for static current neglecting velocity saturation, which is shown in Table 1. The first orer current an charge can be foun by keeping terms of first orer in time erivatives in equation (3.4) ~4~

37 C ( q q + q q ) = c q (3.8) x c0 x c1 c1x c0 μ t c0 Rearranging the terms, equation for the first orer channel charge simplifies to C 1 q = c ( ( q [ x ] x ) x ) c 1 x c 0 c1 + + (3.9) μ q t c0 c0 an the first orer channel current reuces to μ i = ( q q + q q ) (3.30) c1 C c0 x c1 c1x c0 c Finally, equation (3.30) can be solve to compute the first orer channel current at the source i s1 = i c1 (x=0) an the rain i 1 =- i s1 (x=l) ens in all regions of operation. We have assume pinch-off saturation which occurs when q = 0. The rain voltage at saturation can now be estimate by setting v ( x) = 0to get gt v gst v s K as a bounary between the linear an the saturation regions. In the cut-off, it is assume that the channel current is zero, which is mae possible by setting both the charge ensities q an q s to zero. Table 1 summarizes the charge an current in all regions of operations. These results obtaine without partitioning the channel charge are in agreement with Lim-Fossum [3.10] an the BSIM capacitive moel [3.11, 3.1] which were obtaine using War s [3.] partition. Therefore, we have verifie that War s partition is correct when the voltage epenence of Abulk is ignore. Table 3.1: NMOS Zero an First Orer Charges an Currents Linear Saturation Cut-Off Conitions q < 0 c q < 0 c q = 0 c v > 0 gt v = 0 gt v = 0 gt v gst > 0 v gst > 0 v gst = 0 q c v s c v 0 ox gst ox gst q c v 0 0 ox gt ~5~

38 I c 0 μc ox ( vgst vgt ) L(1 + k ) i s 1 coxl [ v ( )( 3 ) 3 gt vgt vgt + vgtvgst + vgst 15( v + v ) t gt gst + vgst ( vgst )(8vgt + 9vgtvgst + 3 vgst )] t i 1 cl ox [ v ( )(3 9 8 ) 3 gt vgt vgt + vgtvgst + vgst 15( v + v ) t gt gst t vgst ( vgst )( vgt 3 vgtvgst vgst )] μc ox v (1 L + k ) gst c L v 5 ox t gst 4 c L v 15 ox t gst ~6~

39 CHAPTER IV IV. MOSFET POWER This chapter iscusses the origin of MOS transistor leakage an escribes the power computation techniques for conserve an issipative components without the channel charge partition. The existence of an energy function is also valiate. The conserve an issipative power components then become the basis of conserve an issipative current components in chapter 5. The fast scaling of operation frequency for semiconuctor integrate circuits that was seen in the last few ecaes cannot continue. One of the reasons is the increase in power issipation. Power limits the scaling. The high power issipation ue to small evice geometry has thrown off course the roamap of future evelopment of semiconuctor technologies as preicte in the International Technology Roamap for Semiconuctors [4.1]. When the evices are switching rapily, the power issipation per unit area goes up causing excessive heating. Unless a sophisticate an expensive cooling system is implemente, the evice may no longer be operational. The reality is: we have reache a power limite scaling regime. Scaling now is no longer etermine by the evice size, but by how much power the chip can issipate at a particular working frequency. However, the lack of suitable evice moels to measure this power issipation has provie a plethora of research avenues. The conventional MOSFET moels have some inherent issues an are not consistent for power an energy preiction as they: Fail to inclue the first orer power issipation ue to channel charge reistribution, ~7~

40 Give a net non-zero power in the channel that has no physical basis from the terms that shoul be conserve. This makes the MOSFET moeling very important going forwar into the nanometer regime for low power esign techniques an power-aware architectures [4.3]. Given that the accuracy of the simulation epens on the physical representation of the evice, it is very important that we have a reliable mathematical moel that is able to represent the evice behavior. Designers nee these accurate moels for circuit evelopment. 4.1 SOURCES OF POWER DISSIPATION There are three sources of power issipation in the MOS transistor [ ]. The first source of power issipation is ue to the transistor switching that is relate to the charging an ischarging of the external loa capacitors. The secon source is from the short-circuit power ue to the current flow from the supply to the groun. These two issipations are relate to the transitions at the gate [4.7]. The thir source is the leakage power. Transistor scaling has reuce the threshol voltage an increase the gate leakage resulting in higher static power. Fig. 4.1 shows all these leakage sources that are taking up the power buget. Some of these sources have ominant effects on the transistor performance in the nano-meter regime [4.7, 4.8]. Figure 4.1: Leakage Current Components [4.5] ~8~

41 I1 I I3 I4 I5 I6 I7 I8 PN junctions reverse bias current Subthreshol leakage Drain Inuce barrier lowering Gate-Inuce rain leakage Punchthrough Narrow with effect Gate oxie tunneling Hot carrier injection 4. POWER AND ENERGY MODELING ISSUES Meyer [4.9] was the first to present a capacitive moel. War an Dutton [4.10] pointe out the assume charge non conservation problems in Meyer s moel. To solve these problems in transient simulation, they propose a charge partitioning scheme with a charge conservation constraint. Sheu et al. [4.11] an Chung [4.1] mae many improvements later to better erive I-V an C-V characteristics. One of the inustry stanars, the BSIM capacitive moel inclues many of these moels to estimate the behavior of MOS transistors. The BSIM moel assumes that the MOSFET capacitance is an energy storage evice an uses the conserve charges (to first orer) to preict the currents an voltages at ifferent noes. The same charge (to zero orer) is also use to preict the channel power. This makes the BSIM capacitive a zero orer, quasi-static power issipation moel. The moel Assumes that the first orer terms only contribute to energy storage Uses channel charge partition scheme an the bulk charge parameter has a non-linear epenence on the source potential. Both these ieas leave a lot to be esire. First, the issipative power has some higher orer terms ue to the charge reistribution. These higher orer issipative components become significant at higher frequencies an moify the total power issipate in the channel [4.13]. This is explaine later in section 4.5. Secon, the non-linear epenence of Abulk on v oes not sb ~9~

42 allow the erivation of energy function from all of the conserve components [Appenix A7.]. These effects causes the BSIM capacitive moel to preict a ifferent number for instantaneous power measure from the supply than the power issipate in the evice, clearly a violation of energy conservation principles. If an analytical close form solution for the store energy function is esire using non-reciprocal capacitors, the FET charge equation has to be solve for a linear source epenence of the bulk without the channel charge partition. These inconsistencies make the current BSIM capacitive moel non-ieal for energy estimation. 4.3 POWER MEASUREMENT TECHNIQUES Many moels have been suggeste for the estimation of power, like using supply current measurements [4.14], input slew epenency [4.15], propagation elay [4.16], short circuit power [4.17] an non-conventional capacitor-base methos [4.18] V DD I p t V in CMOS V out I n C L Figure 4.: Dynamic Power Fig 4. shows one of simplest techniques use to calculate the transistor power consumption. Power is consume when the gate rives the output Vout to a new value. Assuming that the input V in changes very fast, only one transistor turns on at a time. When the output goes high, the ~30~

43 current flows through the PFET an goes only to the capacitor. The current component that goes own the NFET has been neglecte. Similarly when the output settles to a low value, it is assume that the current goes through the NFET. Though the PFET is not quite turne off yet, the current that is coming through the PFET is neglecte. vin 0 T/ T t vout t Ip t In t Figure 4.3: Transient Waveforms Fig 4.3 shows the transient waveforms. The output looks more like a RC time constant ue to the presence of the capacitance, charging up the output from 0 to T/ an then ischarging from T/ to T. If we look at the corresponing current plots for falling input transient, it is only the PFET that is proviing the capacitor current I. For the rising input transient, capacitor current In is through p the NFET. It shoul be note that the currents mentione above are the magnitues of the rain current. The instantaneous power issipation is then calculate by solving for I an V an multiplying them together. It is also assume that the capacitors are purely energy storage evices an oes not contribute to net power issipation. Hence, uring the falling input transition, power issipation is only in the PFET. Similarly uring the rising input transition, power issipation is only in the NFET. Using these assumptions, the average power P c 0 for a complete cycle is compute using 1 T / T P [ I V t I V t ] c0 = T p DSp + (4.1) n DSn 0 T / ~31~

44 where V DSp an V DSn are the outputs at the PFET an NFET respectively. During the falling transition as PFET charges the capacitor, actual positive current flows from the evice to the capacitor. This makes the PFET rain current I negative. p Vout Ip = ( CL ) (4.) t where C is the output loa. The corresponing output voltage at the PFET, V L DSp becomes V = V V = ( V V ) (4.3) DSp out DD DD out where VDD is the supply voltage. From (4.) an (4.3), power issipate in the PFET, P PFET is compute using T / P = I V t (4.4) PFET p DSp 0 Similarly, the current through the NFET, I n is negative of the capacitive current. Vout In = ( CL ) (4.5) t an the corresponing output voltage, V DSn is V DSn = V (4.6) out From (4.5) an (4.6), power issipate in the NFET, P is given by NFET T P = I V t (4.7) NFET n DSn T / The average power, P c0 for a complete cycle is estimate using equations (4.4) an (4.7) as 1 P = [ P + P ] (4.8) c0 T PFET NFET Substituting In, Ip, VDSn an VDSp in equation (4.8), the average power equation reuces to 1 T / V T V P = [ C out ( V V ) t ( C out ) V t ] c0 + T L DD out (4.9) L out 0 t T / t ~3~

45 Because of the fact that the transistor currents are relate to the charging an ischarging of the currents of the capacitor, the power integrals can be replace from integrals over t to an integral over v. This gives a close form expression for the ynamic power inepenent of it () an vt (). P = f C V (4.10) c0 L DD There are, however, some issues in regars to the ynamic power equation (4.10). These issues are: The MOS channel is not purely an energy storage evice an has no energy function. For an energy function to exist, secon orer partials have to be equal. This is shown in the Appenix [A4.5-A4.7]. The MOS capacitors issipate power an the trans-capacitive terms use in the charge moel inclues both issipative an conserve components. Therefore, it is not appropriate to look at the change in the energy of the external loa capacitor C L in the channel as a true measure of power. Dynamic power preicte using equation (4.10) is in fact an easy way of computing the zero orer power by looking at the change in energy uring charging an ischarging of external capacitors. Fig. 4.4 shows another capacitor base technique use for power measurement. In this type of power measurement, switch S is close an the loa capacitor C L is allowe to attain the supply voltagev DD. The switch is then opene an the CMOS gate is allowe to unergo a transition. This causes some energy consumption in the circuit, which is capture by the measuring evice as a ecrease in supply voltage ( Δ v ). Energy issipate in the circuit can now be estimate using 1 1 Energy = C V C ( V Δ v) (4.11) L DD L DD 1 where C L Δv is the energy consume by the circuit. This metho of energy preiction is very accurate [4.18]. However, this energy preiction is not possible uring the esign phase. Hence, ~33~

46 there is a nee for a verification tool that can simulate the real worl behavior of the transistor uring the esign phase. V DD Switch S C L CMOS Measuring Device Figure 4.4: Capacitor base Power Measurement Technique This makes the next an subsequent sections of power erivation one of the most important finings of our research, where the energy function is erive from a symmetrical charge conserving FET moels. Before going through the erivation, it however, becomes important to iscuss the extra source of transistor power issipation that was not inclue in section 4.1. It also becomes important to check the valiity of the quasi-static approximation in the moel erivation. Figure 4.5: Power Dissipation in MOS Transistor When the gate unergoes a transition, from v ss to v or v to v ss, the resistive rop (IR) an the charge reistribution cause the power issipation in the channel. Usually, the zero orer steay state current is use to etermine the power issipation. The aitional power issipation from ~34~