Special Aspects on Non-Magnetic Current Sensing Techniques

Size: px

Start display at page:

Download "Special Aspects on Non-Magnetic Current Sensing Techniques"

Buck Garrett
6 years ago
Views:

1 pecial eminar Aspects ensors on in Non-Magnetic Power Electronics Current ensing Erlangen, March 2007 pecial Aspects on Non-Magnetic Current ensing Techniques Dr. Martin Maerz Department of Power Electronics ystems chottkystrasse 10, Erlangen Germany Tel. (+49) 9131/ , Fax

2 Content Current ense esistors (hunts) Application Hints Parasitic ense esistors 2

3 Current ense esistors Load (Force) Terminal Four-Wire Coaxial Two-Wire Verror Internal lead and terminal resistance Verror Load current ense (Kelvin) Terminal ense esistor ense (Kelvin) Terminal Internal lead and terminal resistance Load (Force) Terminal Typical Parameter ange Value: 100µW... 10W Tolerance: 0,5%... 5% TK: < 100 ppm/k 3

Pseudo Four-Wire Technique Bad Good Useful Good hunt 0xx hunt 0xx ense ense

Error due to voltage drop across the solder joints!

Note: 1mm variation in insert height of a leaded 10mW shunt can change the

4 Pseudo Four-Wire Technique Bad Good Useful Good hunt 0xx hunt 0xx ense ense eparate sense leads from the load current path! Error due to voltage drop across the solder joints! imulating a four-wire shunt by PCB-layout (load current free sense contacts) Note: 1mm variation in insert height of a leaded 10mW shunt can change the value by 1%! Any Cu-section in the load current path between the sense contacts considerably worsens the temperature coefficient! 4

5 ense esistor - Layout Hints I Load A low-inductive shunt is no guaranty for a low-noise measurement signal! B Avoid inductive coupling into the sense leads! Bad V ind ense leads Take care of capacitive currents on the sense leads in the presence of high dv/dt (common mode noise)! Good ense leads 5

ense esistor - Layout Hints Noise current on the sense leads I n C tot dv ( t) dt (1) dv dt C tot L a I n L b hunt signal conditioning circuit D bt C tot comprises the capacitances of signal coupler,

6 ense esistor - Layout Hints Noise current on the sense leads I n C tot dv ( t) dt (1) dv dt C tot L a I n L b hunt signal conditioning circuit D bt C tot comprises the capacitances of signal coupler, board layout, and the auxiliary power supply. Example I n V 10pF A nsec C tot may cause serious ringing in conjunction with L a/b. Control circuit An auxiliary power supply via bootstrap diode (D bt ) requires an especially careful circuit layout! 6

7 ense esistor - Layout Hints Pseudo Differential Measurement GND I 1 V 1 AGND + 2 V 2 V + 2 V 2 1 (2) 1 Choose the ground reference point carefully There must be no second current path between the load and sense ground otherwise danger of: uncontrollable ground current flow electro-magnetic coupling into the resulting ground loop high noise level unstable circuit operation 7

I [A] Voltage V [V] pecial Aspects on Non-Magnetic Current ensing ense esistor - Dynamic Characteristics Equivalent Circuit of a eal esistor Example L I V V I + L di

8 I [A] Voltage V [V] pecial Aspects on Non-Magnetic Current ensing ense esistor - Dynamic Characteristics Equivalent Circuit of a eal esistor Example L I V V I + L di ( t) dt Error Term (3) hunt: s = 20mW, L s = 10nH Current: 100nsec rise time, 200nsec fall time Voltage Current Time [nsec] 8

Current I [A] Voltage V 2 [mv] pecial Aspects on Non-Magnetic Current ensing ense esistor - Dynamic Characteristics Frequency Compensation L I 1 C V 2 For >> + sl the output voltage is: V 1 2 I

9 Current I [A] Voltage V 2 [mv] pecial Aspects on Non-Magnetic Current ensing ense esistor - Dynamic Characteristics Frequency Compensation L I 1 C V 2 For >> + sl the output voltage is: V 1 2 I becoming an all-pass for: L L 1 + s 1 + s C 1 1 C No Phase Delay! (4) (5) pf C 250 pf 500 pf Example 1000 pf Current s =20mW, L s =10nH, 1 =1kW, rise / fall time I s : 100 / 200 nsec Time [nsec]

10 Content Current ense esistors (hunts) Application Hints Parasitic ense esistors 10

11 Parasitic Current ensing esistors Example : Lead esistance : Inductor E 1) : Capacitor E : Power emiconductor Characteristics C 1 T D L C 2 Attractiveness No extra current sensor cost effective No additional power dissipation 1) Effective eries esistance 11

Parasitic Current ensing esistors Conductors d w Conductor resistance 1 d M l w l (6) M : specific

the electrical conductivity of common conductor metals (Cu, Al) (e.g.

resistor values require large l / w ratios, making low-inductive designs quite difficult

12 Parasitic Current ensing esistors Conductors d w Conductor resistance 1 d M l w l (6) M : specific conductivity ( Cu /mm) Cu trace 35µm: 0,5 mω l w Problems High temperature coefficient of the electrical conductivity of common conductor metals (Cu, Al) (e.g. Cu: +40% at 100K temperature rise) Limited accuracy due to geometric tolerances Useful sense resistor values require large l / w ratios, making low-inductive designs quite difficult Applications hort circuit and over-load protection Used in current sense ICs like UCC3926, LM3812 or LM3822 in form of leadframe resistors 12

13 Parasitic Current ensing esistors Inductor E 1 V C C Choosing L E 1 C (8) results in a I L L E capacitor voltage that is a direct image of the voltage drop across the inductors series resistor! Example For 1 >> E + sl the capacitor C is: V C I L E the voltage across L 1+ s 1+ s C E 1 (7) Inductor with L = 2µH, E = 10mW An all-pass is obtained with C = 1 = 10kW Practical Limitations due to a more complex frequency response of real inductors (winding capacitance, etc.) current depending inductance (core saturation) 13

14 Parasitic Current ensing esistors Inductor E I L Imaging the Average Inductor Current 1 L E Advantages Inexpensive No adjustment of time constants Measured value depends only on E C I L V C VC V E out (9) V out Applications»Average current mode control«current balancing in multi-phase converters Overcurrent protection 14

15 Drain Current Normalized ON-esistance pecial Aspects on Non-Magnetic Current ensing Parasitic Current ensing esistors MOFET ( ON ) 2x I nom MOFET Output Characteristic V G = V ON-esistance vs. Chip Temperature High-voltage 1.6 I nom V G = 4V Low-voltage MOFET V G = 3V Drain-ource Voltage [V] With high gate-source voltages linear (ohmic) output characteristic up to nearly two times the nominal current Junction Temperature [ C] ON-esistance heavily dependent on temperature. 15

Parasitic Current ensing esistors MOFET ( ON ) Circuit example I D 2 V Is D( on) ID (10) 1 V D Advantage V Is 1 I Is 2 No extra sensor element (cost effective) No

16 Parasitic Current ensing esistors MOFET ( ON ) Circuit example I D 2 V Is D( on) ID (10) 1 V D Advantage V Is 1 I Is 2 No extra sensor element (cost effective) No additional power dissipation Positiv temperature coefficient of the D(on) can provide an inherent power derating and auto-balancing Disadvantage Poor absoute accuracy 16

17 ense-mofet Virtual Ground Method Typical Measuring Error ense-mofet cell number D I ense I OUT aising offset influence G N 1 N 2 ense typ. ± % I I ense out N N 1 2 PMO I ense _ + I OUT Load 0 Applications I nom I OUT V ense Load current monitoring Overcurrent and short circuit protection 17

18 ense-mofet Ground esistor Method Load 2 I Load (11) D ( on) ense-mofet N1 D D(on) : ON-esistance of the main MOFET Cell number Choose the ground resistor according to N G N 1 N 2 ense V ense I ense since higher sense resistance values change the sense ratio away from the geometric ratio towards a gate voltage and temperature dependent effective sense ratio, introduce an additional temperature dependancy, but also provide a higher sense voltage. 18

19 Literature [1] Lenk,.: Optimum Current ensing Techniques in CPU Converters. Application Bulletin AB-20, Fairchild emiconductors, 1999 [2] Zho X., et al.: A Novel Current-haring Control Technique for Low-Voltage High-Current Voltage egulator Module Applications. IEEE Trans. Power Electronics, vol. 15, 2000, pp [3] Yuvarajan.: Performance Analysis and ignal Processing in a Current ensing MOFET. Proc. Industry Applications ociety Annual Meeting, vol. 2, 1990, pp [4] Forghani-zadeh H.P., et al.: Current-ensing Techniques for DC/DC Converters. ource: Internet [5] Kandarp P.: Current-ensing Power MOFET. Application Note AN-606, VIHAY iliconix, 2002 [6] Mammano B.: Current ensing olutions for Power upply Designers. Power upply Design eminar, EM-1200, 1997, pp. 1-1 to 1-34 [7] IA-PLAN -Präzisionswiderstände. Datenbuch, Isabellenhütte GmbH KG, Dillenburg, 1996 [8] Dallago E., assone G.: High-frequency current transducers in a control system for quasiresonant power converters. IEE Proc.-ci. Meas. Technol., vol. 142, no. 3, 1995, pp

Rg2 Lg2 Rg6 Lg6 Rg7 Lg7. PCB Trace & Plane. Figure 1 Bypass Decoupling Loop

Rg2 Lg2 Rg6 Lg6 Rg7 Lg7. PCB Trace & Plane. Figure 1 Bypass Decoupling Loop TECHNICAL NOTE This article was originally published in 1996. INTRODUCTION In order to guarantee better performance from highspeed digital integrated circuits (ICs), manufacturers are tightening power