EECE488: Analog CMOS Integrated Circuit Design. Set 2: Background

Size: px

Start display at page:

Download "EECE488: Analog CMOS Integrated Circuit Design. Set 2: Background"

Jonah Horn
5 years ago
Views:

1 EECE488: Analo CMOS Interated Circuit esin Set : Backround Shahriar Mirabbasi epartent of Electrical and Coputer Enineerin Uniersity of British Colubia shahriar@ece.ubc.ca Technical contributions of Pedra ajeardi in reisin the slides is reatly acknowleded. EECE 488 Set : Backround

2 Oeriew. Readin Assinents. Structure of MOS Transistors 3. Threshold oltae 4. on-channel Current Equations 5. Reions of Operation 6. Transconductance 7. Second-Order Effects 8. Short-Channel Effects 9. MOS ayout 0. eice Capacitances. Sall-sinal Models.Circuit Ipedance 3. Equialent Transconductance EECE 488 Set : Backround

3 Readin Assinents Readin: Chapter of the textbook Section 6. of the textbook Chapter 7 All the fiures in the lecture notes are esin of Analo CMOS Interated Circuits, McGraw-Hill, 00, unless otherwise noted. EECE 488 Set : Backround 3

4 Transistor stands for Transistor Transistor are seiconductor deices that can be classified as Bipolar Junction Transistors (BJTs) Field Effect Transistors (FETs) epletion-mode FETs or (e.., JFETs) Enhanceent-Mode FETs (e.., MOSFETs) EECE 488 Set : Backround 4

5 Siplistic Model MOS transistors hae three terinals: Gate, Source, and rain The oltae of the Gate terinal deterines the type of connection between Source and rain (Short or Open). Thus, MOS deices behae like a switch G hih G low NMOS eice is ON is shorted to S eice is OFF & S are disconnected PMOS eice is OFF & S are disconnected eice is ON is shorted to S EECE 488 Set : Backround 5

Physical Structure - Source and rain terinals

rain, Gate, Substrate (bulk) Microelectronic

6 Physical Structure - Source and rain terinals are identical except that Source proides chare carriers, and rain receies the. MOS deices hae in fact 4 terinals: Source, rain, Gate, Substrate (bulk) Microelectronic Circuits, 004 Oxford Uniersity Press EECE 488 Set : Backround 6

7 Physical Structure - Chare Carriers are electrons in NMOS deices, and holes in PMOS deices. Electrons hae a hiher obility than holes So, NMOS deices are faster than PMOS deices We rather to hae a p-type substrate?! : ue to Side iffusion Poly-silicon used instead of Metal for fabrication reasons Actual lenth of the channel ( eff ) is less than the lenth of ate EECE 488 Set : Backround 7

8 Physical Structure - 3 N-wells allow both NMOS and PMOS deices to reside on the sae piece of die. As entioned, NMOS and PMOS deices hae 4 terinals: Source, rain, Gate, Substrate (bulk) In order to hae all PN junctions reerse-biased, substrate of NMOS is connected to the ost neatie oltae, and substrate of PMOS is connected to the ost positie oltae. EECE 488 Set : Backround 8

9 MOS transistor Sybols: Physical Structure - 4 electron In NMOS eices: Source rain Current flows fro rain to Source hole In PMOS eices: Source rain Current flows fro Source to rain Current flow deterines which terinal is Source and which one is rain. Equialently, source and drain can be deterined based on their relatie oltaes. EECE 488 Set : Backround 9

10 Threshold oltae - Consider an NMOS: as the ate oltae is increased, the surface under the ate is depleted. If the ate oltae increases ore, free electrons appear under the ate and a conductie channel is fored. (a) An NMOS drien by a ate oltae, (b) foration of depletion reion, (c) onset of inersion, and (d) channel foration As entioned before, in NMOS deices chare carriers in the channel under the ate are electrons. EECE 488 Set : Backround 0

Threshold oltae - Intuitiely, the threshold oltae is the ate oltae that forces the interface (surface under the ate) to be copletely depleted of chare (in NMOS the interface is as uch n-type as the

11 Threshold oltae - Intuitiely, the threshold oltae is the ate oltae that forces the interface (surface under the ate) to be copletely depleted of chare (in NMOS the interface is as uch n-type as the substrate is p-type) Increasin ate oltae aboe this threshold (denoted by or t ) induces an inersion layer (conductie channel) under the ate. Microelectronic Circuits, 004 Oxford Uniersity Press EECE 488 Set : Backround

12 Threshold oltae - 3 Analytically: Where: Φ Φ MS F Q C dep ox Φ MS Built - in Potential Φ ate Φ Silicon the difference between the work functions of the polysilicon ate and the silicon substrate Φ F Work Function (electrostatic potential) K T q ln N n sub i Q dep Chare in the depletion reion 4 q ε si Φ F N sub EECE 488 Set : Backround

13 Threshold oltae - 4 In practice, the natie threshold alue ay not be suited for circuit desin, e.., ay be zero and the deice ay be on for any positie ate oltae. Typically threshold oltae is adjusted by ion iplantation into the channel surface (dopin P-type aterial will increase of NMOS deices). When S is zero, there is no horizontal electric field present in the channel, and therefore no current between the source to the drain. When S is ore than zero, there is soe horizontal electric field which causes a flow of electrons fro source to drain. EECE 488 Set : Backround 3

14 on Channel Current Equations - The oltae of the surface under the ate, (x), depends on the oltaes of Source and rain. If S is zero, S (x). The chare density Q d (unit C/) is unifor. Q d Q C ( C W) ( ) ox Q d WC ox ( ) If S is not zero, the channel is tapered, and (x) is not constant. The chare density depends on x. Q d ( x) WC ox ( ( x) ) EECE 488 Set : Backround 4

15 Current : on Channel Current Equations - 3 dq dq dx I Q dt dx dt elocity in ters of (x): elocity µ E, d d ( x) elocity ( µ ) dx Q d in ters of (x): Q d I x 0 E elocity d dt ( x) WC ox ( ( x) ) Current in ters of (x): I I WC dx µ C n d ( x) [ ( x) ] µ n dx S WC 0 ox W ox [( µ [ on-channel current equation: ox n ( x) ) S S Microelectronic Circuits, 004 Oxford Uniersity Press ] ] d EECE 488 Set : Backround 5

16 on Channel Current Equations - 4 If S - we say the deice is operatin in triode (or linear) reion. Current in Triode Reion: I µ n C ox W ( ) S S Terinoloy: W Aspect Ratio Oerdrie oltae Effectie oltae eff EECE 488 Set : Backround 6

17 on Channel Current Equations - 5 For ery sall S (deep Triode Reion): I can be approxiated to be a linear function of S. The deice resistance will be independent of S and will only depend on eff. The deice will behae like a ariable resistor If S I R << ON ( ) n I µ C S ox W µ C n : ( ) ox W S ( ) EECE 488 Set : Backround 7

18 on Channel Current Equations - 6 Increasin S causes the channel to acquire a tapered shape. Eentually, as S reaches the channel is pinched off at the drain. Increasin S aboe has little effect (ideally, no effect) on the channel s shape. Microelectronic Circuits, 004 Oxford Uniersity Press When S is ore than the channel is pinched off, and the horizontal electric field produces a current. EECE 488 Set : Backround 8

19 on Channel Current Equations - 7 If S >, the transistor is in saturation (actie) reion, and the channel is pinched off. ' ' I x 0 I dx µ nc WC 0 ox ox W ( ' µ [ n ) ( x) ] d et s, for now, assue that. The fact that is not equal to is a second-order effect known as channel-lenth odulation. Since I only depends on, MOS transistors in saturation can be used as current sources. EECE 488 Set : Backround 9

20 on Channel Current Equations - 8 Current Equation for NMOS: I I S 0 ; if µ n Cox µ n Cox µ n C W W ox < ( Cut off ) ( ) S ; if [( ) ] S S W ( ) ; if > > ; if,, S S << > > (, S < ) ( eep Triode) ( Saturation ) ( Triode) EECE 488 Set : Backround 0

21 on Channel Current Equations - 9 Current Equation for PMOS: I I S 0 ; if µ p Cox µ p Cox µ p C SG W W ox < ( Cut off ) ( SG ) S ; if SG [( ) ] SG S S W ( SG ) ; if SG > > ; if,, SG S S > << > SG (, SG S < SG ) ( eep Triode) ( Saturation ) ( Triode) EECE 488 Set : Backround

the current throuh the channel is alost constant.

22 Reions of Operation - Reions of Operation: Cut-off, triode (linear), and saturation (actie or pinch-off) Microelectronic Circuits, 004 Oxford Uniersity Press Once the channel is pinched off, the current throuh the channel is alost constant. As a result, the I- cures hae a ery sall slope in the pinch-off (saturation) reion, indicatin the lare channel resistance. EECE 488 Set : Backround

23 Reions of Operation - The followin illustrates the transition fro pinch-off to triode reion for NMOS and PMOS deices. For NMOS deices: If increases ( G Const.), the deice will o fro Triode to Pinch-off. If G increases ( Const.), the deice will o fro Pinch-off to Triode. ** In NMOS, as G increases the deice will o fro Triode to Pinch-off. For PMOS deices: If decreases ( G Const.), the deice will o fro Triode to Pinch-off. If G decreases ( Const.), the deice will o fro Pinch-off to Triode. ** In PMOS, as G increases the deice will o fro Pinch-off to Triode. EECE 488 Set : Backround 3

24 NMOS Reions of Operation: Reions of Operation - 3 Microelectronic Circuits, 004 Oxford Uniersity Press Relatie leels of the terinal oltaes of the enhanceent-type NMOS transistor for different reions of operation. EECE 488 Set : Backround 4

25 PMOS Reions of Operation: Reions of Operation - 4 Microelectronic Circuits, 004 Oxford Uniersity Press The relatie leels of the terinal oltaes of the enhanceent-type PMOS transistor for different reions of operation. EECE 488 Set : Backround 5

26 Reions of Operation - 5 Exaple: For the followin circuit assue that 0.7. When is the deice on? What is the reion of operation if the deice is on? Sketch the on-resistance of transistor M as a function of G. EECE 488 Set : Backround 6

27 Transconductance - The drain current of the MOSFET in saturation reion is ideally a function of ate-oerdrie oltae (effectie oltae). In reality, it is also a function of S. It akes sense to define a fiure of erit that indicates how well the deice conerts the oltae to current. Which current are we talkin about? What oltae is in the desiner s control? What is this fiure of erit? I S Const. EECE 488 Set : Backround 7

28 Transconductance - Exaple: Plot the transconductance of the followin circuit as a function of S (assue b is a constant oltae). Transconductance in triode: µ n C W Transconductance in saturation: n µ C n ox µ C ox ox W S µ n C [ ( ) ] S S ( ) ox W ( W ) S S Const. Const. Moral: Transconductance drops if the deice enters the triode reion. EECE 488 Set : Backround 8

29 Transconductance - 3 Transconductance,, in saturation: W µ n Cox ( ) µ n C ox W I I If the aspect ratio is constant: depends linearly on ( - ). Also, depends on square root of I. If I is constant: is inersely proportional to ( - ). Also, depends on square root of the aspect ratio. If the oerdrie oltae is constant: depends linearly on I. Also, depends linearly on the aspect ratio. EECE 488 Set : Backround 9

30 Second-Order Effects (Body Effect) Substrate oltae: So far, we assued that the bulk and source of the transistor are at the sae oltae ( B S ). If B > s, then the bulk-source PN junction will be forward biased, and the deice will not operate properly. If B < s, the bulk-source PN junction will be reerse biased. the depletion reion widens, and Q dep increases. will be increased (Body effect or Backate effect). It can be shown that (what is the unit for γ?): 0 γ Φ F SB Φ F where γ q ε C si ox N sub EECE 488 Set : Backround 30

31 Body Effect - Exaple: Consider the circuit below (assue the transistor is in the actie reion): If body-effect is inored, will be constant, and I will only depend on in - out. Since I is constant, in - out reains constant. in out C Const. in out C Conts. In eneral, I depends on - in - out - (and with body effect is not constant). Since I is constant, in - out - reains constant: in out in out C Const. in out C As out increases, SB increases, and as a result increases. Therefore, in - out Increases. No Body Effect With Body Effect EECE 488 Set : Backround 3

32 Body Effect - 3 Exaple: For the followin Circuit sketch the drain current of transistor M when X aries fro - to 0. Assue 0 0.6, γ0.4 /, and Φ F 0.7. EECE 488 Set : Backround 3

33 Channel enth Modulation - When a transistor is in the saturation reion ( S > ), the channel is pinched off. W The drain current is I µ n Cox ( ) where ' - ' ' Assuin we et: ( ) ' λ S ( ) ( λ S ) The drain current is I µ C ( ) µ C ( ) ( λ ) W W n ox n ox ' As I actually depends on both and S, MOS transistors are not ideal current sources (why?). S EECE 488 Set : Backround 33

34 Channel enth Modulation - λ represents the relatie ariation in effectie lenth of the channel for a ien increent in S. For loner channels λ is saller, i.e., λ / Transconductance: I S Const. In Triode: µ C n ox W S In Saturation (inorin channel lenth odulation): µ C n ox W ( ) µ n C In saturation with channel lenth odulation: ox W I I µ C n ox W W ( ) S n ox λ ( λ ) µ C I ( ) The dependence of I on S is uch weaker than its dependence on. S I EECE 488 Set : Backround 34

35 Exaple: Channel enth Modulation - 3 Gien all other paraeters constant, plot I - S characteristic of an NMOS for and In Triode Reion: W I µ n Cox I Therefore : S [( ) S S] W In Saturation Reion: W I µ ncox So we et : I W µ ncox S Therefore : I W λ W S ( ) ( λ ) S ( ) λ Chanin the lenth of the deice fro to will flatten the I - S cures (slope will be diided by two in triode and by four in saturation). Increasin will ake a transistor a better current source, while deradin its current capability. Increasin W will iproe the current capability. EECE 488 Set : Backround 35

36 Sub-threshold Conduction If <, the drain current is not zero. The MOS transistors behae siilar to BJTs. In BJT: I C I S e BE T In MOS: I I 0 e ζ T As shown in the fiure, in MOS transistors, the drain current drops by one decade for approxiately each 80 of drop in. In BJT deices the current drops faster (one decade for approxiately each 60 of drop in ). This current is known as sub-threshold or weak-inersion conduction. EECE 488 Set : Backround 36

37 CMOS Processin Technoloy Top and side iews of a typical CMOS process EECE 588 Set : Introduction and Backround 37

38 CMOS Processin Technoloy ifferent layers coprisin CMOS transistors EECE 588 Set : Introduction and Backround 38

39 Photolithoraphy (ithoraphy) Used to transfer circuit layout inforation to the wafer EECE 588 Set : Introduction and Backround 39

40 Typical Fabrication Sequence 40

41 Self-Alined Process Why source and drain junctions are fored after the ate oxide and polysilicon layers are deposited? EECE 588 Set : Introduction and Backround 4

42 Oxide spacers and silicide Back-End Processin EECE 588 Set : Introduction and Backround 4

43 Back-End Processin Contact and etal layers fabrication EECE 588 Set : Introduction and Backround 43

44 Back-End Processin are contact areas should be aoided to iniize the possibility of spikin EECE 588 Set : Introduction and Backround 44

45 MOS ayout - It is beneficial to hae soe insiht into the layout of the MOS deices. When layin out a desin, there are any iportant paraeters we need to pay attention to such as: drain and source areas, interconnects, and their connections to the silicon throuh contact windows. esin rules deterine the criteria that a circuit layout ust eet for a ien technoloy. Thins like, iniu lenth of transistors, iniu area of contact windows, EECE 488 Set : Backround 45

46 MOS ayout - Exaple: Fiures below show a circuit with a suested layout. The sae circuit can be laid out in different ways, producin different electrical paraeters (such as different terinal capacitances). EECE 488 Set : Backround 46

47 eice Capacitances - The quadratic odel deterines the C behaior of a MOS transistor. The capacitances associated with the deices are iportant when studyin the AC behaior of a deice. There is a capacitance between any two terinals of a MOS transistor. So there are 6 Capacitances in total. The Capacitance between rain and Source is neliible (C S 0). These capacitances will depend on the reion of operation (Bias alues). EECE 488 Set : Backround 47

48 eice Capacitances - The followin will be used to calculate the capacitances between terinals:. Oxide Capacitance: C W C ox,. epletion Capacitance: 3. Oerlap Capacitance: C C dep W o C ox ε t si ox ox q ε N 4 Φ ox F sub C C C W C C 3 4 frine 4. Junction Capacitance: Sidewall Capacitance: C jsw Botto-plate Capacitance: C j C jun C j0 Φ R B C 5 C 6 C j C jsw EECE 488 Set : Backround 48

49 eice Capacitances - 3 In Cut-off:. C : is equal to the oerlap capacitance.. C G : is equal to the oerlap capacitance. Co C 3 3. C GB : is equal to C ate-channel C in series with C channel-bulk C. C C G Co C 4 4. C SB : is equal to the junction capacitance between source and bulk. 5. C B : is equal to the junction capacitance between source and bulk. C SB C 5 C B C 6 EECE 488 Set : Backround 49

50 eice Capacitances - 4 In Triode: The channel isolates the ate fro the substrate. This eans that if G chanes, the chare of the inersion layer are supplied by the drain and source as lon as S is close to zero. So, C is diided between ate and drain terinals, and ate and source terinals, and C is diided between bulk and drain terinals, and bulk and source terinals.. C :. C G : C C C o 3. C GB : the channel isolates the ate fro the substrate. 4. C SB : 5. C B : C C C G o C C SB C5 C C B C6 C GB 0 EECE 488 Set : Backround 50

51 In Saturation: eice Capacitances - 5 The channel isolates the ate fro the substrate. The oltae across the channel aries which can be accounted for by addin two equialent capacitances to the source. One is between source and ate, and is equal to two thirds of C. The other is between source and bulk, and is equal to two thirds of C.. C :. C G : C C o C C C 3 3. C GB : the channel isolates the ate fro the substrate. 4. C SB : 5. C B : G C o CSB C 5 C B C 6 C 3 C GB 0 EECE 488 Set : Backround 5

52 eice Capacitances - 6 In suary: Cut-off Triode Saturation C C o C C o Co C 3 C G Co C C o Co C C C GB CGB C 0 0 C C C C C SB C 5 5 C C 5 3 C B C 6 C C 6 C 6 EECE 488 Set : Backround 5

53 Iportance of ayout Exaple (Folded Structure): Calculate the ate resistance of the circuits shown below. Folded structure: ecreases the drain capacitance ecreases the ate resistance Keeps the aspect ratio the sae EECE 588 Set : Introduction and Backround 53

54 Passie eices Resistors EECE 588 Set : Introduction and Backround 54

55 Passie eices Capacitors: EECE 588 Set : Introduction and Backround 55

56 Passie eices Capacitors EECE 588 Set : Introduction and Backround 56

57 Passie eices Inductors EECE 588 Set : Introduction and Backround 57

58 atch-up ue to parasitic bipolar transistors in a CMOS process EECE 588 Set : Introduction and Backround 58

59 Sall Sinal Models - Sall sinal odel is an approxiation of the lare-sinal odel around the operation point. In analo circuits ost MOS transistors are biased in saturation reion. In eneral, I is a function of, S, and BS. We can use this Taylor series approxiation: Taylor Expansion : I I 0 I I S BS second order ters S BS I S I S I BS I BS I r o S b BS EECE 488 Set : Backround 59

60 Sall Sinal Models - Current in Saturation: Taylor approxiation: Partial eriaties: ( ) ( ) S ox n ox n W C W C I λ µ µ ) ( ' BS BS S S I I I I ( ) S ox n W C I λ µ ) ( 60 EECE 488 Set : Backround ( ) b SB F SB F S ox n BS BS o ox n S W C I I r I W C I Φ Φ η γ γ λ µ λ λ µ ) ( ) (

61 Sall-Sinal Model: Sall Sinal Models - 3 i r S Ters, and b BS, can be odeled by dependent sources. These ters hae the sae polarity: increasin G, has the sae effect as increasin B. The ter, S /r o can be odeled usin a resistor as shown below. o b BS EECE 488 Set : Backround 6

62 Sall Sinal Models - 4 Coplete Sall-Sinal Model with Capacitances: Sall sinal odel includin all the capacitance akes the intuitie (qualitatie) analysis of een a few-transistor circuit difficult! Typically, CA tools are used for accurate circuit analysis For intuitie analysis we try to find a siplest odel that can represent the role of each transistor with reasonable accuracy. EECE 488 Set : Backround 6

63 Circuit Ipedance - It is often useful to deterine the ipedance of a circuit seen fro a specific pair of terinals. The followin is the recipe to do so:. Connect a oltae source, X, to the port.. Suppress all independent sources. 3. Measure or calculate I X. R X I X X EECE 488 Set : Backround 63

64 Exaple: Circuit Ipedance - Find the sall-sinal ipedance of the followin current sources. We draw the sall-sinal odel, which is the sae for both circuits, and connect a oltae source as shown below: i X R r X X o i X X r o r X o EECE 488 Set : Backround 64

65 Circuit Ipedance - 3 Exaple: Find the sall-sinal ipedance of the followin circuits. We draw the sall-sinal odel, which is the sae for both circuits, and connect a oltae source as shown below: 65 EECE 488 Set : Backround b o b o X X X X b X o X BS b o X X r r i R r r i

66 Circuit Ipedance - 4 Exaple: Find the sall-sinal ipedance of the followin circuit. This circuit is known as the diode-connected load, and is used frequently in analo circuits. We draw the sall-sinal odel and connect the oltae source as shown below: 66 EECE 488 Set : Backround o o X X X o X X o X o X X r r i R r r r i If channel lenth odulation is inored (r o ) we et: o X r R

67 Circuit Ipedance - 5 Exaple: Find the sall-sinal ipedance of the followin circuit. This circuit is a diode-connected load with body effect. b X X b X o X BS b o X X r r i 67 EECE 488 Set : Backround b o b o b o X X X b o X r r r i R r If channel lenth odulation is inored (r o ) we et: b b b b o X r R

68 Equialent Transconductance - Recall that the transconductance of a transistor was a a fiure of erit that indicates how well the deice conerts a oltae to current. I S Const. It is soeties useful to define the equialent transconductance of a circuit as follows: I OUT G Const. IN OUT The followin is a sall-sinal block diara of an arbitrary circuit with a Norton equialent at the output port. We notice that: OUT Constant so OUT 0 in the sall sinal odel. G i OUT IN OUT 0 EECE 488 Set : Backround 68

69 Exaple: Equialent Transconductance - Find the equialent transconductance of an NMOS transistor in saturation fro its sall-sinal odel. i OUT G i OUT IN IN EECE 488 Set : Backround 69

70 Equialent Transconductance - 3 Exaple: Find the equialent transconductance of the followin circuit when the NMOS transistor in saturation. 70 EECE 488 Set : Backround ( ) ( ) S S b S O O O O S S b S IN OUT IN O S S b S OUT O S OUT S OUT b S OUT IN O S BS b OUT S OUT S IN R R R r r r r R R R i G r R R R i r R i R i R i r i R i ) (

71 Short-Channel Effects Threshold Reduction rain-induced barrier lowerin (IB) Mobility deradation elocity saturation Hot carrier effects Substrate current Gate current Output ipedance ariation EECE 488 Set : Backround 7

72 Threshold oltae ariation in Short Channel eices The Threshold of transistors fabricated on the sae chip decreases as the channel lenth decreases. Intuitiely, the extent of depletion reions associated with drain and source in the channel area, reduces the iobile chare that ust be iaed by the chare on the ate. EECE 488 Set : Backround 7

73 rain-induced Barrier owerin (IB) When the channel is short, the drain oltae increases the channel surface potential, lowerin the barrier to flow chare fro source (think of increased electric field) and therefore, decreasin the threshold. EECE 488 Set : Backround 73

74 Effects of elocity Saturation ue to drop in obility at hih electric fields (a) Preature drain current saturation and (b) reduction in EECE 488 Set : Backround 74

75 Hot Carrier Effects Short channel deices ay experience hih lateral drain-source electric field Soe carriers that ake it to drain hae hih elocity (called hot carriers) Hot carriers ay hit silicon atos at hih speed and cause ipact ionization The resultin electron and holes are absorbed by the drain and substrate causin extra drain-substrate current Really hot carriers ay be injected into ate oxide and flow out of ate causin ate current! EECE 488 Set : Backround 75

76 Output Ipedance ariation Recall the definition of λ. EECE 488 Set : Backround 76

77 Output Ipedance ariation in Short-Channel eices EECE 488 Set : Backround 77

EECE488: Analog CMOS Integrated Circuit Design. Introduction and Background

EECE488: Analog CMOS Integrated Circuit Design. Introduction and Background EECE488: Analo CMOS Interated Circuit Desin Introduction and Backround Shahriar Mirabbasi Departent of Electrical and Coputer Enineerin University of British Colubia shahriar@ece.ubc.ca Technical contributions