EE 330 Lecture 33. Basic amplifier architectures Common Emitter/Source Common Collector/Drain Common Base/Gate. Basic Amplifiers

Transcription

1 33 Lecture 33 asic aplifier architectures oon itter/source oon ollector/drain oon ase/gate asic plifiers nalysis, Operation, and Desin

2 xa 3 Friday pril 3

3 eview Previous Lecture Two-Port quivalents of Interconnected Two-ports i i y y 2 2 y 2 y 22 2 XX I I Two Port (Norton) i v H-paraeters (Hybrid Paraeters) h i h2 v2 h2 i h22 v 2 i2 v2 Linear Two Port I I 2 IN OUT 2 2 Two Port (Thevenin) pply, open 2 to et but short 2 to et IN pply 2, open to et but short to et OUT

4 eview Previous Lecture ircuit analysis steps Lare sinal Q-point analysis Open cap, short inductors ssue operation reions for active devices eplace each nonlinear device by its siplified piecewise linear odel opute Q-point: node voltaes and device currents erify assued reion Sall sinal D analysis Short D -source, open D I-source Short couplin caps eplace each nonlinear device by its ss odel Perfor standard linear analysis as in 2

5 eview Previous Lecture asic plifier Structures D G S Sall Sinal Transistor Models as 3-terinal Devices MOS oon Input Output JT oon Input Output oon Source or oon itter oon Gate or oon ase oon Drain or oon ollector S G D G S D D G S Objectives in Study of asic plifier Structures. Obtain key properties of each basic aplifier 2. Develop ethod of desinin aplifiers with specific characteristics usin basic aplifier structures

6 eview Previous Lecture The three basic aplifier types for both MOS and bipolar processes oon itter oon Source oon ase oon Gate oon ollector oon Drain Will focus on the perforance of the bipolar structures and then obtain perforance of the MOS structures by observation

7 Two-Port Models of asic plifiers widely used for nalysis and Desin of plifier ircuits Methods of Obtainin plifier Two-Port Network i in v2 o v 2. TST : i TST Method (considered in last lecture) 2. Write : 2 equations in standard for = i + IN 2 = i O 3. Thevenin-Norton Transforations 4. d Hoc pproaches ny of these ethods can be used to obtain the two-port odel

8 test : itest Method for Obtainin Two-Port plifier Paraeters SUMMY fro PIOUS LTU test i in v2 o v 2 out-test out-test test test i TST i i in v2 in v2 o o v v 2 2 i TST test in test test test i test i If Unilateral = out-test i in v2 o v 2 test out-test test

9 Will now develop two-port odel for each of the three basic aplifiers and look at one widely used application of each oon itter oon Source oon ase oon Gate oon ollector oon Drain

10 onsider oon itter/oon Source Two-port Models oon itter oon Source oon ase oon Gate oon ollector oon Drain Will focus on ipolar ircuit since MOS counterpart is a special case obtained by settin π =

11 asic /S plifier Structures OUT OUT M IN IN oon itter plifier oon Source plifier OUT OUT IN M IN oon itter plifier oon Source plifier an include or exclude and in two-port odels (of course they are different circuits) The and S aplifiers are theselves two-ports!

12 Two-port odel for oon itter onfiuration oon itter be π be O? i in v o 2 { i, and }

13 Two-Port Models of asic plifiers widely used for nalysis and Desin of plifier ircuits Methods of Obtainin plifier Two-Port Network i in v2 o v 2. TST : i TST Method 2. Write : 2 equations in standard for = i + IN 2 = i O 3. Thevenin-Norton Transforations 4. d Hoc pproaches

14 Two-port odel for oon itter onfiuration oon itter be π be O i in v o 2 y Thevenin : Norton Transforations in

15 Two-Port Models of asic plifiers widely used for nalysis and Desin of plifier ircuits Methods of Obtainin plifier Two-Port Network i in v2 o v 2. TST : i TST ethod 2. Write : 2 equations in standard for = i + IN 2 = i O 3. Thevenin-Norton Transforations 4. d Hoc pproaches

16 Two-port odel for oon itter onfiuration lternately, by TST : i TST Method To obtain in i test oon itter test be π O be i in v o 2 in in i test test { in, and }

17 Two-port odel for oon itter onfiuration lternately, by TST : i TST Method To obtain test be π O be out-test oon itter out-test test i in v o 2 outtest test { in, and }

18 Two-port odel for oon itter onfiuration lternately, by TST To obtain : i TST Method i test be π be O te oon itter i test i test test test i in v o 2 { in, and }

19 Two-port odel for oon itter onfiuration i in v o 2 oon itter In ters of sall sinal odel paraeters: in In ters of operatin point and odel paraeters: t i F F I Q t IQ haracteristics: Input ipedance is id-rane oltae Gain is Lare and Invertin Output ipedance is lare Unilateral Widely used to build voltae aplifiers

20 oon itter onfiuration onsider the followin application DD (this will also enerate a two-port odel for this application) out in oon itter inc Two-port includin in o in v out out Two-Port Model in out= o// in out in = r = i n π = // out o

21 oon itter onfiuration onsider the followin application (this will also enerate a two-port odel for this application) This circuit can also be analyzed directly without usin 2-port odel for confiuration oon itter inc out in be π be O out in = out out= = r in π in

22 oon itter onfiuration onsider the followin application (this is also a two-port odel for this application) Sall sinal paraeter doain oon itter inc Operatin point and odel paraeter doain out = r in π haracteristics: Input ipedance is id-rane oltae Gain is lare and Invertin Output ipedance is id-rane Unilateral Widely used as a voltae aplifier out in I = I Q t Q t

23 oon Source/ oon itter onfiurations in in t I Q oon itter oon Source in In ters of operatin point and odel paraeters: F F F in IDQ IDQ t IQ 2 2 F Q Q haracteristics: Input ipedance is id-rane (infinite for MOS) oltae Gain is Lare and Invertin Output ipedance is lare Unilateral Widely used to build voltae aplifiers

24 oon Source/oon itter onfiuration D oon itter inc out out in = r in I Q π t = I Q t D D in haracteristics: out Input ipedance is id-rane (infinite for MOS) oltae Gain is Lare and Invertin Output ipedance is id-rane Unilateral Widely used as a voltae aplifier out oon Source inc D in In ters of operatin point and odel paraeters: D D D 2I DQ D Q D D D

25 onsider oon ollector/oon Drain Two-port Models oon itter oon Source oon ase oon Gate oon ollector oon Drain Will focus on ipolar ircuit since MOS counterpart is a special case obtained by settin π =

26 Two-port odel for oon ollector onfiuration be π be O oon ollector? i ox ix vr2 v 2 { ix,, r and X }

27 Two-Port Models of asic plifiers widely used for nalysis and Desin of plifier ircuits Methods of Obtainin plifier Two-Port Network i in v2 o v 2. TST : i TST Method 2. Write : 2 equations in standard for = i + IN 2 = i O 3. Thevenin-Norton Transforations 4. d Hoc pproaches

28 Two-port odel for oon ollector onfiuration i oon ollector be π be O 2 pplyin KL at the input and output node, obtain i 2 i 2 o 2 These can be rewritten as i r π o o Standard Two-Port plifier epresentation i ix v2 i v ix 2 i ox 2 : 2 equations in standard for 2 2 ox It thus follows that ix =r π Or= X o o

29 Two-port odel for oon ollector onfiuration i be π be O 2 oon ollector i Two-port oon ollector Model ox ix v 2 vr2 ix =r π Or= X o o

30 oon ollector onfiuration onsider the followin application DD Deterine in,, and (this is not askin for a two-port odel for the application in and defined for no additional load on output, o defined for short-circuit input) in out IN oon ollector OUT SS in i ox ix vr2 v 2 out if ox o = = ox o o o = i + X in ix vr v in X = = π o r o = r r +β o o in π π

31 oon ollector onfiuration onsider the followin application (this is not askin for a two-port odel for the application, in and defined for no additional load on output, o defined for short-circuit input -) in DD out IN oon ollector OUT lternately, this circuit can also be analyzed directly SS i in π O OUT in out in in out out in I Q I + Q t i i in in in out in out in r + o o in= rπ π β o

32 oon ollector onfiuration onsider the followin application (this is not askin for a two-port odel for the application, in and defined for no additional load on output, o defined for short-circuit input -) in DD out IN oon ollector OUT SS i in π O OUT π O i out in OUT To obtain, set in i out out out out = o o

33 oon ollector onfiuration onsider the followin application (this is not askin for a two-port odel for the application, in and defined for no additional load on output, o defined for short-circuit input -) in DD out IN oon ollector OUT SS out = IQ I + r + o o Q t o o in= rπ π β o Question: Why are these not the two-port paraeters of this circuit? in defined for open-circuit on output instead of shortcircuit (see previous slide : -2 slides) r i ox ix v 2 vr2

34 oon ollector onfiuration DD For this application OUT (this is not a two-port odel for this application) IN in out oon ollector Sall sinal paraeter doain if IQ I + Q t SS Operatin point and odel paraeter doain I Q t o r +β in π in I Q t β + haracteristics: I Q t I t Q Output ipedance is low is positive and near Input ipedance is very lare Widely used as a buffer Not copletely unilateral but output-input transconductance (or r ) is sall and effects are enerally neliible thouh anitude sae as

35 oon ollector/oon Drain onfiurations For these /D applications (not two-port odels for these applications) DD OUT in out o r +β in π + IQ I + Q t I in Q t I IN Q t β if Output ipedance is low is positive and near Input ipedance is very lare oon ollector I Q t I t Q OUT in G D S SS S in out IN S + In ters of operatin point and odel paraeters: in S S S oon Drain if 2IDQ S if 2I DQ Q 2IDQ S+Q S 2I DQ S Q +2I 2I Widely used as a buffer Not copletely unilateral but output-input transconductance is sall Q S Q Q DQ S DQ S D

36 onsider oon ase/oon Gate Two-port Models oon itter oon Source oon ase oon Gate oon ollector oon Drain Will focus on ipolar ircuit since MOS counterpart is a special case obtained by settin π =

37 Two-port odel for oon ase onfiuration be π be O oon ase? i ox ix vr2 v 2 { ix,, r and X }

38 Two-Port Models of asic plifiers widely used for nalysis and Desin of plifier ircuits Methods of Obtainin plifier Two-Port Network i in v2 o v 2. TST : i TST Method 2. Write : 2 equations in standard for = i + IN 2 = i O 3. Thevenin-Norton Transforations 4. d Hoc pproaches

39 Two-port odel for oon ase onfiuration i be π be O 2 oon ase Fro KL i 2 i 2 2 These can be rewritten as 2 i 2 2 It thus follows that: ix Or i : 2 equations in standard for Standard For for plifier Two-Port in v2 o v 2 = i + IN 2 = i O ox

40 Two-port odel for oon ase onfiuration i be π be O 2 oon ase Two-port oon ase Model i ox in vr2 v 2 ix Or ox

41 oon ase onfiuration onsider the followin application (this is not askin for a two-port odel for this application - in and defined for no load on output, o defined for short-circuit input ) DD out IN OUT in oon ase in i ox ix vr2 v 2 out = + X in ix+ r out in= = i ix in= - i i // out X out r +

42 oon ase onfiuration onsider the followin application (this is not askin for a two-port odel for this application in and defined for no load on output, o defined for short-circuit input ) DD out IN OUT in oon ase lternately, this circuit can also be analyzed directly i out in be π be O 2 y KL at the output node, obtain + = + in y KL at the eitter node, obtain i = + + in out //r out out = + + in= + π + + π

43 oon ase pplication DD OUT (this is not a two-port odel for this application) out IN in oon ase in <<r out haracteristics: in I Q t t I Q <<r Output ipedance is id-rane is lare and positive (equal in a to that to ) Input ipedance is very low Not copletely unilateral but output-input transconductance is sall out

44 oon ase/oon Gate pplication (these are not a two-port odels) DD DD OUT D OUT out IN G GG D S OUT IN D in oon ase in oon Gate in <<r out D in out <<r D D I Q t in In ters of operatin point and odel paraeters: I << Q F t 2IDQ D I out in 2I Q Q Q DQ out I << DQ D D haracteristics: Output ipedance is id-rane is lare and positive (equal in a to that to ) Input ipedance is very low Not copletely unilateral but output-input transconductance is sall

45 oon itter with itter esistor onfiuration DD out out in in be π be O y KL at two non-rounded nodes - out in in- out in - + = out π in π π

46 oon itter with itter esistor onfiuration DD out out in in be π be O - It can also be shown that out r +β in π Nearly unilateral (is unilateral if o =)

47 oon itter with itter esistor onfiuration DD out - in r +β in π out (this is not a two-port odel) haracteristics: nalysis would siplify if were set to in odel Gain can be accurately controlled with resistor ratios Useful for reasonably accurate low ains Input ipedance is hih

48 (not two-port odels for the four basic structures)

49 an use these equations only when sall sinal circuit is XTLY like that shown!!

50 asic plifier Structures. oon itter/oon Source 2. oon ollector/oon Drain 3. oon ase/oon Gate 4. oon itter with / oon Source with S 5. ascode (actually : or S:G cascade) 6. Darlinton (special : or D:S cascade) Will be discussed later The first 4 are ost popular

51 Why are we focusin on these basic circuits?. So that we can develop analytical skills 2. So that we can desin a circuit 3. So that we can et the insiht needed to desin a circuit Which is the ost iportant?

52 nd of Lecture 33