A new small-signal RF MOSFET model

Transcription

1 A new sall-sinal F MOSFET odel KWO-MING HANG, HAN-PANG WANG Departent of Electronics Enineerin, National hiao-tun Uniersity, Hsinchu, Taiwan 3,. O.. Tel: Fax: Astract: In this paper, an accurate sall sinal odel of F MOSFETs accountin for the distriuted ate effect, the strate network and chare conseration is proposed for circuit siulation. The -paraeters expressions of the odel are deried. The odelin equations are of relatiely siple for and easily to e ipleented into a circuit siulation AD tool. The proposed odel is erified y the experiental data. Furtherore, seeral F odels hae een copared with the new odel, and results show that the proposed odel has a satisfactory accuracy in the siulation for F application. Key-Words: F, MOSFET, sall-sinal odel, nonreciprocal capacitance, HSPIE, distriuted ate resistance. Introduction ontinuously scalin down of the channel lenth and the sequent increase of the unit-ain cutoff frequency hae ade MOS technoloy ecoe a suitale technoloy in applications for analo F Is []. As circuitry operates at hiher frequency and lower oltaes, a ajor requireent to ensure the circuit perforance and to shorten the desin cycle for F circuit desin is the aailaility of F MOS transistor odel to descrie the circuit ehaior accurately. Seeral odels [], [3] were proposed to use discrete MOS transistors connected in series alon the channel to represent the distriuted channel network. These odels are accurate enouh for lon channel lenth deices, ut they are difficult to ipleent due to the coputational cost increase ecause of an increase in the nuer of MOSFETs that hae to e ealuated. In a paper y Ki et al. [4], the distriuted nature of the ate reion was odeled y treatin the MOS transistor as an array of sall indiidual transistors connected in series ia a ate resistance. Howeer, these odels were difficult to ipleent due to the scalin liitations in odelin sall indiidual transistors. In addition, a odel proposed y Aou-Alla et al. [5] accounts for the distriuted ate reion ased on the transission line theore. In this work, althouh it can accurately descrie the distriuted nature of ate reion, it did not take into account the strate network. In addition, seeral conentional odels [6-8] excluded the nonreciprocal capacitance considerin the chare conseration, and this would result in a sinificant error in predictin the iainary parts of and. In this work, we propose a hih frequency analytical MOSFETs odel well descriin the distriuted effects of the ate reion, strate reion, and includin the nonreciprocal capacitance. The proposed odel is physical-ased and can e easily applicale for MESFET and SOI MOSFETs structures. Sall sinal F MOSFET odel In this section, a new and analytical sall sinal F MOSFET odel includin the distriuted ate network effect, the strate network effect and the nonreciprocal

2 capacitance is proposed.. Approaches and assuptions To accurately descrie the fact that the sinal traels across the ate in the for of incident and reflected EM waes, we use the concept of transission line theore to odel the distriuted nature of the ate reion. For the sake of siplicity and calculation efficiency, we add a luped resistance to the ulk terinal and three strate-related capacitances (e..,, s and to account for the strate couplin effect. Besides, in order to take into account the chare conseration [], the nonreciprocal capacitances (e.., d and d are introduced into the odel, where d represents the capacitie effect of the drain on the ate, and d represents the capacitie effect of the ate on the drain. To descrie the distriuted nature of the ate reion, a MOS transistor is iewed as an array of discrete transistors connected in parallel ia ate resistances alon the ate reion, as illustrated in Fi., and the related sall sinal equialent circuit is shown in Fi. which is ased on the three-terinal confiuration. Gate Source s s d s s d s Fi.. Pictorial iew of distriuted eleents within a MOS transistor alon the ate width. s Sustrate In a three-terinal confiuration, the strate is tied to the source, as in ost hih frequency applications [], where X represents the ariale X per unit width. Before the deriations of the -paraeters of the MOS d s s d Drain Gate transistors, the followin assuptions hae to e ade. It is assued that the D ias condition reains the sae alon the ate width. This eans that only A sall sinals applied at the ate reion needed to e considered. It is assued that the electric field alon the width of the deice is sinificantly less than the fields existin alon the channel lenth. Source s s s s Bulk B s d d d ds dvs dt = d d Fi.. Sall-sinal equialent circuit of the MOSFET for F odelin, where = d d is a transcapacitance takin care of the different effects of the ate and drain on each other in ters of charin currents.. Analysis of the F MOSFET odel The circuit confiuration shown in Fi. is iewed as a dual-feeack circuit in which d is the local shunt-shunt feeack eleent that fors the first feeack loop (i.e., loop A, where d = d x represents the ate-drain capacitance of the section x at the ate reion, and, s, and x are the local shunt-shunt feeack eleents that for the second feeack loop (i.e., loop B, where = x represents the ate-strate capacitance of the section x at the ate reion, then the circuit ecoes uch easier to e soled. The feeack loops A and B are illustrated in Fi. 3, where V and V represent the output oltae (e.., V ds and the oltae alon the ate width shown in Fi., respectiely. By local shunt-shunt feeack theory [9], the loadin effects at the input and output terinals caused y the feeack networks shown in Fi. 3 can e expressed in the s Drain

3 -paraeter representation ien in appendix A (eqs.(a-a6. Feeack Loop A Fi. 3. The -paraeter presentations of two feeack loops, where loop A represents the sinal feeack path etween input and output nodes throuh d, loop B represents the feeack path throuh strate network. Fi. 4. The coplete sall-sinal equialent circuit of the F MOSFET after siplification y local shunt-shunt feeack theory [9]. By the local shunt-shunt feeack theory entioned aoe, the circuit in Fi. can e transfored into the, one in Fi. 4. In Fi. 4, soe coponents (i.e.,,, i d x V x V d d Feeack Loop B x i i V V s s i x s ( x, out, i i( x,, out,,,,,, and in the Blocks A and B are referred to as the per-unit width coponents and ien in appendix A (eqs.(a7-a for details. In the deriation of -paraeters, the coplete V V W, i,,, V, V, V, V, i i ds,, dvs dt = W, d BlockB d s, W, i BlockB V V out x sall-sinal equialent circuit of Fi. 4 is analyzed as a two-port circuit with input at the ate and output at the drain and oth the source and strate terinals are rounded. Alon the ate width, we hae the transission line equations in frequency doain as follows: ( x ( = i( x i( x = ( s s,, ( x x (. (,, out Takin the deriaties of ( and ( with respect to x, and coinin the consequent results ack into equations ( and (, respectiely, will result in two equations as follows: i x ( x ( s = i( x s,, (3 (4 The solutions for (x and i(x can e expressed as follows: ( x A i x = I (5 e I e ( x = V (6 e Ve B A where I, I, V and V are constants, and A = ( ss,, (7 B = (,, out. (8 In order to et the four constant coefficients, the oundary conditions i(w= and (= s are used and stituted into equations (5 and (6, and otain I V e AW V AW I e = B A = s (9 ( Then, stitutin equations (5 and (6 into equations ( and (, respectiely, we can hae the relationship of x ( x = ( s ( x s ( out,,,, constants V, V to constants I and I as follows: ( ( Ie I e ( AV e AV e A Ve AV e = A Ie AI e = ( By usin equations (9 (, the expressions for (x

4 and i(x can e otained as: ( ( ( B cosh A W x B x = s A cosh( A W A (3 B A sinh ( ( A ( W x i x = s (4 A cosh( A W where is the ate resistance per unit width. The aerae oltae at the ate reion and total current in the channel can e expressed as: ( B tanh AW B = s A AW A (5 B tanh( AW B = = s. A AW A (6 Then, accordin to the two-port circuit odel, the -paraeters of the equialent sall sinal circuit can e soled and ien in Appendix B for details. 3 Verification of the odel In this section, a erification includin coparisons of the extensions of the BSIM33 odels [] and [], the proposed odel and the easured data is presented. The easured data hae een corrected for the parasitic capacitances of input/output pads and the resistances and inductances of connection lines usin two-step de-eeddin technique []. In Fi. 5, the siulation results of -paraeters of BSIM33 odels [], [] and proposed odel are copared with the easured data for a MOS deice with W/L = -µ/.35-µ iased at V s = V and V ds = V. In this fiure, it is oious that a satisfactory areeent exists etween the siulation results otained y proposed odel and the easured data at frequency up to GHz. On the other hand, due to the lack of considerin chare conseration, the odels of [] and [] hae inaccurate predictions in the siulations of and, unlike the proposed odel. Therefore, the oseration of the ood atch etween the proposed odel and the easured data deonstrates that the proposed odel is accurate and appropriate for HF applications. (Sieens (Sieens (Sieens (Sieens Proposed odel Model of [] Model of [] W/L = -µ/.35-µ V s = V, V ds = V (a Proposed odel Model of [] Model of [] W/L = -µ/.35-µ V s = V, V ds = V ( (c (d Frequency (GHz I[ ] e[ ] Proposed odel Model of [] Model of [] W/L = -µ/.35-µ V s = V, V ds = V Frequency (GHz I[ ] e[ ] Proposed odel Model of [] Model of [] W/L = -µ/.35-µ V s = V, V ds = V Frequency (GHz I[ ] e[ ] Frequency (GHz I[ ] e[ ]

5 Fi. 5. eal and iainary parts of -paraeters (a ; ( ; (c ; and (d as a function of frequency for a deice with W/L = -µ/.35-µ for the easured data, odels of [], [] and proposed odel. 4 onclusions In this paper, a new and accurate sall sinal odel includin distriuted ate network, strate parasitics and nonreciprocal capacitances hae een deeloped. This odel uses transission line theore to descrie the distriuted ate reion, a sinle strate resistance and the related capacitances to odel the strate parasitic and the nonreciprocal capacitances to account for the chare conseration. In addition, usin the easured data to erify its accuracy in predictin HF characteristics of MOS transistors has done the exaination. A ood accuracy of the proposed odel has een found. Besides, a coparison of the siulations otained y proposed odel and BSIM33 extension odel to the experiental data has deonstrated the adaptaility of the proposed odel for F applications. Toether with the siple closed-for expressions for -paraeters, the present odel can e easily incorporated in AD tools (i.e., HSPIE for circuit siulation and optiization in F applications. Appendix A: The followin equations are eqs. (A-A6 in turn:, = s d =,, d = s d x, = s x = s s s,,, s x = =, ( ( ( s = s ( s x ( s ( x s ( s The followin equations are eqs. (A7-A in turn: = Appendix B: The -paraeters equations are expressed as: where G tanh( AW AW eferences: = s,, d, = sd s, =, =, = s =. [] P. H. Woerlee, et al, F-MOS perforance trends, IEEE Trans. Electron Deices, ol. 48,, pp ( s ( s ( x i = s i = i = out d s out= = s id = out = s s d s s ( s = s = s tanh AW s d = d s out = s = d s s s s ( AW = s G s s s ( G [ s ( ] s s s ds s s d G G

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