Self-consistent 2D Compact Model for Nanoscale Double Gate MOSFETs

Transcription

1 Self-consistent D Copact Model for Nanoscale Double Gate MOSFETs S. Kolberg 1, T.A. Fjeldly, and B. Iñiguez 3 1, UniK University Graduate Center and Norwegian University of Science and Technology, N-07 Kjeller, Norway {kolberg,torfj}@unik.no 3 Universitat Rovira i Virgili (URV), Tarragona, E-43001, Spain benjain.iniguez@urv.net Abstract. D odeling results of the electrostatics and the drain current in nanoscale DG MOSFETs are presented. The odeling of the D capacitive coupling within the device is based on the conforal apping technique. In oderate above-threshold conditions, we obtain self-consistent results, which are in excellent agreeent with nuerical siulations. 1 Introduction In nanoscale double gate (DG) MOSFETs, the electron barrier topology is a critical factor when deterining conduction paths and currents in the device. A prerequisite to obtaining a precise description of such devices is to include two-diensional (D) effects in the odels, based on a self-consistent solution of the D field pattern in the device. In such an approach, short-channel effects and scaling properties will be intrinsic to the odel which, accordingly, will require only a inial paraeter set of clear physical origin. The basic odeling proble is to obtain an analytical or sei-analytical solution of a D Poisson's equation where the four contacts (source, drain and the two gates) and the dielectric gaps define the boundary conditions. According to the superposition principle, Poisson's equation can be separated into a D Laplace equation for the capacitive coupling and the reainder involves the potential distribution established by the body charges [1-10]. The latter can usually be treated by siplifying considerations. The Laplace proble for the DG MOSFET can be solved in different ways. One possibility is to perfor a full Fourier expansion of the potential or by using a loworder truncation [1-4]. A corresponding procedure by eans of expansion in Bessel functions has been used for cylindrical surrounding gate transistors [5]. An alternative approach is to apply the conforal apping technique [6], which was first used for classical, long-channel MOSFETs [7]. Later, the technique was enhanced and applied to sub-100 n devices [8] and to the subthreshold regie of undoped, nanoscale DG MOSFETs [9,10]. Here, we present new odeling results based on this technique applied to a wider range of operation. V.N. Alexandrov et al. (Eds.): ICCS 006, Part IV, LNCS 3994, pp , 006. Springer-Verlag Berlin Heidelberg 006

2 608 S. Kolberg, T.A. Fjeldly, and B. Iñiguez In Section, we discuss the conforal apping as applied to the Laplaces proble in DG MOSFETs. In Section 3, we present a classical analysis of the self-consistent electrostatics of the device at gate voltages where the concentration of free electrons is significant. The specific device considered is assued to have a gate length of L =5 n, a silicon thickness of t Si = 1 n, a p-type body doping of N a =10 15 c-3, an aluinu etal gate, and a high-k gate insulator (nitrated Si-oxide) with a relative perittivity of 7 and a thickness of t ox = 1.6 n [11]. In such a sall device volue, the depletion charge can be neglected. Because of the sall diensions of this device, the drain current will have the character of both drift-diffusion and ballistic transport. However, we only consider the drift-diffusion foralis since it allows us to ake coparisons with nuerical calculations using the Atlas siulator fro Silvaco. Conforal Mapping and Capacitive Coupling The ethod of conforal apping is applied since the solution of the Laplace equation is ore easily derived in the new plane into which the device is apped. This solution is then apped back to the noral plane using a apping function for the coordinates between the two planes..1 Conforal Mapping The device body described in the noral (x, y) -plane, as depicted in Fig. 1 (with D equipotential lines indicated), is apped into the upper half of a coplex (u, iv) - plane. Fig. 1. Scheatic view of the DG MOSFET device structure indicating the D equipotential lines associated with capacitive coupling between the contacts The boundary of the body is apped into the real u-axis [9], as shown in Fig.. The iv-axis represents the gate-to-gate syetry line through the body center. To siplify the discussion, we replace the insulator of thickness t ox by an electrostatically equivalent silicon layer of thickness t' ox =t ox ε s /ε ox, where ε s and ε ox are the perittivities of the silicon and the insulator, respectively. Laplace's equation is then considered for this extended body whose boundary is defined by the inner surfaces of the gate electrodes, the source, the drain, and the insulator gaps in the four corners between the contacts. In the strongly doped source and drain contacts, the depletion widths will be

3 Self-consistent D Copact Model for Nanoscale Double Gate MOSFETs 609 Fig.. The body of the DG MOSFET apped into the upper half of the (u, iv)-plane. The insets show the apping functions for the u-axis (lower), the iv-axis (upper left) and the circle with radius 1/ k. These represent the boundary, the gate-to-gate syetry line, and the source-todrain syetry line, respectively. sall copared to the body diensions and can be neglected, although the potential drops within this region should be counted. The apping of the boundary is defined by the following Schwartz-Christoffel transforation [5,9,10]: ( k, w) ( k ) L F z = x + iy = where K = w dw' F( k, u) w ( 1 w' )( 1 k ' ) 0 Here, F(k,u + iv) is the elliptic integral and K(k) F(k,1) is the coplete elliptic integral, both of the first kind. The odulus k is a constant between 0 and 1 deterined by the geoetric ratio L/(t si + t' ox ). For real arguents in the standard range 0 u 1, aple approxiate expressions, series expansions, and iteration routines exist for F(k,u). F(k, u + iv) can also be expressed in ters of the standard elliptic integral for soe other values of the arguent, both real and coplex. In addition, routines exist for calculating the values for general coplex arguents w. Note that in Fig., u = 0 corresponding to x = 0 defines the iddle point on the upper gate contact (Gate 1). The four corners of the body ap to u = ±1 and u = ±1/k. The iddle point in the lower gate contact (Gate ) is at u = ± or v =. For the boundary, the apping functions are given by the following expressions in ters of the standard elliptic integral (note that F(k,-u) = - F(k,u)). Gate1: L F( k, u) x K( k) =, y = 0 (1) ()

4 610 S. Kolberg, T.A. Fjeldly, and B. Iñiguez S and D: L x = ±, y = ( ) t + t' 1 F 1 k, K( 1 k ) Si ox 1 k u 1 k (3) L 1 = (4) ku Gate: x Fk, K( k), y = t Si + t' ox For the present device, where k = 0.478, the apping function for the boundary is shown in the lower part of Fig.. The gate-to-gate syetry line, which corresponds to the iaginary axis in the w-plane, has the following apping function [10]: G1-G sy. line: v ( tsi + t' ) F ox 1 k, K ( 1 ) x = 0, y = k 1 + v Siilarly, the source-to-drain syetry line aps into a circle of radius 1/ k about the origin of the w-plane as follows, 1 + k 1 k + S D sy. line: L k k t ' ox,cos( ), Si + t x = F θ K y = (6) where θ is the angle easured anticlockwise fro the positive u-axis. The apping functions for these two syetry lines are shown in the upper left and right insets of Fig., respectively. Once the potential distribution has been calculated in the (u, iv)-plane, it can be apped back into the (x, iy)-plane using the above expressions.. Capacitive Coupling The potential distribution throughout the body can generally be expressed as [6] ( u, v) v = π ( u' ) ( u u' ) + du' v where φ(u') is the electrostatic potential along the boundary, i.e. for all values of u', and the integral runs over the entire boundary. The ajor contributions to this integral coe fro the four equipotential contacts and inor ters coe fro the insulator at the four corners. In the liit of zero insulator thickness, Eq. (7) results in the following analytical expression for the potential distribution in the w-plane [10], (5) (7) ( u, v) 1 1 ku ku ( VGS VFB ) π tan tan + ( VGS1 VFB ) kv kv u 1 1+ u 1 1 ku 1 1 u = tan + tan + Vbi tan tan π v v kv v 1 1+ ku 1 1+ u + ( V + V ) bi DS tan tan kv v (8) In our calculations, the effects of a finite insulator thickness are included. V GS1 and V GS are the potentials of Gate 1 and Gate, respectively, referred to the source contact, V FB is the flat-band voltage for the gates and the silicon body, V bi is

5 Self-consistent D Copact Model for Nanoscale Double Gate MOSFETs 611 the built-in voltage of the source and drain, and V DS is the drain-source voltage. Along the two syetry lines, Eq. (8) siplifies soewhat. Moreover, the apping functions along these lines can be expressed in ters of the unity-range elliptic integrals. The potential distribution according to Eq. (8) will doinate the behavior of the device in the subthreshold regie. Using the general apping function of Eq. (1), the potential profile can now be transfored back to the z-plane. Fig. 3 shows φ(x, y) for the present device in subthreshold using V GS1 = V GS = V and V DS = 0.5 V. Fig. 3. Potential distribution over the extended body at subthreshold condition (V DS = 0.5 V and V GS1 = V GS = V) calculated fro Eq. (8) and apped to the (x,y)-plane using the apping functions discussed in Section.1 We note that the potential distribution has a saddle point near the device center, corresponding to the iniu barrier energy for electron conduction between source and drain. With increasing drain voltage, the barrier iniu is steadily lowered and shifted fro the device center towards the source. This drain-induced barrier lowering (DIBL) is intrinsic to the present foralis as expressed in Eq. (8) [9,10]. An excellent agreeent between the present odel and nuerical calculations using the Atlas device siulator has been deonstrated [10]. With increasing gate voltage, the barrier gate-to-gate energy profile is lowered and flattens. Eventually, the barrier iniu shifts to the silicon-insulator interfaces. When we approach this regie, the induced electron density will be sufficiently high to significantly influence the device electrostatics, requiring a self-consistent analysis (see Section 3). The device threshold voltage V T can be defined in several ways, for exaple, in ters of a iniu current level, a iniu electron sheet density, or, as is usually done for the classical MOSFET, as the gate bias that causes a band bending by twice the silicon body Feri potential at the barrier iniu. Using the latter definition, we find fro the potential distribution of Eq. (8) that V T = V for syetric gates and zero drain bias [10]. For the other definitions, V T will be higher.

6 61 S. Kolberg, T.A. Fjeldly, and B. Iñiguez 3 Self-consistent Modeling in Moderate Inversion In oderate inversion, the contribution of the electrons to the body potential distribution is coparable to that of the capacitive coupling. We assue a classical electron distribution and consider specifically the gate-to-gate energy barrier at the iddle of the device for V GS1 = V GS and V DS = 0 V. The shift in position and agnitude of the barrier at finite V DS (DIBL-effect) is ebedded in the D expression of Eq. (8) and therefore carries over to the calculation of the odified, self-consistent gate-to-gate barrier profile. For the drain current odeling (see Section 4), we have adopted a siplified approach where we assue that the gate-to-gate potential distribution for finite values of V DS retains the sae, near-parabolic for as for V DS = 0 V, but scaled to reflect the correct barrier iniu as dictated by the DIBL-effect. Along the gate-to gate syetry line, we superipose the 1D potential contribution φ 1 (y) fro the free electrons and the D contribution φ (y) fro the capacitive coupling to obtain the total potential ( ) 1 ( y) ( y) = + (9) y Classically, φ 1 (y) is deterined by integrating twice the 1D Poisson equation for the total potential using Boltzann statistics for the electron density inside the silicon layer. This leads to a self-consistent expression for φ 1 (y) in the for of an integral equation. To solve this, we approxiate φ(y) by a syetric parabolic for with a axiu deviation φ fro its boundary value V GS V FB. For thin devices as here, this approxiation is found to agree very well with nuerical siulations within the operating range considered. By adding the resulting, explicit expression for φ 1 (y) to φ (y) fro Eq. (8) in Eq. (9), we obtain the following iplicit, algebraic equation fro which the paraeter φ can easily be extracted, 4 = tan π sgn 1 ( ) ( t + t' ) 1 + qni Si ox VGS VFB b 1 ( V ) bi VGS + VFB exp k 8ε s Vth πv th t' ox V ' th t ox erf + 1 exp 1 1 Vth tsi + t' ox Vth tsi + t' ox Here, erf is the error function and sgn returns the sign of its arguent. Fig. 4a) shows a coparison of the potential φ versus applied V GS for V DS = 0 V as calculated fro Eq. (10) and siulated classically fro Atlas. Note that in the odel calculations, we have adjusted V bi to include the effects of a finite depletion width inside the source and drain. We observe an excellent agreeent between the odel and the siulation within the range of V GS considered. (10) 4 Drain Current Modeling The sall diensions of the present device indicate that the drain current will have the character of both drift-diffusion and ballistic/quasi-ballistic transport. Here, we discuss a drain current odel based the classical drift-diffusion foralis.

7 Self-consistent D Copact Model for Nanoscale Double Gate MOSFETs 613 For this device, the barrier topography at axiu is relatively rigid, i.e., it is little affected by the drain current for a reasonable set of bias voltages within the subthreshold and oderate inversion regies. This allows us to use the following siple, explicit drift-diffusion odel for the current that relies on the shape of the barrier near its axiu [1], I DD = qwμ n n s ( x) dv F dx ( x) VDS Vth qwμ V ( 1 e ) n th L 0 dx n Here, W is the device width, V F (x) is the quasi-feri potential in the channel, n s (x) is the sheet electron density of the channel, and n so (x) is the sae density in the absence of drain current (constant V F fro source through the barrier). Note that with I DD obtained fro Eq. (11), we can go back and find an estiate of the true V F (x). If necessary, this, in turn, can be used to derive a self-consistent expression for I DD, where the effect of the current on the barrier profile is included. Fig. 4b) shows a coparison between the odeled drift-diffusion current obtained fro Eq. (11) and the corresponding current using the Atlas device siulator. Note that in this odel calculation, we have adjusted the effective gate length slightly to account for the true path length of the carriers through the channel. Again, we observe an excellent agreeent between odeled and siulated results within the range of V GS considered. so ( x) (11) a) b) Fig. 4. Coparison of φ versus V GS for V DS = 0 V (a) and drift-diffusion current versus V GS for V DS = 0.1 V, 0. V and 0.3 V (b) between calculations based the present odel (Eqs. (9) and (11)) (solid curves) and nuerical siulations perfored with Atlas (sybols) 5 Conclusion We have developed a precise, copact D odel for nanoscale DG MOSFETs for the subthreshold and the oderately strong inversion regies of operation. The D odeling is based on conforal apping techniques and a self-consistent analysis of the energy barrier topography, that include the effects of both the capacitive coupling between the contacts and the presence of electrons. Assuing a drift-diffusion transport echanis, the drain current calculated fro the present odel and fro

8 614 S. Kolberg, T.A. Fjeldly, and B. Iñiguez nuerical siulations (Atlas) show excellent agreeent. Extensions of the odel to include the strong inversion regie, quantu effects, and ballistic/quasi-ballistic transport are under way. Acknowledgeent This work was supported by the European Coission under contract no (SINANO) and the Norwegian Research Council under contract No /130 (SMIDA). We acknowledge the donation of TCAD tools fro Silvaco. References 1. Woo, J. S., Terrill, K.W., Vasudev, P. K.: Two-diensional analytic odeling of very thin SOI MOSFETs. IEEE Trans. Electron Devices. vol. 37 (1990) Frank, D. J., Taur, Y., Wong, H.-S. P.: Generalized scale length for two-diensional effects in MOSFETs. IEEE Electron Device Letters. vol. 19 (1998) Oh, S.-H., Monroe, D., Hergenrother, J. M.: Analytic Description of Short-Channel Effects in Fully-depleted Double Gate and Cylindrical, Surrounding-Gate MOSFETs. IEEE Electron Device Letters. vol. 1. no. 9 (000) Liang, X., Taur, Y.: A -D analytical solution for SCEs in the D MOSFET. IEEE Trans. Electron Devices. vol. 51. no. 8 (004) Iñíguez, B. Haid, H. A., Jiénez, D., Roig, J.: Copact Model for Multiple Gate MOSFETs. Proc. of the Workshop on Copact Modeling, Anahei, CA (005) Weber, E.: Electroagnetic fields, vol. 1 - Mapping of Fields. Wiley, New York (1950) 7. Klös, A., Kostka, A.: A new analytical ethod of solving D Poisson s equation in MOS devices applied to threshold voltage and subthreshold odeling. Solid-State Electronics. vol. 39 (1996) Østhaug, J., Fjeldly, T. A., Iniguez, B.: Closed-for D odeling of sub-100n MOSFETs in the subthreshold regie. J. Teleco. and Inforation Techn.. vol. 1/004, (004) Kolberg, S., Fjeldly, T. A.: D odeling of nanoscale DG SOI MOSFETs in the subthreshold regie, accepted for publication in Journal of Coputational Electronics 10. Kolberg, S., Fjeldly, T. A.: D Modeling of Nanoscale Double Gate SOI MOSFETs Using Conforal Mapping. Physica Scripta, accepted for publication in Physica Scripta 11. Teplate device for odeling and siulation defined within the European Coission Network of Excellence project SINANO ( 1. Fjeldly, T. A., Shur, M. S.: Threshold Voltage Modeling and the Subthreshold Regie of Operation of Short-Channel MOSFETs. IEEE Trans. Electron Devices. vol. 40, (1993)