Is quantum capacitance in graphene a potential hurdle for device scaling?

Transcription

1 Electronic Supplementary Material Is quantum capacitance in raphene a potential hurdle for device scalin? Jaeho Lee 1,,, Hyun-Jon hun 1,3, (), David H. Seo 1, Jaehon Lee,4, Hyuncheol Shin, Sunae Seo 1,5, Seonjun Park 1, Sunwoo Hwan 1, and Kinam Kim 1,6 1 Samsun Advanced Institute of Technoloy, Samsun Electronics, Yonin-Si, Gyeoni-Do , Korea Inter-University Semiconductor esearch enter (IS), School of Electrical Enineerin and omputer Science, Seoul National University, Seoul , Korea 3 Division of Quantum Phases and Devices, Department of Physics, Konkuk University, Seoul , Korea 4 Semiconductor &D enter, Samsun Electronics, Hwasun-ity, Gyeoni-Do , Korea 5 Department of Physics, Sejon University, Seoul , Korea 6 Memory Division, Samsun Electronics, Hwasun-ity, Gyeoni-Do , Korea Both authors are contributed equally. Supportin information to DOI /s S1 Extraction of device parameters usin various equivalent circuit models S1.1 Off-state model The off-state-equivalent circuit consists of the capacitances and ate resistance as shown in Fi. 3(a) in the main text. Each component can be extracted from the Y-parameters of radio-frequency measurements. We can obtain four components (Y 11, Y 1, Y 1 and Y ) of the Y-parameter from two-port measurements, with the ate electrode as port 1 and the drain electrode as port. From the equivalent circuit of device, we can express the Y-parameters usin device components such as ate resistance ( ), ate source capacitance ( s0 ), ate drain capacitance ( d0 ), oxide capacitance ( ox ) and quantum capacitance ( Q ). We used the Y 11 parameter to extract the quantum capacitance. The Y 11 parameter can be expressed as Y j j, f. 1 j 11 1 (S1) Address

2 Fiure S1 Therefore, can be obtained as follows: ey Im Y 11 11, (S) ImY where ey is the real part of Y-parameter, ImY means the imainary part, and f is measurement frequency. If we divide the ate capacitance into overlap capacitance ( over ) and channel capacitance ( channel ), the over decreases with underlap (L s or L d ). Since the channel capacitance is only related to the ate-controlled area and not influenced by device underlap variation, we can express the ate capacitance as a function of device underlap as 11 ( L ) ( L ) (S3) s over s channel Since the overlap capacitance between ate and source/drain electrodes can be approximated as a simple MIM capacitor with distance d and dielectric constant ε overlap, overlap can be expressed as follows: overlap overlap Area d L s t ox. (S4) The measured ate capacitance can be fitted as shown in Fi. S1, and channel can be obtained by extrapolation, since overlap capacitance is zero for infinite underlap. We can acquire the quantum capacitance from the ate capacitance usin Eq. (3) from ox and channel capacitance ( channel ). S1. On-state model The on-state model uses the equivalent circuit as shown in Fi. S (the same as Fi. 3(b) in the main text). From the equivalent circuit, Y-parameters were obtained and device parameters were extracted. The extraction process is as shown below: to derive the Y-parameter, the equivalent circuit is divided into reions 1,, 3 and the intrinsic (INT) part for convenience. The Y-parameter of the raphene device is expressed as Y Y Z Y Z DUT INT reion3 reion reion1 1 (S5)

3 Fiure S Each reion can be expressed as the followin equations: Z reion (S6) Z reion i( ) i s0 d0 d0 i i( ) d0 ds0 d0 (S7) Z reion3 0 s + s s d (S8) Y INT i( ) i s d d i i m d ds d (S9) The Y-parameter of the intrinsic reion (Eq. (S9)) is derived from considerin the current flow as shown in Fi. S3 and the followin equations: i i v, i i ( v v ), i v, i v (S10) 1 s 1 d 1 3 m 1 4 ds I i i 1 1 I YV I i i i 3 4 i v i ( v v ) s 1 d 1 i ( v v ) v v d 1 m 1 ds i( ) v i v s d 1 d ( i ) v ( i ) v m d 1 ds d Y Y v Y Y v 1 (S-11) Nano esearch

4 Solvin equation S5 is too complicated to obtain the device parameters:, d, s, m, ds ( ds ), s, d, s0, d0, and ds0. Therefore we separate the raphene part and the electrode part for simplicity. S1..1 Parasitic component extraction of electrodes Fiure S3 We first extract the electrode components (, s0, d0 and ds0 ), which have no contribution from raphene. We used additional patterns which were the same as the devices except for the absence of raphene. Fiure S4 shows the equivalent circuit of the extraction pattern of the electrode components. The Y-parameter of the extraction pattern is expressed as Y [ Y Z ] Y [ Y Z ]. (S1) pattern reion reion1 reion pattern reion1 Fiure S4 Usin Eqs. (14) and (15), the Y-parameter of the pattern is iven by the followin equations: Y 1 reion ds0 d0 d0 i i [ ( )] [ ( )] d0 s0 ds0 d0 s0 d0 ds0 s0 ds0 d0 Zreion1 d0 ds0 d0 i i [ ( )] [ ( )] d0 ds0 s0 ds0 d0 d0 s0 ds0 d0 s0 (S13)

5 [ Y Z ] ( ) d0 s0 d 0 ( ) i ( ) d0 s0 i d0 s0 ( i [ ( )] d0 d0 s0 ds0 d0 s0 ( ) i ( ) i d0 s0 d0 s0 1 1 pattern reion1 d0 s0 (S14) Therefore, the electrode components can be derived as follows: d0 e[ Y ](e[ Y ] Im[ Y ] ) (e[ Y ] e[ Y ])(e[ Y ] Im[ Y ] ),, (S15) s0 e[ Y ]Im[ Y ] e[ Y ]Im[ Y ] e[ Y ] 11 e[ Y ] Im[ Y ] Eq. (S15) are used in the main text to extract the parameters for the two on-state models. S1.. Parameter extraction for the raphene device Now we are oin to obtain the parameters of the intrinsic device as shown in Fi. S3. Since the electrode components are removed, Eq. S5 can be modified as 1 1 DUT 1 1. M reion1 reion INT reion3. Y Y Z Y Y Z (S16) The Y-parameter components of YM can be expressed as the real and imainary parts as shown in Eq. (S17). Usin Eqs. (S7) and (S11), the Y-parameter components of Y M are obtained from the followin equations: Y M ii ii ii ii (S17) 1 1 s ds s d d s ds m s s s ds d s d ds m d s 1 s d d s ds d s m s s d s 11 I s d d s s ds s d d s ds m s s s ds d s d ds m d s ds d s m s s d s 11 d s s 1 ds d s m s s d s 1 d d ds s s ds s d m s s ds s d d s ds m s Nano esearch

6 I s d s s ds s d d s ds m s d ds s d s d m s ds d s m s s d s 1 I m d s s 1 ds d s m s s d s 1 d d ds s s ds s d m s s ds s d d s ds m s m s d s s ds s d d s ds m s d ds s d s d m s ds d s m s s d s d s ds s d d s ds m s ds ds d s m s s d s I 1 1 ds s ds s d d s ds m s d ds d s m s s d s (S18 S5) S1...1 On-state model without underlap resistance In this model, it is assumed that the underlap (L s ) is zero, that is, s = d = 0. Then, the equations can be reduced to the simple form: Im[ Y ] Im[ Y ] Im[ Y ] ,, e[ Y ], e[ Y ]. (S6) d s m 1 ds Equations (S6) and (S15) are used in the main text to extract parameters for the on-state model without underlap resistances. S1... On-state model with underlap resistance If the resistance components caused by underlap are nelected, the device parameters are exactly obtained in the small underlap device. However, the underlap increment induces an extraction error. Hence, we proposed an improved method of device parameter extraction usin an assumption based on the device eometry. The transistor has a symmetrical layout. Hence, if a device misalined between ate electrode and source/drain electrodes is fabricated, the underlap resistance between ate and drain is the same as the resistance between ate and source, since the underlap resistance is a function of the distance between electrodes. Fiure S5 shows the layout of the misalined device. ompared with the normally fabricated device, the distance between ate

7 Fiure S5 and drain is same as the distance between ate and source for the ate-shift condition. Hence, we can assume s is equal to d. Usin this assumption, the parameter equations were derived as follows: d e[ Y ]Im[ Y ] e[ Y ]Im[ Y ] Im[ Y ] 3Im[ Y ]Im[ Y ] Im[ Y ] e[ Y ] e[ Y ] 11 1 s e[ Y ] 3e[ Y ]e[ Y ] e[ Y ] s e[ Y ]Im[ Y ] e[ Y ]Im[ Y ] Im[ Y ]Im[ Y ] Im[ Y ] e[ Y ] e[ Y ] 11 1 s e[ Y ]e[ Y ] e[ Y ] (S7) e[ Y ] (Im[ Y ]Im[ Y ] Im[ Y ] e[ Y ]e[ Y ] e[ Y ] ) 1 1 s ds s Im[ Y ] 3Im[ Y ]Im[ Y ] Im[ Y ] e[ Y ] e[ Y ] 11 1 s e[ Y ] 3e[ Y ]e[ Y ] e[ Y ] ( )(Im[ Y ] e[ Y ] ) Im[ Y ]( 6 ) s d d d s s ( )( (Im[ Y ] e[ Y ] ) 4 e[ Y ] 4) d s s d s s 11 ( )( (Im[ ] e[ ] ) e[ ]) m Y Y Y s d s s Equations (S7) and (S15) are used in the main text to extract parameters for the on-state model with underlap resistance. S esistance of the ate metal Usin the ate structure of the radio-frequency device, the resistance of the ate pattern can be calculated. The ate pattern consisted of via and ate patterns excludin interconnection line as shown in Fi. S6. Via was divided into the Au reion with resistance Via and the TiN reion with resistance INTVia. Hence, ate resistance can be expressed as the resistances of three parts as shown in the followin: INT_ate INTVia Via (S-8) T ( INTVia_ w) ( INT_ w),, 3( Via _ l)( Via _ w) 3 T ( INTVia _ l) 3 TL( N ) Au Via Tin Tin Via INTVia f W TiN f 3TL N INT _ ate f Nano esearch

8 Fiure S6 Fiure S7 The ate resistance was calculated to be Ω usin the structural dimensions and material parameters of the ate pattern shown in Table 1. Therefore, the extracted resistance Ω seems realistic, when compared with the calculation shown in Fi. S8. Table 1 Fiure S8