ANALYSIS OF POWER EFFICIENCY FOR FOUR-PHASE POSITIVE CHARGE PUMPS

Transcription

1 ANALYSS OF POWER EFFCENCY FOR FOUR-PHASE POSTVE CHARGE PUMPS Chien-pin Hsu and Honchin Lin Department of Electrical Enineerin National Chun-Hsin University, Taichun, Taiwan ABSTRACT n this paper, the compact model of power efficiency for four-phase positive chare pump is derived. The model was verified by usin post-layout simulation with 0.5µm triple-well flash memory technoloy. By includin parasitic effects in the pump, the discrepancies between the model and the post-layout simulation results are within 4%. KEY WORDS Modellin, power efficiency, body effect, threshold voltae, and chare pump 1. ntroduction The chare pump is a DC-DC voltae converter to enerate the required voltae hiher or lower than the supply voltae. Chare pump circuits are usually applied to flash memory, EEPROM and LCD displays. The most popular schemes are based on the circuit proposed by Dickson [1]. Due to low power requirement in many applications, the power efficiency of the chare pump has become one of the important issues in recent years. Palumbo et al. proposed an optimized stratey to desin minimum power consumption for the two-phase chare pump []. The power efficiency comparison between four-phase chare pump and voltae doublers [3] was presented. Even thouh the power efficiency of voltae doublers is slihtly better, they require h NMOS and PMOS transistors at the same time, unlike four-phase chare pumps only requirin NMOS or PMOS transistors. The SO CMOS process used to increase efficiency was discussed in [4]- [6]. Althouh many works have been done for power efficiencies of the two-phase chare pumps and voltae doublers, there have been few reports focused on fourphase chare pumps. n this paper, a complete chare transfer method to analyze the power efficiency is presented for the four-phase chare pump. The resultin model was verified by usin a 0.5µm triple-well flash memory process. This paper is oranized as follows. n Section, the modified four-phase four-stae positive chare is described. The formulation of power efficiency for the chare pump is derived in the next section. Section 4 shows the areement of the proposed model and the postlayout simulations. The final conclusions are iven in Section 5.. The Four-Phase Positive Chare Pump The performance of the Dickson chare pump is deraded due to threshold voltae and body effect. The modified four-stae positive chare pump with the four-phase clocks is shown in Fi. 1 [7]. The reason to add the transistor M si (i = 1~4) will be iven below. One stae of the chare pump consists of a storae capacitor (C i = C L = C, i = 1~4), an NMOS switch (M i ), a ate boostin circuitry (M i and C i ), and a body control transistors M si. Durin the chare transferrin period, the chare stored in C i is transferred to C i+1 of the next stae throuh the switch transistor, M i. n order to eliminate the threshold voltae deradation in M i, the ate boostin circuitry is used to raise much hiher ate voltae of M i. The conventional method to avoid body effect of M i is achieved by tie the well to its drain. However, the hih instantaneous PN junction between the well and the source may cause hiher noise in the chip, thus the reliability may become an issue. To minimize the noise issue, the transfer switch M si is used to track the well to the lowest potential in each stae to avoid body effects [8]. Fi. 1. The modified four-stae positive chare pump and the four-phase clocks

2 The output of an N-stae four-phase positive chare pump can be iven as C N Vout = ( N + 1) V Vtn (1) C C + f ( C + C ) where V tn is the threshold voltae of switch M out, C is the switch-node parasitic capacitance, is the current, and f is clock frequency whose amplitude is V. = t1 t () t 3 = + + b + t (3) t 5 = t (4) Qt 7 = + + t + b (5) 3. Compact Model of Power Efficiency To calculate the power efficiency of the four-phase positive chare pump, the power consumption must be evaluated. The power consumption in the chare pump includes the storae capacitor C i, the boostin capacitor C i, the tom-plate (C ) and the -plate (C ) parasitic capacitances of C i, as well as the tom-plate (C b ) and the -plate (C t ) parasitic capacitances of C i. Actually, the total switch-node parasitic capacitors include the ate capacitance of M i, C db of M i, C db and C sb of M i, and C db of M si [6]. For simplicity, those parasitic capacitances are assumed to be included in C and C t in the followin analysis. Moreover, the ideal clock sinals without buffers are directly connected to the tom plates of C i and C i for power efficiency analyses [1], since the sizes of buffers influence the power consumption and the waveforms of clocks. The clock cycles are divided into eiht different intervals in time. Fis. to 5 illustrate the chare distribution of the four-phase positive chare pump in time intervals t1, t3, t5 and t7, respectively. Durin t1, M 1, M 3 and M out are turned on and the chares of V and φ 1 are transferred to C 1, C 3 and C L, respectively. At time interval t3, the chares of V and C are transferred to C 1 and C 3 throuh M 1 and M 3, respectively. Durin t5, similar to t1, M and M 4 turn on and the chares of φ 3 are delivered to C and C 4. Similarly, at time t7, those chares stored in C 1 and C 3 are transferred to C and C 4 throuh M and M 4, respectively. Nevertheless, there is no chare consumed in the others time interval. The clock cycles are divided into eiht different intervals in time. Fis. to 5 illustrate the chare distribution of the four-phase positive chare pump in time intervals t1, t3, t5 and t7, respectively. Durin t1, M 1, M 3 and M out are turned on and the chares of V and φ 1 are transferred to C 1, C 3 and C L, respectively. At time interval t3, the chares of V and C are transferred to C 1 and C 3 throuh M 1 and M 3, respectively. Durin t5, it is similar to t1 that M and M 4 are turned on and the chares of φ 3 are delivered to C and C 4. Similarly, at time t7, those chares stored in C 1 and C 3 are transferred to C and C 4 throuh M and M 4, respectively. Nevertheless, there is no chare consumed in the other time intervals. From t1 to t8, the chares provided by V are Fi.. Chare transfer durin t1 (φ 1 = φ 3 = hih, φ = φ 4 = Fi. 3. Chare transfer durin t3 (φ 1 = φ = hih, φ 3 = φ 4 = Fi. 4. Chare transfer durin t5 (φ 1 = φ 3 = hih, φ = φ 4 = Fi. 5. Chare transfer durin t7 (φ 1 = φ = low, φ 3 = φ 4 = hih) The total chare provided by the power supply in one clock cycle is the sum of Eqns. () to (5). T = t + 4 (6) 1 b Therefore, the total current consumption of the four-phase chare pump is 16

3 total = t + 4b (7) This analysis can be extended to any number of staes. For an N-stae chare pump, the total current consumption can be expressed as total = ( N + 1) + N + (N + 1) + N + Nt + Nb (8) The current that chares and dischares the tom plate and the plate of the storae capacitor is iven as [6] = C V (9) C = C + C (10) where V is the supply voltae and is the output in current. Similarly, b = C V b Ct and t Ci + C t can be obtained for the tom plate and the plate of the boostin capacitor, where is the current that chares the boostin capacitor. By definition, the power efficiency of the chare pump may be written as follows. P out Vout η = = (11) P V in By substitutin the above expressions of currents and V out into Eqn. (11), the efficiency η can be written in Eqn. (1). C N ( N+ 1)( ) V Vtn C+ C f ( C+ C ) η = NC ( 1) V f N+ C N t Cb V f V ( N+ 1) N + N C+ C ( Ci + Ct ) total (1) Since the tom-plate and the -plate parasitic capacitance C and C are nearly proportional to the storae capacitor C, we may assume C = αc and C = C. Hence, Eqns. (9) and (10) become = α V (13) = = (14) C + Similarly, C b and C t are also fractions of the boostin capacitor C i so that C b = α C i and C t = C i. b and t can be expressed as b = α i V (15) i t = = (16) C + i i 1 N ( N + 1)( ) V Vtn f (1 + ) η = NαCV + V f (N 1) γ α γ V ( N + 1) Nγ + N + N 4. Model Verification f (17) To verify the compact model obtained in the previous section, the post-layout SPCE simulations were carried out with 0.5 µm triple-well flash memory technoloy. The threshold voltae of the NMOS is about 0.65 V. The storae capacitance and the boostin capacitance for the chare pump are 35 pf and 1 pf, respectively. The parameters α and based on the post-layout parasitic parameter extraction for the chare pump are α = and = 0.0. Similarly, the parameters related to the boostin capacitors α and are and 0.019, respectively. A set of simulation results was performed by varyin the supply voltae from 1. V to V with the output current from 0 µa to µa at the frequency of 6MHz or 10MHz. Power efficiency and V out are compared between the compact model and post-layout simulations in Fis. 6 to 9. The simulations aree well with the model with the maximum errors lower than 4%. Efficency (%) Model Simulation Supply Voltae (Volt) Fi.6. Power efficiencies versus supply voltaes for the four-stae pump with f = 10 MHz and output current = 1 µa Since the storae capacitance is more than an order of manitude larer than boostin capacitor. Therefore, it can be assumed that C i is a fraction of C to have C i = γc. Thus, Eqn. (1) can be rewritten as 17

4 V out (Volt) Fi. 7. Output voltaes vs. in currents for the fourstae positive chare pump with V = 1.8 V Efficiency (%) Error (%) MHz 10 MHz Fi. 8. Power efficiencies and error percentae between the model and simulations are plotted as functions of in current for the four-stae chare pump with V = 1.8 V. 5. Conclusion n this work, a theoretical analysis of power efficiency is presented for the four-phase positive chare pump with body potential control to avoid body effects and minimize noise due to PN junction conduction. The compact model well arees with the post-layout simulation results. The maximum errors are always less than 4% for various in currents and supply voltaes. This model should be very helpful for desin of stae number, capacitors and operation frequency of positive four-phase chare pumps. Acknowledements The authors would like to acknowlede Chip mplementation Center (CC) of National Applied Research Laboratories (NARL) of Taiwan for the support in chip desin. This work was supported by National Science Council of Taiwan (NSC 95-1-E and NSC 95-0-E ). Efficiency (%) Number of staes Fi. 9. Power efficiencies versus stae numbers for the four-stae chare pump with output current of 1 µa and V = 1.8 V. References [1] J. Dickson, On-chip hih-voltae eneration NMOS interated circuits usin an improved voltae multiplier technique, EEE J. Solid-State Circuits, SC- 11, 1976, [] G. Palumbo, D. Pappalardo, and M. Gaiti, Charepump circuits: power-consumption optimization, EEE Trans. on Circuits and Systems : Fundamental Theory and Applications, 49, 00, [3] D. Baderna, A. Cabrini, G. Torelli, and M. Pasotti, Efficiency comparison between doubler and Dickson chare pumps, EEE nt. Symp. Circuits Syst.,, Kobe, Japan, 005, [4] M. R. Houe, T. McNutt, J. Zhan, A. Mantooth, and M. M. Mojarradi, A hih voltae Dickson chare pump in SO CMOS, Proc. EEE Custom nterated Circuits Conf., 003, [5] M. R. Houe T. Ahmad, T. R. McNutt, H. A. Mantooth, and M. M. Mojarradi, Desin technique of an on-chip, hih-voltae chare pump in SO, EEE nt. Symp. Circuits Syst., 1, Kobe, Japan, 005,

5 [6] M. R. Houe, T. Ahmad, T. R. McNutt, H. A. Mantooth, & M. M. Mojarradi, A Technique to ncrease the Efficiency of Hih Voltae Chare Pumps, EEE Trans. on Circuits and Systems : Express Briefs, 53, 006, [7] H. Lin, J. Lu and Y.-T. Lin, A new four-phase chare pump without body effects for low supply voltaes, Proc. EEE Asia-Pacific Conference, Taipei, Taiwan, 00, [8] J. Shin,.-Y. Chun, Y. J. Park, & H. S. Min, A new chare pump without deradation in threshold voltae due to body effect, EEE J. Solid-State Circuits, 35, 000,