Convexity-Based Optimization for Power-Delay Tradeoff using Transistor Sizing

Transcription

1 Convexity-Based Optiization for Power-Delay Tradeoff using Transistor Sizing Mahesh Ketkar, and Sachin S. Sapatnekar Departent of Electrical and Coputer Engineering University of Minnesota, Minneapolis, MN Priyadarsan Patra Strategic CAD Labs, Intel Corporation, Hillsboro, OR This paper solves the delay-power optiization proble by eploying accurate optiization techniques. A new class of functions, called generalized posynoials, which is a superset of the set of posynoials, is used to odel the delay and the power. The apping of these generalized posynoials to regular posynoials, which allows the use of existing posynoial solvers, is shown. We show how all constraints representing the circuit can be represented copactly in posynoial for. Finally, the results of power optiization are presented. Introduction It is well known that in the past, trends in perforance, density and power have followed the scaling theory. For these trends to continue, two iportant issues that need special attention are power delivery and power dissipation [1]. Typically, each generation of chips has shown about a 30% reduction in gate delay and about sae or ore reduction in energy dissipation per transition. The total power dissipation can be scaled down by reducing either the supply voltage, frequency or die size, each of which results in reduced perforance. Therefore, the proble of optiization for low power to eet the stringent perforance constraints continues to be a very relevant proble. Several approaches that perfor circuit level optiization for area or power have been published. In [2], the authors published a linear prograing based ethod for gate sizing for powerdelay tradeoffs, using a piecewise linear gate delay odel. Such a odel is siplistic and inaccurate in the present deep subicron regie. In [3], the power optiization proble is solved by transistor sizing and ordering. Power dissipation is odeled accurately by incorporating fanout capacitances and gate transition easure. A pin-delay odel is developed based on the delay odel used in SIS. However, in the absence of any convexity properties, they use heuristic techniques to solve the proble. The evident drawback of eploying a heuristic approach is that there is no guarantee that the solution will be optial, even after application of any refineent techniques. In [4], only transistor reordering is used for the power-perforance optiization, but the iportant aspect of transistor sizing is not considered. Recently an accurate technique for circuit optiization has been presented in [5], using a nonlinear optiization technique. Siulation followed by tie doain sensitivity coputation is used to provide gradients to a nonlinear optiizer. However, drawbacks include the destruction of convexity properties due to transient siulation-based odeling, the need for circuit-level siulation which tends to ake the optiization coputationally intensive, and the pattern dependent nature of the tiing analysis which requires the user to supply the siulation vectors. Thus, although several attepts have been ade to solve the proble, the lack of convexity based techniques tends to keep the results away fro optiality. The solution is to use the odels that posses convexity properties and hence lend theselves to accurate optiization techniques. It is observed in [6] that the Elore odel posses convexity properties, and several transistor sizing techniques have ade use of the this odel [6,7]. However, the Elore odel is inaccurate for deep subicron technologies. Its failure to correctly consider several factors such as transistor nonlinearities, the effect of the position of switching transistor, the input transition ties, and the transistors opposing the transition, are a few of the reasons for its inaccuracy. In [8], we had developed a convex odel for gate delay that overcoes these liitations. For the sake of copleteness, we have included a brief treatent of the odel in section 2. The theoretical underpinning of this odel developent is a result that defines a new class of functions that is shown to work well for odeling circuit delays. This set of functions includes the set of posynoials as a proper subset, and therefore, we refer to these functions as generalized posynoials. In this paper, we show the precise relation between a generalized posynoial prograing proble and a posynoial prograing proble. We illustrate this in Section 4, and show that geoetric prograing solvers ay be used for generalized posynoial progras. This is a powerful result, since we now have a large new class of functions that can accurately capture the delay behavior of a circuit, but ay use conventional fast ethods, which exploit the structure of the proble, for solving the. Before proceeding to present the convex odels, a few words on the iportance of convex optiization are in order. A convex optiization proble involves the iniization of a convex function over a convex set (for definitions of these ters, the reader is referred to [9]). A proble of the type iniize f x (1) such that g i x 0 1 i where R n is the n-diensional real space and x a vector in R n, is a convex prograing proble if f x and g i x 1 i, are convex functions. The advantage of a convex prograing forulation is that the proble is known to have the property that x R n

2 any local iniu is also a global iniu, and efficient optiization algoriths for solving such a proble are available. Therefore, it is desirable to attept to express any optiization proble using a convex forulation, as far as possible, under the caveat that the accuracy of the odeling functions for the obective and the constraints ust be preserved. In the context of transistor sizing, this requires the derivation of convex closed-for expressions for the path delay; as a result, this will satisfy the requireent of relation (1) that each tiing constraint is of the for g i x 0. In [8], where we solve the proble of area optiization, we have incorporated these odels into a TILOS [6] like optiizer. However, the use of heuristics has inherent drawbacks as there can be no guarantee of optiality. For the odel to fully exploit its convexity properties, it is necessary to couple it with accurate atheatical optiizers. In this paper, we show, for the first tie, how these odels lend theselves effectively to traditional posynoial solvers. We show the apping fro generalized posynoials to posynoials which enables these odels to be used with a geoetric prograing optiizer. The transistor size optiization proble is forally stated as iniize Power subect to Delay T spec (2) An iportant contribution of this paper is the accurate solution of this power-delay tradeoff proble. The accuracy stes fro the fact that we use an accurate generalized posynoial odeling fraework coupled with foral optiization techniques. A apping between generalized posynoials and traditional posynoials is shown, so that a fast posynoial solver can be used as the optiization engine. This optiizer, unlike the convex optiizer in [7], requires all constraints to be explicitly listed. We show how this ay be done efficiently while preserving the posynoial nature of all constraints. Finally, we differ fro [8], which uses a TILOS-like heuristic optiizer for area-delay optiization, and we can guarantee a global iniu using this approach. Convex delay odel Delay abstractions and posynoial delay odeling The delay characteristics of the output wavefor at a gate ay be represented by two nubers: (1) the delay, i.e., the difference in the tie when the output wavefor crosses 50% of its final value, and the corresponding tie for the input wavefor. (2) the output transition tie, i.e., the tie required for the wavefor to go fro 10% to 90% of its final value. In uch of the previous work on transistor sizing, the circuit delay has been expressed in the for of a class of functions known as posynoials. A posynoial is a function p of a positive variable x R n that has the for p x n γ i 1 x α i i (3) where the exponents α i R and the coefficients γ R. In the positive orthant in the x space, posynoial functions have the useful property that they can be apped onto a convex function through an eleentary variable transforation, x i e z i. The Elore delay odel used, for exaple, in TILOS [6] and icontrast [7], eployed the following for of expressions for the path delay. D x n x a i i i 1 x n b i i 1 x i K (4) where a i b i K R are constants and, x x 1 x n is the vector of transistor sizes. Equation (4) represents a posynoial function, and hence convex optiizers can efficiently take advantage of the convexity properties of such a delay expression to obtain an optial solution. Notice that the Elore delay expressions are a sall subset of the set of posynoials; specifically they are posynoials whose exponents belong to the set -1,0,1. Generalized posynoials Posynoials and convex functions are a rich class of functions better delay estiates can be obtained by fully exploiting this richness. Here, we describe a generalized posynoial for that is useful for delay odeling and can be proven to have convexity properties. A generalized posynoial function G k x x R n, where k 0 is called the order of the function, is defined recursively as follows: 1. A generalized posynoial of order 0, G 0, is the posynoial for defined earlier: G 0 x n γ i 1 x α i i (5) where the exponents α i R and the coefficients γ R. 2. A generalized posynoial of order k is defined as G k x n γ i 1 α G k 1 i x i (6) where the exponents α i R and the coefficients γ R, and G k 1 i x is a generalized posynoial of order k 1. Specifically, the generalized posynoial of first order, is given by f x γ i ω i l x a i ls s β i (7) where each β i R, each a i ls R, each γ i R, and each ω i l R. The following theore parallels the relationship between posynoials and convex functions, and is proved in [8]. As a consequence of this, we will loosely refer to generalized posynoials as being convex in future discussions. Theore 1: If the range of interest of x is restricted to the positive orthant where each x i 0, then under the variable transforation

3 fro the space x R n to the space z R n given by x i e z i, the generalized posynoial function f of equation (6) is apped to a convex function in the z doain, provided β i 0 for each i. Stripping Equation (7) of its coplicated notation, one ay observe that the ter in the innerost bracket, l 1 ω i l s p 1 xa i ls s, represents a posynoial function. Therefore, a generalized posynoial of first order is siilar to a posynoial, except that the place of the x i variable in Equation (3) is taken by a posynoial. Siilarly, a generalized posynoial of order k uses a generalized posynoial of order k 1 in place of the x i variables in Equation (3). The class of posynoials is, by definition a proper subset of the class of generalized posynoials. Generalized posynoial delay odel The paraeters that have an observable effect on gate delay are the widths of transistors in the gate, input transition tie, and loading capacitance. We refer to these input paraeters as characterization variables. Our ai is to develop a generalized posynoial delay odel which is dependent on all these characterization variables. We attepted the use of several types of functions to achieve the desired levels of accuracy. The general for of expression that provided consistently good results for different gate types is as follows Delay n P x i 1 i 1 β c i i C (8) Here, the x i s are characterization variables, and the c i s, β i s, C, and P s are real constants, referred to collectively as characterization constants. The paraeter is set to either -1 or 1, depending on the variable, as will soon be explained. The proble of characterization is that of deterining appropriate values for the characterization constants. Due to the curve-fitting nature of the characterization procedure (akin to standard cell characterization), it is not possible to ascribe direct physical eanings to each of these ters. However, it can be seen that the gate delay increases as the loading capacitance, the width of the transistor opposing transition, and the input transition tie are increased, and decreases as the switching transistor width is increased, iplying that an appropriate choice for the paraeter for the first three variables is 1, while for the last one it is -1. Note that this is not as restrictive as the Elore for since, aong other things, the β i s and c i s provide an additional degree of freedo that was not available for the Elore delay for. A two-step ethodology is adopted to coplete the characterization. In the first step, a nuber of circuit siulations are perfored to generate points on a grid. In the second, a leastsquares procedure is used to fit the data to a function of the type in Equation (8). A series of siulations is perfored to collect the experiental data using the HSPICE circuit siulator. Since the nuber of points increases exponentially with an increase in Gate Delay Output Transition Mean Deviation Inv Rise 0.31% 2.83 % Fall 1.29 % 2.82 % Nor2 Rise 1.82 % 2.56 % Fall % 5.06 % Nand2 Rise 5.18 % 6.17 % Fall % 3.58 % Nor3 Rise 0.24 % 1.76 % Fall 24.2 % 7.64 % Nand3 Rise 9.21 % 5.98 % Fall 1.26 % 2.29 % AOI3 Rise 5.21 % 6.38 % Fall 0.86 % 6.27 % Table 1: Accuracy of the delay characterization approach nuber of variables, udicious pruning is applied to the characterization space. The deterination of the characterization constants was perfored by solving the following nonlinear progra that iniizes the su of the squares of the percentage errors over all data points. N 2 D esti i D iniize actual i (9) i 0 D actual i Here, N is the nuber of data points, and D esti i and D actual i, respectively, represent the values given by Equation (8), and the corresponding easured value at the i th data point. This nonlinear prograing proble is solved using the MINOS optiization package [10] to deterine the values of characterization constants. For a library-based design, a full characterization of all cells can be carried out and its coplexity is coparable to the coplexity of characterizing the library using any other eans. For general full custo designs, the nuber of SPICE data points to be generated for the curve fit increases exponentially with the nuber of characterization variables. It is coputationally expensive to perfor such a large nuber of siulations and hence an alternative strategy is suggested. We precharacterize a set of logic structures such that any gate can be apped to one of the eleents of this set with soe acceptable loss of accuracy. It is iportant to ephasize that the use of these apping strategies only serves to reduce the coplexity of the characterization procedure. If one is willing to invest the CPU tie required to perfor the characterizations for each gate type, then this procedure is unnecessary. Gate delays are affected by the position of the switching transistor because of the discharging of internal capacitances, and the developent of separate priitives for different switching scenarios is necessary to tackle this issue. We developed a set of logic structures that can odel all the static gates, including coplex gates and sequential eleents, with acceptable accuracy. Details about the characterization procedure and the set of logic structures used for the precharacteri-

4 zation are provided in [8]. Table 1 shows results of odel validation on various gates. The odel delay values are copared with those obtained by using SPICE. The results show that all the gate delay odels have acceptable accuracy. For the proble to be posed as a convex prograing proble it is necessary to prove that the delays of individual paths satisfy the convexity properties. The proof is oitted fro the discussion here, and interested readers are referred to [8]. Power dissipation odel In this paper we consider dynaic power dissipation. The switching power dissipation odel we use is given below. P isw 1 2 V 2 C i TD i (10) where P isw is the average switching power dissipation, V is power supply voltage, C i is the output capacitance, and TD i is the transition density, all corresponding to gate n i. The transition density is defined [11] as li T n T T, where n T represents the nuber of transitions the gate perfors in tie T. The use of transition density allows a gate with lower switching probabilities to be sized larger. The short circuit power is known to be dependent on the input transition tie to a great extent, and hence can be controlled by placing constraints on the input transition tie for each gate. With proper constraints on the input transition tie, the short circuit power is no ore than 10% to 20% of the total power. It will be shown in next section that the transition tie, τ i, and the loading capacitance, C i, can be expressed in ters of generalized posynoials and hence equation (10) is also a generalized posynoial. Although we recognize the iportance of leakage power in the deep subicron regie in the future, the rationale behind considering only the dynaic power is that this power continues to account for the aor percentage of total power. The proof of convexity of circuit power dissipation is siilar to that of the proof of convexity of path delay and the details can be found in [8]. Proble forulation in detail Traditionally posynoial progras have been solved by using geoetric optiizers. In this work, we have used generalized posynoials to odel the gate delay and power dissipation. While these functions are provably equivalent to convex functions, a precise relationship between generalized posynoial prograing probles and posynoial prograing probles would perit the use of geoetric optiizers to solve the proble forulated here. In this section, we describe a technique for transforing the set of delay constraints described by generalized posynoials into a posynoial for. Conversion of generalized posynoials to posynoials As will be shown shortly, the transforation is carried out by the introduction of additional variables. Consider the constrained generalized posynoial below: γ i ω i l x a i ls s β i D req (11) where D req is the required delay tie, and β i 0 i. Note that the ter in the parenthesis is a regular posynoial. If we substitute that posynoial by the variable y, the result is the constraint β γ i y i D req (12) It is well known that any constraint where a posynoial function is required to be less than or equal to a constant, is equivalent to a convex set under the variable transforation; we will refer to such a constraint as a posynoial constraint. However, the above substitution also requires that the following equality ust be satisfied: ω i l x a i ls s y (13) This equality can be represented by a pair of inequalities, only one of which is a posynoial constraint. This iplies that the constraint set is no longer transforable to a convex set in the x and y variables. We will now ake use of a subtle observation. If we relax the equality in (13) into a inequality, then for any variable assignent that satisfies the relaxed set of constraints, since γ i 0 and β i 0, it ust be true that γ i ω i l x a i ls s β i β γ i y i (14) In conunction with constraint (12), this iplies that the constraint (11) ust be satisfied. Therefore, we ay replace each such generalized posynoial constraint of order 1 by the set of inequalities given by γ i y β i D req ω i l x a i ls s y (15) It is instructive to note that this substitution technique ay be used, in general, for generalized posynoials of order k. This is easily seen, since the above procedure reduces an order k generalized posynoial constraint to an order k 1 generalized posynoial constraint; this process ay be carried out recursively until posynoial constraints are obtained.

5 Introduction of interediate variables As entioned in section 2, the path delay can be proved to be a convex function. However, the nuber of input to output paths increases exponentially with an increase in the nuber of gates in the cobinational logic. We avoid path enueration by the introduction of interediate variables. For each gate, n i, we introduce the following variables: D ir : Arrival tie at the output of gate n i for the rise transition at the output. D i f : Arrival tie at the output of gate n i for the falling transition at the output. τ ir : Rise transition tie at the output of gate n i. τ i f : Fall transition tie at the output of gate n i. In addition, we introduce variables odel the pin to pin delay. D i r represents the delay fro gate n i to gate n for the rise transition at the output of gate n. Siilarly, D i f represents delay fro gate n i to gate n for the fall transition at the output of gate n. To illustrate the constraint foration, consider a subcircuit shown below. A B Figure 1: An exaple circuit Then the constraints related to gate C are, D a f D ar D b f D br D acr D ac f D bcr D bc f C D cr 1 D c f 1 D cr 1 D c f 1 (16) The above set of equations represents the constraints on the arrival tie at the output of the gate C. All the gates are assued to be inverting, but siilar equations can be derived if noninverting gates are used. These equations along with the equations resulting fro the conversion of generalized posynoials corresponding to D acr D ac f D bcr D bc f, to regular posynoials, and the constraints iposed on the output delay, for the coplete set of posynoial equations to be solved by the geoetric optiizer. Experiental Results We have ipleented the transistor sizing optiization tool which integrates constraint generation progra and generalized posynoial solver. Our constraint generation progra writes the obective function and constraints in the generalized posynoial for. For optiization we used the new proprietary Generalized Posynoial Optiizer fro Intel for any of our circuits. This solver Circuit Transistor Dout spec τout spec Power Count (ps) (ps) (w) inv c s cob cob s Table 2: Results of sizing various circuits is extreely efficient since it utilizes the properties of geoetric progras to arrive at a solution. We have optiized several circuits for power, placing constraints on the input-to-output delay. We optiized the circuits for varying target delay and output transition tie constraints. The results are tabulated in the Table 2. First two coluns give the test circuit nae and transistor count. Third colun titled Dout spec represents the input-to-output delay constraint, while the fourth colun titled τout spec represents the transition tie constraint placed on the output. Last colun represents the power obtained on optiization. The execution ties of optiization, using geoetric progra solver, vary fro about a second, for very sall circuits, to about 8 inutes, for oderately sized circuits. As expected, the power dissipation increases as the constraints are ade tighter. Conclusion and future work We have presented a generalized posynoial delay odel for CMOS gates that is better suited for odern technologies than the Elore odel, but aintains the convexity properties. We have shown the use of the odel in the context of optiization for low power. We have presented a new apping technique that can be used to convert generalized posynoials to regular posynoials enabling the use of conventional atheatical optiizers. Results show that in addition to the useful property of convexity,

6 the odel is also coputationally efficient. In future we plan to incorporate leakage power and present an approach that is suitable for future technologies where leakage current can no longer be neglected. Acknowledgeents: [10] Departent of Operations Research, Stanford University, MINOS 5.4 USER S GUIDE, [11] F. N. Na, Transition density: A new easure of activity in digital circuits, IEEE Transactions on Coputer-Aided Design, vol. 12, pp , Feb We would like to thank Professor Michael Todd at Cornell University for his useful coents. References [1] V. De and S. Borkar, Technology and design challenges for low power and high perforance, in Proceedings of the International Syposiu on Low Power Electronics and Design, pp , [2] M. R. C. M. Berkelaar, P. H. W. Buuran, and J. A. G. Jess, Coputing the entire active area/power consuption versus delay trade-off curve for gate sizing with a piecewise linear siulator, in Proceedings of the IEEE/ACM International Conference on Coputer-Aided Design, pp , [3] C. H. Tan and J. Allen, Miniization of power in VLSI circuits using transistor sizing, input ordering, and statistical power estiation, in Proceedings of the 1994 International Workshop on Low Power Design, pp , [4] S. C. Prasad and K. Roy, Circuit optiization for iniization of power consuption under delay constraint, in Proceedings of the 1994 International Workshop on Low Power Design, pp , [5] A. Conn, I. M. Elfadel, W. W. Molzen, P. R. O Brien, P. N. Strenski, C. Visweswariah, and C. B. Whan, Gradientbased optiization of custo circuits using a static-tiing forulation, in Proceedings of the ACM/IEEE Design Autoation Conference, pp , [6] J. Fishburn and A. Dunlop, TILOS: A posynoial prograing approach to transistor sizing, in Proceedings of the IEEE International Conference on Coputer-Aided Design, pp , [7] S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, An exact solution to the transistor sizing proble for CMOS circuits using convex optiization, IEEE Transactions on Coputer-Aided Design, vol. 12, pp , Nov [8] M. Ketkar, K. Kasasetty, and S. S. Sapatnekar, Convex delay odels for transistor sizing, in Proceedings of the ACM/IEEE Design Autoation Conference, pp , [9] D. G. Luenberger, Linear and Nonlinear Prograing. Reading, Massachusetts: Addison-Wesley, 2nd ed., 1984.