Modeling of Passive Elements with ASITIC. Prof. Ali M. Niknejad Berkeley Wireless Research Center University of California, Berkeley

Transcription

1 Modeling of Passive Eleents with ASITIC Prof. Ali M. Niknejad Berkeley Wireless Research Center University of California, Berkeley

2 Outline of Presentation ASITIC Overview Electroagnetic Solution Approach Partial Inductance Matrix Eddy Current Losses Capacitance Matrix Experiental Validation Broadband Modeling Liitations and Future of ASITIC

3 Applications of Passives for RFICs Narrow-band ipedance atching Tuned loads resonant tank) Low noise degeneration and feedback Natural/artificial transission lines Linear filters high dynaic range) Fully differential circuits Low voltage/low power design

4 The Goal of ASITIC δω ω 0 Technology File Layout Electrical Specs Model Solve the analysis, design, and odeling probles Achieve accuracy over a wide frequency range Perfor analysis of structures quickly for optiization Retain flexibility to work with arbitrary structures Create a design environent Generate siple copact odels

5 OpenGL ASITIC Block Diagra Display Hardware Input Log Files Tech File Graphical Interface CoLine Interface TechFile Processing Geo Engine Calc Engine Parser DRC Meshing Engine Green Function Table Lookup Nuerical Back-End LAPACK BLAS FFTW QUADPACK

6 Planar Inductor/Transforer Layout circular spiral inductor syetric center-tapped balun transforer

7 3D Inductor/Transforer/Capacitors 3D structures allow ore flexibility Shunting several spirals lowers series loss Series interconnection of spirals can enhance agnetic field and provide nearly n increase in inductance due to tight agnetic coupling New transforer topologies are also possible Multi-layer finger capacitor structures offer high density

8 High Freq. Effects Over Si Substrate radiation proxiity effects due to presence of nearby segent segents couple agnetically and electrically through oxide/air current crowding at edge due to skin effect substrate injection substrate current by ohic, eddy, and displaceent current substrate tap nearby causes lateral currents

9 Efficient/Accurate Method of Analysis Electrically Short Segent Distributed Inductance and Resistance Substrate Loss Model short etal segent as luped RLC Circuit Metal segents are linked capacitively and inductively Set up node equations for coplete syste and solve Method equivalent to solving Maxwell s equations Reference: A. Ruehli, H. Heeb, MTT, July 9 Partial Eleent Equivalent Circuits PEEC)

10 Substrate Currents Fro Maxwell s equations Coulob Gauge): A = jωµεe + µ J = ω µεa 13 radiation = jωµε ' jωa φ) jωµσa 13 jωεµ φ 1443 µσ φ 13 eddy currents disp. conduction Neglect radiation as long as Displaceent and conduction current are curl-free Losses due to conduction currents accounted for by solving: ρ jσ φ = ε ' = ε + ε ' ω Losses due to eddy currents accounted for by solving: A l ax = << λ jωµσa

11 Current Constriction in Spiral Center Current Density 1 GHz 5 GHz L=00 µ W=10 µ S = 10 µ N = 5 L=00 µ W=10 µ S = 1 µ N = 5

12 Partial Inductance Matrix Calculation Current constriction occurs at HF Current concentrates along the outer skin of a conductor Proxiity of other conductors also influence the distribution Inner turns in a spiral have ost current constriction Exaple: Use S=1 µ spacing on and S=10 µ Noralized Inductance S = 10u S = 1u Noralized Resistance S = 10u S = 1u Lac / Ldc Rac / Rdc GHz) GHz) L dc = 5. nh and.6 nh

13 Bulk Eddy Current Losses Reference: A. M. Niknejad and R. G. Meyer, MTT, January 01 substrate space A free A z y x A + = ),, ) Γ = 0 0,, ) )cos, ) ~ 0 d x x w K e j Z y y S M j i π µ ω ) ) tanh ) ) ) tanh ) ) t t e y = Γ < Γ )] I[ li 0 0 ) y e + = Γ Due to linearity in Maxwell s equations: Note that free-space contribution doinates inductance Substrate ter doinates losses Use existing 3D techniques to approxiate inductance Use D forulation to approxiate loss: For single layer substrate integral has analytic for): For two layer substrate use nuerical integration):

14 Capacitance Matrix Calculation Solve 3D Poisson's equation over ulti-layer substrate Green function used to find ipedance atrix Green func is calculated in efficient anner using DCT b a ρ Ν,ε Ν source point field point ρ k, ε k ρ j, ε j ρ 0, ε 0 Reference: A. M. Niknejad, R. Gharpurey, R. G. Meyer, TCAD, April 98

15 Measureent and Siulation over a Conductive Substrate S11eas si S1eas S11eas si GHz GHz Device self-resonance frequency: 4.5 GHz si at 4.15 GHz) Measureents perfored using GSG air co-planar probes Processed with HP 8719C Network Analyzer 100 MHz - 14 GHz)

16 Extracted Device Inductance and Series Loss Leas Lsi 15 0 Reas R no eddy) Rsi GHz GHz Device pi-paraeters equivalent to s-paraeters Inductance and resistance calculated using real/iag part of s 1 Inductance decrease due to capacitive currents at hf Resistance increase doinated by eddy current losses

17 Extracted Device Quality Factor Q Qeas Qsi Q no eddy) GHz Negative Q eans device is acting capacitively Device Q predicted 40% higher without eddy currents

18 Broadband Copact Modeling C s L 0 C s R 0 L 0 / C c R 1 / L / L 1 / C ox C ox R 0 / R sub C sub R sub R sc C sub Reference: Yu Cao et. al., CICC 00 Conventional π odel has physical roots Model works well over a narrow band Model cannot capture freq. dep. skin-effect and proxiity effects: L f ) R f ) Physically derived -π odel can fit data over a wider frequency range

19 ASITIC Hoepage Current Release: Grackle Supported Platfors: Linux, Windows 000/NT HP-UX, SunOS Online Help, FAQ, Install Guide Quickstart, Saple Sessions Your feedback is very iportant!

20 Liitations and Future of ASITIC Copute Conductor Thickness in Capacitance Include Reflected Substrate Inductance Autoatically generate wideband odels Divorce Geoetric Layout and Electrical Model Allow direct iporting GDSII and CIF files Work on Full-Chip RF Extraction Work with Board and Package Environent