Journal of Chemical and Pharmaceutical Research, 2014, 6(2): Research Article

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1 Available online Journal of Cheical and Pharaceutical Research, 214, 6(2):77-82 Research Article ISSN : CODEN(USA) : JCPRC5 Design of experients of electroigration reliability for solder joints of a wafer level chip scale package Yuanxiang Zhang and Yingyu Ji College of Mechanical Engineering, Quzhou University, Quzhou, China ABSTRACT Electroigration (EM) in solder joints under high current density has becoe a critical reliability issue for the future high density icroelectronic packaging. This paper presents a prediction ethod for electroigration (EM) induced void generation of solder joint in a wafer level Chip Scale Package (WL-CSP) structure. The driving force for electroigration induced failure considered here includes the electron wind force, stress gradients, teperature gradients, as well as the atoic density gradient. To understand ipact of the under ball etallurgy (UBM) geoetry and solder bup shape on electroigration reliability, the EM siulation for WL-CSP structure is perfored to get tie to failure (TTF) based on the full factorial design of experients (DOE) by using 3D finite eleent analysis. The analysis of the ipact of under ball etallurgy and solder bup geoetry on the void generation and TTF is presented. Key words: Electroigration; tie to failure; solder joint; void prediction INTRODUCTION It is well known that, as the electronics industry continues to push for high perforance and iaturization, the deands of higher current densities increases. This ay cause electroigration failures, not only in integrated circuit (IC) interconnects but also in solder joints of IC packages. [1].The solder bup under a flip CSP or a WL-CSP has a UBM on the chip side and a bup pad on substrate side. One challenge we face as the chip size shrinks, is how to design a robust UBM and solder bup shape to reduce the electroigration failure and to obtain the longer tie to failure (TTF) life in a optiization solution. In a solder syste of a flip chip or a CSP, the failure phenoenon of electroigration has been found inside the solder joint which is adjacent to the under bup etallization (UBM) layer [2]. Due to the unique geoetry of a flip chip, current crowding occurs at the contact interface between the solder bup and the UBM. The current crowding and the high teperature at the contact interface between the solder bup and the UBM causes the foration of voids [3]. The void propagates across the entire solder/ubm interface and leads to failure finally. Therefore, how to design the UBM geoetry with different UBM ri angles to iprove the failure life of EM is essential. In order to ake the failure life of the package structure as longer as possible, soe studies tried to optiize the ball shapes at ball level, such as the double-bup [4]. It also indicated that the double-bup WLP had uch better reliability than standard WLP packages under theral cycling. But whether it has a better EM life needs to be studied further. This paper studies electroigration induced void generation in a WL-CSP structure based on the previous work [5-6]. The electronicigration forulation considering the effects of the electron wind force, stress gradients, teperature gradients, and the atoic density gradient has deonstrated reasonable predicted TTF results as copared to electronicigration test results. For understanding the ipact of the UBM geoetry and solder bup shape on electroigration reliability, this paper proposes a paraetric siulation for UBM geoetry with different UBM ri angle, diaeter and thickness, as well as different solder bup shape. 77

2 Yuanxiang Zhang and Yingyu Ji J. Che. Phar. Res., 214, 6(2):77-82 BASIC ELECTROMIGRATION FORMULATION Electroigration is a diffusion process which is controlled by asstransportation. The tie dependent evolution equation of the local atoic density can be given as c q + = (1) t Where c is the noralized atoic density (NAD), c=c/c, C is the actual atoic density and C is the initial (equilibriu state) atoic density in the absence of a stress field, t is the tie; q is the total noralized atoic flux. The atoic density includes electron windforce, stress gradients, teperature gradients, and the atoic densitygradient, respectively. The total noralized atoic flux can be written by [5] cd cd T cd q = q Z e Q D c c ( T ) Ew + qth + q S + q C = ρ j + Ω σ = F, σ, j, D c (2) kt kt T kt where D D T D F( T, σ, j, ) = Z eρj Q + Ω σ (3) kt kt T kt where k is Boltzann s constant; e is the electronic charge; Z is the effective charge which is detered experientally; T is the absolute teperature; ρ is the resistivity which is calculated as ρ = ρ ( ( )) 1+ α T T, where αis the teperature coefficient of the etallic aterial, ρ is the resistivity at T ; j is the current density vector; Q is the heat of transport; Ωis the atoic volue; σ ( ) = σ 1 + σ 2 + σ 3 / 3 is the local hydrostatic stress, where σ 1, E σ 2, σ 3 are the coponents of principal stress; D is the effective ato diffusivity, = a D D exp, where E a is the kt activation energy, D is the effective therally activated diffusion coefficient. For the EM evolution equation (Eq. (1))on any enclosed doain V with the corresponding boundaryγ, the atoic flux boundary conditions (B.C.) of etal interconnects can usually be expressed as q n = on Γ (4) q For blocking boundary condition, q = on Γ (5) For the initial tie, the noralized atoic density for all nodes is c =1 (6) The above equations and boundary conditions constitute the boundary value proble that governs the atoic transport during EM. This boundary value proble ust be solved accurately in order to adequately describe the continuous ato redistribution and to capture the realistic kinetics of void nucleation and growth as a function of the interconnect architecture, segent geoetry, aterial properties, and stress conditions. Different fro previous ethodology, the effect of atoic density gradient is not neglected; it is included in equation (1). In order to perfor the analysis of electroigration, coupled diffusion and theral-electric-structural analysis is needed. The EM void evaluation siulation consists of the siulation part for an incubation period and a void growth period. In the siulation for the incubation period, at first, the initial distributions of current density and teperature in the interconnect structure are obtained by the 3D finite eleent ethod analysis based on the ANSYS platfor. Then, atoic density redistribution in the interconnect structure are solved based on the atoic density redistribution siulation code written in a FORTRAN code [5-6]. 78

3 Yuanxiang Zhang and Yingyu Ji J. Che. Phar. Res., 214, 6(2):77-82 Assue that there is a critical noralized atoic density for void initiation, When the noralized atoic density c is less than or equal to c ( c c c, and for hillock initiation, c. ax ), a void will appear [7]. Conversely, when the noralized atoic density c is greater than or equal to c ( c c ax ax ), a hillock will be generated. For the solder aterial, a criterion for void generation is selected to be c =.85. The work in this paper can show the location of hillock, but it has not yet considered the foration of a hillock. In the siulation procedure of the void growth period, once the average atoic density value of the eleents are less than the critical atoic density for void initiation c, the corresponding eleents will be killed ("eleent death") and the structure need to be reconstructed. To achieve the "eleent death" effect, ANSYS do not actually reove "killed" eleents. Instead, it deactivates the by reducing the eleent aterial attribute, such as the elastic odulus and resistivity, by a factor of1.e-6.in the seiconductor industry for a WL-CSP bup failure criterion, a 15% increent in electrical resistance of the bup is usually considered EM failure. This criterion is used in this work to get the final TTF. EM FAILURE ANALYSIS FOR SOLDER JOINTS IN WL-CSP Gee et al. [3] have done the electroigration test for SnAgCu and SnPb solder joints in a WL-CSP package. The package has 36 solder bups with 5 µ pitch. The diension of silicon chip is Solder bups are.15 in diaeter and.2 in height. The exterior 2 solder bups are assued to connect with each other in a daisy chain as shown in Fig.1. Sub-odel technique in ANSYS is introduced to get the better response of the electronic igration. The global theral-electric coupled field odel uses Solid69 eleent and the global stress odel uses Visco17 eleent for solder bups and Solid45 eleent for the reaining parts of the odel. Firstly, the global structure is odeled using relative coarse eleents firstly. Secondly, a refined theral-electric coupled field sub-odel and a refined stress sub-odel with UBM (Al/NI(V)/Cu) layer are then constructed as shown in Fig. 2. Fig. 1: WL-CSP package odel: (a) WL-CSP package structure; (b) local view Fig. 2: Sub-odel of WL-CSP structure: (a) solid sub-odel and its esh; (b) local view of solder bup The solder bup aterial is 95SnAg4.5Cu.5. The related theral echanical and electrical constants used in the siulation are taken fro refs. [6, 8].The electroigration paraeters of solder bups are selected fro the previous refs [8-1, 18]. In addition, for the solder bup EM void failure, = c. 85 and c = are used. ax Fig.3 shows the electron flow direction in a global odel. The free convection boundary condition is applied with 17 W/ 2 ºC fil coefficient and 5ºC bulk teperature. Three different current 1.6A, 1.7A and 1.8A are applied. 79

4 Yuanxiang Zhang and Yingyu Ji J. Che. Phar. Res., 214, 6(2):77-82 Fig. 3: Electron flow direction in a global odel Fig. 4: Teperature and current density distribution of solder bup Fig. 5: Void foration between siulation solutions and test results Fig. 6:Coparison of TTF between siulation solutions and test results Fig.4 shows the teperature and current density distribution of the solder bup under current 1.6A.Fro the Fig.4, it can be seen that the current crowding occurs at the contact interface between the solder bup and Al line at which a large portion of the electron enters the solder bup. The current density at the corner is approxiately one order of the agnitude higher than the average current density in solder bups. Fig. 5 shows void shape and location coparison between siulation and test. Fro the Fig.5, we can see the void by siulation appears at the solder bup adjacent the UBM layer which is siilar to the void and failure ode shown in the test [3].Based on atoic density redistribution algorith, TTF of CSP structure under high current density can be calculated. A coparison of the siulation results for TTF and the previous experiental test results is also presented in Fig.6. The results show 8

5 Yuanxiang Zhang and Yingyu Ji J. Che. Phar. Res., 214, 6(2):77-82 that the siulated TTF data agree well with the tested ean tie to failure (MTTF). There is soe difference in the current of 1.65A, this ight be either due to the odeling setting up and selected paraeters need to be further validated or the error of the test syste. PARAMETER SIMULATIONS FOR UBM AND SOLDER BUMP The paraeters of DOE include UBM ri angle, UBM diaeter, and UBM thickness and solder bup shape. Fig.7 gives the scheatic three different UBM ri angles. Table 1 lists the total paraeters of DOE. The current 1.7A is applied in this section. Table 1: Design paraeters of DOE Design paraeters Value UBM ri angle º, 15º, 3º, 45º, 6º, 75º, 9º UBMdiaeter.9,.11,.125 UBMthickness.16,.212,.424 Solder bup shape Ball, Cylinder, Square Cube, Double ball Fig.8show the TTF and voidwith different UBM ri angle. It shows that the UBM geoetry has a significant ipact on the solder bup void growth and TTF. The 75 UBM ri angle get the longest the solder bup TTF, the UBM and the 9 UBM ri angle is the poor structures to withstand the electroigration failure. Fig.8 alsoshows voids with three UBM ri angles. It is obsevered that all these voids appear in the solder bup adjacent to the UBM layer.fig.9 shows the ipact of UBM diaeter on TTF. As the UBM diaeter increases, the EM life also increases. Fig. 1 shows the ipact of UBM thickness on TTF with 3 UBM ri angle. Fro Fig. 1, it can be observed that the thicker of UBM, the longer of the TTF life. α = α = 6 α = 9 Fig.7: Scheatic diagra of UBM ri angle 3 24 TTF(h) UBM ri angle( ) Fig.8: TTF and void with different UBM ri angle TTF(h) UBM diaeter() Fig.9: TTF and void with different UBM diaeter 81

6 Yuanxiang Zhang and Yingyu Ji J. Che. Phar. Res., 214, 6(2): TTF(h) E+ 1.E-3 2.E-3 3.E-3 4.E-3 5.E-3 Thickness of UBM() Fig.1: TTF with different UBM thicknesses In order to study the ipact of shapes of ball on EM TTF life, this paper selects cylinder, cube and single and dual balls. Those shapes keep the sae volue with the sae height (except dual ball). The dual ball has twice the volue of a single ball. Table 2 gives the TTF coparison with different bup shapes. Fro the Table 2 it can be seen that the cylinder bup has the longest TTF while dual bup gives the shortest TTF. Table 2: TTF of different Solder bup shapes Solder bup shapes TTF(hours) Spheroid Cylinder Cube Double ball CONCLUSION The siulation results show that the UBM geoetry and bup shape have significant ipact on the solder bup void growth and TTF. There is a best solution for UBM ri angle (75 in the bup layout of this paper). A thicker and larger diaeter UBM will help to produce the longer bup TTF. Siulation also shows that if we keep the sae shape of solder bup, the larger (and higher) the solder bup, the longer the TTF. In addition to that, different bup shapes in dual ball, ball, cylinder and cube are studied. The results show that the cylinder bup gives the longest TTF life following by the cube bup and the single ball bup, while the double ball bup is found to have the shortest TTF. It is the weakest bup to withstand the electroigration failure. Therefore in WL-CSP design, a robust design against electroigration should consider optiized UBM and bup geoetry paraeters to get the best solution, like selecting a thicker UBM, shorter bup pitch, lower bup and cylindrical bup shape. Acknowledgents This research was funded by Zhejiang Provincial Natural Science Foundation (No.LQ13E514) and Scientific Research Project of Zhejiang Provincial Education Departent (Y ). REFERENCES [1] K Croes, C J Wilson, M Lofrano, et al. Microelectronic Engineering, 211, 88(5), [2] S H Chae, X Zhang, K H Lu, et al. Journal of Materials Science: Materials in Electronics, 27, 18, [3] S Gee, N Kelkar, J Huang, et al. Proceeding of InterPACK25, 25, [4] X J Fan, Q Han. Proceeding of 1th Electronics Packaging Technology Conference, 28, [5] J P Jing, L H Liang, M Guang. ASME Journal of Electronic Packaging, 21, 132(1),1-7. [6] Y Liu, L H Liang, S Irving, et al. Microelectronics Reliability, 28, 48(6), [7] K Sasagawa, M Hasegawa, M Saka, et al. Journal of Applied Physics, 22, 91(11), [8] R Darveaux. ASME Journal of Electronic Packaging, 22, 124(3), [9] C Basaran, M Lin. International Journal of Solids and Structures, 27, 44(14-15), [1] C Basaran, M Lin. Mechanics of Materials, 28, 4(1-2),