ACCURATE, HIGH SPEED PREDICTIVE MODELING OF PASSIVE DEVICES

Transcription

1 ACCURATE, HIGH SPEED PREDICTIVE MODELING OF PASSIVE DEVICES A Thesis Presented to The Academic Faculty by Ravi Poddar In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy In Electrical and Computer Engineering Georgia Institute of Technology January 1998 Copyright 1998 by Ravi Poddar

2 ACCURATE, HIGH SPEED PREDICTIVE MODELING OF PASSIVE DEVICES Approved: Martin A. Brooke Phillip E. Allen Joy Laskar Date Approved ii

3 DEDICATION To My Parents and Grandparents iii

4 ACKNOWLEDGEMENT I would like to thank my thesis advisor, Dr. Martin A. Brooke, for his constant support, flexibility, flow of ideas, and patience during this research program. He has allowed me to explore new ideas, but has constantly helped me stay focused on the main objectives of the research work. His strong affiliations with other research groups, including the microwave applications, optoelectronics and MEMS groups, have allowed me to interact with and gain insight from student members and faculty from those areas. I would especially like to thank Dr. Joy Laskar of the microwave applications group and his graduate students for their assistance in the use of high frequency test equipment, which has been fundamental to the verification of this work. I would also like to thank the many students of the various groups and the Microelectronics Research Center staff for assistance in fabrication of devices, and general help and advice. Last but not least, I would like to thank my family for their constant support and encouragement during this research program. iv

5 TABLE OF CONTENTS DEDICATION...iii ACKNOWLEDGEMENT...iv TABLE OF CONTENTS...v LIST OF FIGURES...xiii SUMMARY...xxviii CHAPTER I Introduction Thesis Organization...4 CHAPTER II Background Introduction Analytical Models Measurement Based Models Numerical Full-Wave Methods Discussion Summary...14 CHAPTER III Passive Device Modeling Methodology Introduction Design and Modeling Flowchart Building Blocks...20 v

6 3.4. Build Block Definition Test Structures Test Structure Equivalent Circuit Extraction Case Study: RLC Filter Frequency Resolution and Extraction Example Case Study: Partial Element Equivalent Circuit (PEEC) Extraction and Sensitivity Analysis Case Study: 4 Segment RLC Circuit Extraction and Sensitivity Analysis Library Based Implementation Summary...46 CHAPTER IV Modeling of Resistors Introduction Modeling Procedure Detailed Resistor Modeling Procedure Processing and Measurement Modeling and Parameter Extraction Sensitivity Analysis Model Extraction Results Summary...79 CHAPTER V Modeling of Interdigital Capacitors Introduction...80 vi

7 5.2. Modeling Procedure Detailed Modeling Procedure Processing and Measurement Modeling and Parameter Extraction Sensitivity Analysis Model Extraction Results Conclusion CHAPTER VI Modeling of Planar Spiral Inductors Introduction Modeling Procedure Detailed Modeling Procedure Method-of-Moments Simulation Modeling and Parameter Extraction Sensitivity Analysis Model Extraction Results Conclusion CHAPTER VII Modeling of Fully 3-Dimensional Passive Device Introduction Modeling Procedure Detailed LTCC Structure Modeling Procedure Solenoid Inductor and Gridded Plate Capacitor Building Blocks vii

8 7.4. Solenoid Inductor and Gridded Plate Capacitor Test Structures Structure Fabrication and Measurement Modeling and Parameter Extraction Sensitivity Analysis Model Extraction Results Summary CHAPTER VIII Conclusions and Recommendations Summary of Research and General Conclusions Discussion Test Structure Design Number of Test Structures Simultaneous Optimization Recommendations Recommendations for Building Blocks Recommendations for Test Structure Design Recommendations for Statistical Modeling Recommendations for Parameter Extraction and Optimization Recommendations for Implementation Final Conclusions APPENDIX A Sensitivity Analysis of 4 Segment RLC Circuit A.1. Introduction APPENDIX B Current Flow Visualization Software viii

9 B.1. Introduction B.2. Algorithm B.2.1. Network Solution Methodology B.2.2. Mathematical Implementation B.3. Visualization Results B.4. Source Code B.4.1. Fundamental Structure Geometry Input and Matrix Generator B.4.2. Input and Output Point Definition Routine and Solver B.4.3. Linear Solver Routine B.4.4. Nodal Elimination Routine APPENDIX C HSPICE CIRCUIT OPTIMIZATION C.1. Introduction C.2. Input File Parameters C.2.1. Desired Goal Definition C.2.2. Definition of Circuit Parameters for Optimization C.2.3. Criteria for Successful Optimization C.2.4. Optimization Execution C.3. Complete Optimization Control File Example C.4. Simultaneous S-parameter Circuit Optimization APPENDIX D Circuits and Data for Serpentine Resistor Modeling D.1. Introduction D.2. Test Structure D.2.1. Circuit Optimization Input File ix

10 D.2.2. Measured S-Parameter Data D.3. Test Structure D.3.1. Circuit Optimization Input File D.3.2. Measured S-Parameter Data D.4. 9-Segment Resistor D.4.1. Circuit File D.4.2. Measured S-Parameter Data APPENDIX E Circuits and Data for Interdigital Capacitor Modeling E.1. Introduction E.2. Test Structure E.2.1. Circuit Optimization Input File E.2.2. Measured S-Parameter Data E.3. Test Structure E.3.1. Circuit Optimization Input File E.3.2. Measured S-Parameter Data E.4. Test Structure E.4.1. Circuit Optimization Input File E.4.2. Measured S-Parameter Data E Segment Interdigital Capacitor E Segment Resistor and 10-Segment Interdigital Capacitor Series Equivalent Circuit E.5.2. Measured S-Parameter Data for 10-Segment Interdigital Capacitor..294 x

11 E.5.3. Voltage Magnitude and Phase of RC Series Circuit Terminated in 50 Ohm Resistor APPENDIX F Circuits and Data for Planar Spiral Inductor Modeling F.1. Introduction F.2. Test Structure F.2.1. Circuit Optimization Input File F.2.2. Method-of-Moments S-Parameter Data F.3. Test Structure F.3.1. Circuit Optimization Input File F.3.2. Method-of-Moments S-Parameter Data F.4. Test Structure F.4.1. Circuit Optimization Input File F.4.2. Method-o-Moments S-Parameter Data F.5. 4-Turn Spiral Inductor F.5.1. Circuit File for 4-Turn Spiral Inductor F.5.2. Method-of-Moments S-Parameter Data APPENDIX G Circuits and Data for Low Temperature Cofired Ceramic (LTCC) Structures Modeling G.1. Introduction G.2. Test structure G.2.1. Circuit Optimization Input File G.2.2. S-Parameter Measured Data G.3. Test Structure xi

12 G.3.1. Circuit Optimization Input File G.3.2. Measured S-Parameter Data G.4. Test Structure G.4.1. Circuit Optimization Input File G.4.2. Measured S-Parameter Data G.5. Test Structure G.5.1. Circuit Optimization Input File G.5.2. Measured S-Parameter Data G.6. Solenoid Inductors - 4 Coils, with 6 and 8 Turns per Coil G.6.1. Inductor Equivalent Circuit G.6.2. Measured S-Parameter Data G.7. Capacitor Benchmark Structure G.7.1. Equivalent Circuit G.7.2. Measured S-Parameter Data REFERENCES xii

13 LIST OF FIGURES Figure Design and Modeling Flowchart...19 Figure Uncoupled and coupled PEEC circuits with associated building blocks...23 Figure Interdigital capacitor segment end piece and possible second order (nearest neighbor coupling) equivalent circuit...24 Figure Serpentine resistors designed from the same set of building blocks...27 Figure Test structures for serpentine resistor modeling...29 Figure Test structure for initial guess computation...36 Figure Voltage gain of low pass filter...37 Figure Expanded view of overshoot region in gain response of low pass filter...37 Figure Sensitivity plot of Z 11 for PEEC circuit...40 Figure Circuit for impedance parameter sensitivity analysis...41 Figure Sensitivity analysis of Z 11 for circuit of Figure Figure Sensitivity analysis of Z 21 for circuit of Figure Figure Current distribution plot of serpentine resistor structure...52 Figure Enlarged view of U shaped section of serpentine resistor...53 xiii

14 Figure Current contour plot showing current crowding effects in serpentine resistor...53 Figure Test structures and primitives for meander resistor modeling...54 Figure Photograph of fabricated structures for meander resistor modeling Figure Photograph of predictively modeled 9 segment resistor...57 Figure S 21 and S 11 sensitivity with respect to line inductance in the uncoupled square building block in test structure Figure S 21 and S 11 sensitivity with respect to capacitance to ground in the uncoupled square building block for test structure Figure S 21 and S 11 sensitivity with respect to line resistance in the uncoupled square building block in test structure Figure S 21 and S 11 sensitivity with respect to shunt capacitance in the uncoupled square building block in test structure Figure S 21 and S 11 sensitivity with respect to capacitance to ground in the probe pad building block in test structure Figure S 21 and S 11 sensitivity with respect to line inductance in the probe pad building block in test structure Figure S 21 and S 11 sensitivity with respect to line resistance in the probe pad building block test structure xiv

15 Figure S 21 and S 11 sensitivity with respect to shunt capacitance in the probe pad building block in test structure Figure S 21 and S 11 sensitivity with respect to capacitance to ground in the coupled squares building block in test structure Figure S 21 and S 11 sensitivity with respect to mutual inductance in the coupled squares building block in test structure Figure S 21 and S 11 sensitivity with respect to coupling capacitance in the coupled squares building block in test structure Figure S 21 and S 11 sensitivity with respect to capacitance to ground in the U- shaped building block in test structure Figure S 21 and S 11 sensitivity with respect to line resistance in the U-shaped building block in test structure Figure S 21 and S 11 sensitivity with respect to line inductance in the U-shaped building block in test structure Figure S 21 and S 11 sensitivity with respect to shunt capacitance in the U-shaped building block in test structure Figure Building blocks, equivalent circuits and parameter values for serpentine resistor modeling Figure Measured vs. modeled results for test structure 1. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response xv

16 Figure Measured vs. modeled results for test structure 2. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response...70 Figure Serpentine resistor and associated building blocks...72 Figure Measured vs. predicted results for 9 segment resistor. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response...73 Figure Resistor divider circuit...74 Figure MDS generated vs. predicted results for voltage divider circuit. (a) Voltage magnitude response. (b) Voltage phase response...75 Figure Segment LC circuit with 9 segment resistor used as termination Figure MDS generated vs. predicted results for 6 segment LC circuit with resistive termination. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response...77 Figure MDS generated vs. results using ideal 17.88Ω resistor for 6 segment LC circuit. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response...78 Figure Interdigital capacitor and associated building blocks...84 Figure Contour and indexed color intensity plots of current distribution in ladder shaped structure...85 Figure Contour plot of current in T-shaped section within ladder structure Figure Test structures and building blocks for interdigital capacitor and serpentine resistor modeling xvi

17 Figure Fabricated interdigital capacitor - test structure Figure Fabricated interdigital capacitor 10 segment capacitor predictively modeled...89 Figure Fabricated RC structure predictively modeled...90 Figure S 21 and S 11 sensitivity of test structure 3 with respect to line to line coupling capacitance (CM)...92 Figure S 21 and S 11 sensitivity of test structure 3 with respect to stub to line coupling capacitance (C2) in the shielded stub Figure S 21 and S 11 sensitivity of test structure 3 with respect to line to ground capacitance in the IDC fingers Figure S 21 and S 11 sensitivity of test structure 3 with respect to line to ground capacitance in the shielded stub Figure S 21 and S 11 sensitivity of test structure 3 with respect to line inductance in finger segments...94 Figure S 21 and S 11 sensitivity of test structure 3 with respect to line inductance in shielded stub...95 Figure S 21 and S 11 sensitivity of test structure 3 with respect to line to line mutual inductance between finger segments Figure S 21 and S 11 sensitivity of test structure 3 with respect to line resistance in finger segments...96 xvii

18 Figure S 21 and S 11 sensitivity of test structure 3 with respect to line resistance in shielded stub...96 Figure Building blocks, equivalent circuits, and parameters for IDC and resistor modeling...98 Figure S-parameter measured and modeled results for test structure Figure S-parameter measured and modeled results for test structure Figure S-parameter measured and modeled results for test structure Figure RLC resonant tank circuit Figure Measured and predicted results for 10 segment interdigital capacitor Figure Actual (MDS) and predicted resonator voltage magnitude and phase Figure Spiral inductor and associated building blocks Figure Indexed color intensity plots of current distribution in spiral inductor Figure Contour plot of X and Y directed current gradients showing current crowding in spiral inductor Figure Test structures and building blocks for spiral inductor modeling Figure S 21 and S 11 sensitivity of test structure 1 with respect to line-to-ground capacitance in the uncoupled square building block Figure S 21 and S 11 sensitivity of test structure 1 with respect to line inductance in the uncoupled square building block xviii

19 Figure S 21 and S 11 sensitivity of test structure 1 with respect to line resistance in the uncoupled square building block Figure S 21 and S 11 sensitivity of test structure 1 with respect to shunt capacitance in the uncoupled square building block Figure S 21 and S 11 sensitivity of test structure 2 with respect to line-to-line coupling capacitance in the coupled squares building block Figure S 21 and S 11 sensitivity of test structure 2 with respect to line-to-ground capacitance in the U building block Figure S 21 and S 11 sensitivity of test structure 2 with respect to shunt capacitance in the U building block Figure S 21 and S 11 sensitivity of test structure 2 with respect to line-to-line mutual inductance in the coupled squares building block Figure S 21 and S 11 sensitivity of test structure 2 with respect to line-to-ground capacitance in the coupled squares building block Figure S 21 and S 11 sensitivity of test structure 2 with respect to line inductance in the U-shaped building block Figure S 21 and S 11 sensitivity of test structure 3 with respect to line inductance in the uncoupled squares section of the coupled corner building block Figure S 21 and S 11 sensitivity of test structure 3 with respect to line resistance in the uncoupled squares section of the coupled corner building block xix

20 Figure S 21 and S 11 sensitivity of test structure 3 with respect to shunt capacitance in the uncoupled squares section of the coupled corner building block Figure S 21 and S 11 sensitivity of test structure 3 with respect to line-to-line coupling capacitance in the coupled corner building block Figure S 21 and S 11 sensitivity of test structure 3 with respect to line-to-ground capacitance in the coupled corner building block Figure S 21 and S 11 sensitivity of test structure 3 with respect to shunt capacitance in the coupled corner building block Figure S 21 and S 11 sensitivity of test structure 3 with respect to line-to-line mutual inductance in the coupled corner building block Figure S 21 and S 11 sensitivity of test structure 3 with respect to line inductance in the coupled corner building block Figure S 21 and S 11 sensitivity of test structure 3 with respect to line resistance in the coupled corner building block Figure Building blocks, equivalent circuits, and parameters for spiral inductor modeling Figure S-parameter measured and modeled results for test structure Figure S-parameter measured and modeled results for test structure Figure S-parameter measured and modeled results for test structure Figure turn spiral inductor predictively modeled xx

21 Figure Z-parameter circuit configurations for inductor analysis (top) MDS configuration (bottom) circuit predictive model configuration Figure Measured and predicted results for Z11(dB) of four turn spiral inductor. 138 Figure Measured and predicted results for Z11(phase) of four turn spiral inductor Figure LC resonant tank circuit Figure Actual (MDS) and predicted LC circuit output voltage magnitude Figure Actual (MDS) and predicted LC circuit output voltage phase Figure LC circuit with 2 4-turn inductors in parallel Figure Actual (MDS) and predicted LC circuit output voltage magnitude Figure Actual (MDS) and predicted LC circuit output voltage phase Figure Solenoid inductor geometry Figure Gridded plate capacitor geometry Figure Solenoid inductor building blocks Figure Gridded plate capacitor building block Figure Test structures for solenoid inductor modeling Figure Additional test structure for gridded plate capacitor modeling Figure Physical layout of LTCC coupon Figure Photograph of top side of fabricated LTCC coupon xxi

22 Figure Photograph of bottom side of LTCC coupon with last embedded layer partially visible Figure Photograph of cross section of metal line in a LTCC structure along the line length (photograph courtesy of National Semiconductor Corp.) Figure Photograph of cross section of metal line across line width (short) (photograph courtesy of National Semiconductor Corp.) Figure Photograph of cross section of 2 via stack (photograph courtesy of National Semiconductor Corp.) Figure S 11 and S 21 sensitivity responses of test structure 1 with respect to capacitance to ground in the interconnect line building block Figure S 11 and S 21 sensitivity responses of test structure 1 with respect to line inductance in the interconnect line building block Figure S 11 and S 21 sensitivity responses of test structure 1 with respect to capacitance-to-ground in the probe pad building block Figure S 11 and S 21 sensitivity responses of test structure 1 with respect to line inductance in the probe pad building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to capacitance-to-ground of the top conductor in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line inductance of the top conductor in the inductor coil building block xxii

23 Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line resistance of the top conductor in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line conductance of the top conductor in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line-toground capacitance of the bottom conductor in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line inductance of the bottom conductor in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line resistance of the bottom conductor in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line conductance to ground of the bottom conductor in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to via capacitance in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to via inductance in the inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 3 with respect to coupling capacitance in the interacting inductor coil building block xxiii

24 Figure S 11 and S 21 sensitivity responses of test structure 3 with respect to line-toline mutual inductance in the interacting inductor coil building block Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to capacitance-to-ground of the top plate in the gridded capacitor building block Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to capacitance-to-ground of the bottom plate in the gridded capacitor building block Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to mutual capacitance between the plates in the gridded capacitor building block Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to mutual inductance between the plates in the gridded capacitor building block Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to line inductance for both plates in the gridded capacitor building block Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to line resistance for both plates in the gridded capacitor building block Figure Z-parameter MDS circuit configuration for inductor and capacitor analysis Figure Building blocks, equivalent circuits and parameter values for solenoid inductor and gridded plate capacitor modeling xxiv

25 Figure Measured vs. modeled results for test structure 1. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response Figure Measured vs. modeled results for test structure 2. (a) Z 11 magnitude response. (b) Z 11 phase response Figure Measured vs. modeled results for test structure 3. (a) Z 11 magnitude response. (b) Z 11 phase response Figure Measured vs. modeled results for test structure 4. (a) Z 11 magnitude response. (b) Z 11 phase response Figure Fabricated solenoid inductors Figure Measured and predicted results for Z 11 (db) for 4-coil, 6 turn per coil inductor Figure Measured and predicted results for Z 11 (phase) for 4-coil, 6 turn per coil inductor Figure Measured and predicted results for Z 11 (db) for 4-coil, 8 turn per coil inductor Figure Measured and predicted results for Z 11 (phase) for 4-coil, 8 turn per coil inductor Figure Large gridded plate capacitor used to test capacitor building block model validity Figure Measured and predicted results for Z 11 (db) for large capacitor xxv

26 Figure Measured and predicted results for Z 11 (phase) for large capacitor Figure A.1-1 Circuit for impedance parameter sensitivity analysis Figure A.1-2. Z 11 and Z 21 real and imaginary components for RLC circuit Figure A.1-3. Z 11 sensitivity with respect to C and L for RLC circuit, real and imaginary parts Figure A.1-4. Z 11 sensitivity with respect to R and R2 for RLC circuit, real and imaginary parts Figure A.1-5. Z 21 sensitivity with respect to C and L for RLC circuit, real and imaginary parts Figure A.1-6. Z 21 sensitivity with respect to R and R2 for RLC circuit, real and imaginary parts Figure B.1-1. Possible corner building block and usage in two structures Figure B.2-1. Representative impedance grid. Each box represents and impedance Figure B.2-2. Definition of S-shaped region on impedance grid Figure B.2-3. Impedance and corresponding entries in MNA matrix Figure B.2-4. Mapping operation between computed voltage vector and 2D voltage matrix for actual geometrical structure being analyzed Figure B.2-5. MNA matrix sparsity pattern for serpentine resistor analysis xxvi

27 Figure B.2-6 Contour and indexed image plots of current distribution for two different geometry bends Figure B.3-1. Indexed current intensity plot of gridded structure Figure B.3-2. Current gradient magnitude contour plot Figure B.3-3. Contour plots of X and Y directed current gradients showing current crowding effects Figure B.3-4. Current profile plot through axis A-A Figure B.3-5. Current profile plot through axis B-B Figure B.3-6. Current profile plot through axis C-C xxvii

28 SUMMARY A novel procedure is presented for accurate, high frequency electrical behavior predictive modeling of passive devices with interactions. The developed method is based upon defining structural building blocks and equivalent circuits, associating design rules with them, and characterizing them through the use of test structures. The test structures are designed such that they are comprised only of sensitive combinations of defined building blocks, and they are measured over a wide band of frequencies using network analysis techniques. Building block equivalent circuit models are derived from the measured test structure data by nonlinear optimization methods. The method has been experimentally verified for all different classes of passive devices, including resistors, capacitors, and inductors, in both planar and 3-dimensional configurations. The method has also been verified on circuits using these components, with good results obtained in both cases. xxviii

29 CHAPTER I INTRODUCTION Advances in technology are making possible systems that are faster and more powerful than ever before. Research and development in academia and industry are constantly finding new ways to improve system performance. Most of the advances have been in the area of integrated circuit (IC) technology and fabrication. While on-chip frequencies are already at the 500 MHz level in commercial products, such as in the Alpha microprocessor developed at Digital Equipment Corporation, communication with off-chip devices such as DRAM still occur at a much reduced rate. In fact, frequencies at the board level at even the MHz range are difficult to obtain cheaply, mainly due to the parasitic effects of simple interconnect lines on the printed circuit board. While most systems do include a number of integrated circuits, they usually also include a large number of passive devices. In general, the majority of passive devices that are required are kept off chip and outside the package, in order to reduce costs and to reserve area for active structures. In some cases, however, such as in analog and RF chips, vital passive devices may be integrated on chip. This generally is required when accurate passives are required, or when high speed signals must be propagated through these structures, as would be the case for resistors in a resistor utilizing digital to analog converter, or for capacitors and inductors in a high-q cutoff filter or oscillator. 1

30 Increasing on-chip transistor count is allowing more functionality to be integrated on to a single integrated circuit. This has led to combining functions of several separate chips into one IC, thereby eliminating the need for other ICs altogether. This integration has lead to considerable reductions in overall board space requirements, with overall active component counts dropping by significant percentages. Passive component board area has actually increased as a percentage of overall board space in recent times, and is now becoming a limiting factor for further reductions in board size. Reducing printed circuit board area would result in much smaller, lighter, and more reliable systems which could potentially impact every component using electronic circuits. The advantages of miniaturization have driven the development of new technologies to remove passives from on top of the printed circuit board, and instead to embed them within a substrate or a package. Processes such as thick and thin film processing have allowed for the deposition of materials at mil and micron level linewidths and spacings within multichip modules, and techniques such as low temperature cofired ceramic (LTCC) processing allow for thick film printing and stacking of passive devices in a multilayer (well over 30 layers are possible), low-cost substrate. LTCC fabrication techniques show tremendous promise for integration of a large number of passive components into a multilayer ceramic substrate, with the possibility of combining it along with an integrated circuit within a standard IC size package. Passive devices manufactured in these technologies take on certain representative shapes. Resistors, for example, are usually designed in straight lines or in a serpentine 2

31 fashion, while capacitors are usually designed with interdigitated fingers in the planar form, and as a parallel plate device in 3 dimensions. Inductors too have basically two shapes, one is planar spiral structure, while a 3 dimensional implementation involves generating a solenoid with two different layers of metal and many deep vias. In order to utilize any new technology efficiently for design work, good behavior predictions of the various components involved is very important. In integrated circuit design work, for example, good models for transistors are crucial to help obtain fabricated circuits that match designed specifications. In this area itself, transistor models are in continuous development, and based on technology enhancements, have evolved from SPICE level I, II, and III, to the current BSIM family of models. In the same manner, accurate, frequency dependent, wide band models of passive components are very important for successful high speed circuit design. Most practical passive devices have complex geometries, nonuniform current flow, and correspondingly complex field patterns. All passive components suffer from parasitic effects which can affect the electrical behavior of the device at different frequencies. In addition, for small planar and 3 dimensional structures, the structures can become electrically long above some frequency, and start exhibiting transmission line behavior. Coupling effects within the structure itself can also affect performance, and this kind of behavior can easily manifest itself in passive components where many long lines run adjacent to each other, as is the case in serpentine resistors. All of these phenomena, coupled with non-ideal processing effects, make predictive modeling of such structures very difficult. 3

32 1.1. Thesis Organization In this dissertation, a novel method of modeling of passive structures will presented, with several case studies examined in detail. The first part of this thesis is dedicated to the development and procedures of the method, while the second section shows the application of the method to the predictive modeling of the three main classes of passive devices, namely the resistor, capacitor, and inductor. Procedures and results are shown initially for planar devices. Modeling of fully 3-dimensional devices with interactions is also examined, and good results are shown for devices fabricated in a state-of-the-art multilayer low temperature cofired ceramic substrate process. A brief chapter-by-chapter outline of the thesis is given below. Chapter 2 discusses the background and origin of the problem, and presents some of the major work already performed in this area. As will be seen, most of the work originates from the microwave engineering arena, where planar passive structures have been used for a considerable length of time and at high frequencies for microwave/rf applications. Chapter 3 presents a detailed description of the passive predictive modeling methodology developed under this research program. Chapter 4 shows the application of the method to the modeling of planar serpentine resistor structures. The results are compared against measurements, and are verified up to 5-10 GHz frequency range. Chapter 5 also shows application of the method, in this case to interdigital capacitors, and combined capacitor resistor circuits. Again, results are verified against measurements. Chapter 6 shows application of the method to the modeling of planar spiral inductors. 4

33 Results are obtained and verified against simulations obtained from a Method of Moments simulator. Chapter 7 presents the application of the method to full 3 dimensional structures manufactured in a thick film low temperature cofired ceramic process. The structures modeled include gridded plate capacitors and solenoid inductors in both series and parallel configurations with interactions. The results obtained are compared against actual measurements with good agreement up to the first resonance. Chapter 8 draws conclusions regarding this work and provides recommendations for further research. Several appendices are also included which document some detailed circuit sensitivity analysis; the development of a current visualization tool; optimization procedures; and the various circuit models and measured data of passive device test and benchmark structures studied under this research work. 5

34 CHAPTER II BACKGROUND 2.1. Introduction As presented in Chapter 1, accurate modeling of integrated passive components is becoming very important for the successful design and fabrication of compact, high performance systems that utilize such devices. Highly miniaturized passive components have been used extensively in the microwave/rf community and have been fabricated on GaAs, and high speed silicon substrates for use in microwave circuits. Clearly, at microwave frequencies, good frequency dependent models of passive components must be obtained for successful design. As a result of this requirement, much of the work in the area of passive component modeling originates from the microwave engineering community. Modeling of miniature passive components usually falls into three categories; analytical equation based models; measurement based models, and numerical full wave electromagnetic models. There has also been some interesting work published using neural networks for the modeling of passive devices. In this chapter, an overview of the various methods will be presented; details can be found in the various references. 6

35 2.2. Analytical Models In this section passive component equation models that are based on fundamental principles are discussed. There are very few entirely analytical models that do not require any kind of special numerical computation, such as numerical integration, except for very simple structures. Most of the methods do require some form of numerical analysis, but do not require gridding, and solving large matrix equations, as is the case for the direct full wave methods. Many analytical expressions have also been derived from simulation and curve fitting, and not directly from first principles. It is neither practical nor useful to present all analytical formulas and methods for modeling of passive components, but some representative results are discussed. Expressions for electrically small straight line, circular, and rectangular inductors can be found in [1]. Completely analytical results (without any numerical techniques involved) are given for the inductance of a straight line, taking into account metal thickness, and also attempts to take into account high frequency skin effect losses. Analytical equations are also provided for the single loop, circular and rectangular inductors, but all of these require numerical methods involving numerical integration and the use of elliptical integrals. A generalization of the method described in [1] for the modeling of multilayer spiral inductors is given in [2]. Models for circular spiral inductors are also presented in [3], which is based on some early work on exact evaluation of inductance of circular line segments. This paper also presents an overview of the various methods for inductor 7

36 modeling that had been attempted earlier, and the reader is referred to its list of references for further information. Another paper based on early work [4] is presented in [5], in which the author presents some modifications to a very early empirically derived formula for square spiral inductor modeling, with good results. Capacitor models have been shown in various papers. Parallel plate capacitor models are usually modeled using microstrip coupled lines and conformal mapping theory [1]. Interdigital capacitors have been modeled within a microwave CAD package using built in models for coupled microstrips, T-junctions, etc. [1] These models themselves are based upon curve fit or table lookup models derived from full wave simulations or measurements of the various pieces [6]. Multilayer interdigital capacitors have also been modeled analytically using complex conformal mapping techniques [7]. In general, there appears to be a myriad of different analytical models available for the modeling of passive devices. They clearly fall into two classes; derived from first principles and derived from curve fitting from simulation or measurement. It is interesting to note that resistive effects are either not modeled at all, or are simply included in the form of a series resistance term, since many microstrip models assume very low loss conductors. This is also probably a major factor contributing to the fact that very little work can be found on modeling of serpentine resistors, except by use of full wave methods. 8

37 2.3. Measurement Based Models In many cases, models of passive components are only developed after they have been fabricated and measured. This technique has many advantages, since it can be applied to any arbitrary structure, and takes into account processing effects such as nonuniform dielectric thicknesses, which would be very difficult to achieve with any other method. For high frequency applications, network analysis or time domain reflectometry (TDR) measurements are taken to characterize the device under measurement. In network analysis, a scattering parameter response over a wide band of frequencies is obtained, while for TDR a time domain voltage profile is obtained, with peaks and valleys representing capacitive or inductive discontinuities within the structure. Frequency domain S-parameter measurements allow device models to be constructed in several ways. One way is to simply use the S-parameters as a black box model of the device, and use that for design applications. Some simulators allow the use of S-parameter datasets as models (such as Hewlett-Packard MDS), but this is still not widely supported. The other approach is to fit the measured S-parameter data to a circuit model using optimization. Simple circuit representations of the various passive components can be found in [6], and these are often used in the literature. Examples of using S-parameter measurements to model passive structure are given in [8], [9] and [10]. In time domain reflectometry, a very short duration pulse is injected into the structure under test, and an effective reflected impulse response is obtained. The response usually contains peaks, valleys, oscillations, and relaxations, and these phenomena can be 9

38 related to inductive, capacitive, resistive or some combination discontinuities. The position of the discontinuity within the structure can also be estimated, since an earlier one will manifest itself earlier on the TDR output. Based upon the actual time scale, the relative position of the discontinuity can be determined, since the velocity of propagation is known (or can be easily found). An overview of time domain reflectometry can be found in [11]. Examples of where TDR has been used in passive component modeling can be found in [12] and [13] Numerical Full-Wave Methods Numerical electromagnetic full-wave simulation methods are undoubtedly the most flexible and general of all the modeling methods. These methods essentially apply Maxwell s equations to an arbitrary geometry structure and compute electric and magnetic field patterns. The methods generally require segmenting the structure under analysis into many small pieces, and solving equations on each piece in order to obtain the response of the whole structure. Simulation time is directly related to the number of grid cells and frequency points, and as a result, simulation times can become very long for complex structures. Problems are especially difficult when there are many discontinuities in a structure, such as a gridded plate, since many grid cells have to be created to model complex behavior at the corners and edges of the discontinuities. There are several different numerical methods that have been used for full wave analysis of structures. These methods include the finite and boundary element methods, 10

39 the finite-difference time domain method, the method of moments, the transmission line matrix method, the 3-D spectral domain analysis [14], and the mixed potential integral equation method [15]. Some good general overview papers describing the most popular methods are [16], [17], [18] and [19]. One of the more popular methods of simulation is the dyadic Green s function based method of moments algorithm (MoM), since it eliminates one degree of freedom by assuming infinitely thin conductors, but still allows for multilayer (conductors on different layers) simulations. This falls into the class of 2 ½-dimensional methods, however, simulations with this method can take many hours also, but are radically faster, although more inaccurate than full 3-D methods. There are many articles in the literature showing the use of this method for modeling of passive structures. Some representative ones are [20], [21], [22] and [23]. Another method that has become very popular for passive device modeling is the finite difference time domain (FDTD) method [24]. Unlike the method of moments, this is a full 3-D method, and does take into account conductor heights. Much work can be found where the FDTD method has been applied to the modeling of spiral inductors with air bridges [25], [26], and [27]. Additionally interdigital capacitors have also been modeled using the method [28]. The method has also been used to model an entire library of components, including discontinuities in [29] and [30]. For the modeling of full 3-D devices, such as those that can be manufactured in a multilayer low temperature cofired ceramic (LTCC) process, the finite element method seems to be the simulation method of choice [31] [32]. 11

40 In addition to the standard methods of modeling, a new neural network based approach has been presented [33]. This method is based upon training a neural network on the S-parameters of various devices, with the network inputs being design parameters such as widths and lengths. The method has shown very good results for an inductor modeling application Discussion All of the above methods have advantages and disadvantages. The analytical methods can be very useful if good results can be obtained for a particular process. Derivations of expressions from measured or simulated structures can be a time consuming and difficult process, and for general structure design many degrees of freedom will be required. For example, for spiral inductor modeling, the designer will at least need to vary the number of turns in an inductor and also the horizontal and vertical dimensions, yielding 3 degrees of freedom. Additionally, in order to model parasitics, even more variables are introduced, and this will tend to complicate the generation of analytical models further. However, if development time is acceptable, and expressions can be developed, then accurate analytical models are very useful and extremely fast. Models developed from measurements are very accurate, since they account for processing effects such as inhomogeneous dielectrics, uneven conductors, and similar effects which are very difficult to model with any other method. The main problem associated with this method is lack of flexibility. The generated models only apply to the 12

41 devices actual fabricated, with no accurate method of scaling to model other structures. The method can be used to model a large library of components, and a designer must choose components from that library alone to obtain accurate models. If the designer requires a component that does not exist in the library, it must first be fabricated and then modeled. In general, developing a comprehensive library of modeled components could be difficult and time consuming. Full wave analysis is a very useful method for investigating the electrical behavior of an arbitrary structure. The analysis is usually quite accurate if enough time is spent to input the substrate and structure geometries accurately. However, due to the meshing nature of these methods, the more complex the input system, the greater the number of mesh points, and the longer the simulation time. Even for relatively simple structures, such as planar resistors and interdigital capacitors, simulation times can run into hours for accurate high frequency simulations using a method of moments approach. Finite element simulations usually take much longer since an entire 3-dimensional volume must be meshed and solved. The use of these tools for component design is probably not very practical (although it has been attempted [34]), since design by nature is an iterative process, and each iteration could take many hours or even days of simulation time on modern workstations. 13

42 2.6. Summary In this chapter, an overview of the various methods of passive component design has been presented and classified. A brief discussion has also been presented, treating some of the more important issues regarding each type of method. In the next chapter a novel test structure and building block based modeling methodology that has been developed under this research program will be presented. In the chapters following that, the method will be demonstrated and verified on various types of passive structures, including resistors, capacitors, inductors, and full 3-D structures manufactured in a LTCC process. 14

43 CHAPTER III PASSIVE DEVICE MODELING METHODOLOGY 3.1. Introduction This chapter describes in detail the development of a new high speed, high frequency modeling methodology for passive devices with interactions [35], [36], and [37]. The method produces circuit models of structures which are constructed from equivalent circuits of building blocks. The building block equivalent circuits are derived from test structures and measurements, and thus automatically take into account effects of processing fluctuations and nonideal material properties. The generated circuit models simulate in a standard circuit solver and occur very quickly, usually on the order of minutes or seconds, thus providing a major speedup over methods that do not utilize lumped elements. The method is applicable to both electrically long and short structures, and is independent of technology or the process in which the structures are fabricated. The building block paradigm of this method as well as the production of circuit models that simulate very quickly make this method very well suited for circuit design applications. 15

44 Accuracy of the modeling method is solely dependent upon the accuracy of the modeled building blocks. Extremely accurate models that are valid up to very high frequencies can be obtained if long interaction distances and retardation effects are taken into account. The method is also flexible enough that circuit models do not have to be used for the building blocks. If necessary, multiport parameter black box representations can be used, although many circuit simulators do not accept direct multiport parameters as input. The fundamental idea behind the modeling procedure is that most designed passive structures are comprised of several key geometrical building blocks, that is, they can be constructed from several building block cells representing individual parts of the structure. These building blocks can de defined in a number of ways, but careful selection can result in relatively few building blocks being needed. If accurate models for each of the building blocks along with interaction information can be obtained, then any arbitrary structure comprised of those building blocks can be modeled accurately using the individual block models. Building block models are extracted by the use of test structures. Test structures comprising a complete set of the identified building blocks are designed and manufactured in the process of interest, and two port frequency measurements are performed on them by use of a network analyzer. In general, any test structure will be comprised of several different building blocks. Using the measured data, optimization and extraction routines are performed in order to extract passive RLC models for each of the embedded building blocks. These building blocks and their associated models can be 16

45 used to predict the behavior of other arbitrary geometry structures made in the same process as the test structures, if they are comprised of the modeled building blocks in a specified and correct manner. The method generates equivalent circuits of the devices, and the predictions are obtained simply through circuit simulation utilizing standard SPICE-like software Design and Modeling Flowchart The entire developed modeling methodology can be concisely described in a flow diagram. The diagram is shown in Figure The details behind the method will be described at length in the remainder of the chapter, but a short description of the complete process will help clarify the process. The first step in the modeling process is to identify what sort of devices are to be modeled in a process, identify building blocks and consequently design rules. Once the building blocks have been defined, the next step is to design and fabricate test structures to characterize them. This is then followed by measurement of the test structures in order to aid building block circuit extraction. The measured data is then used to set up optimizations to extract equivalent circuits of the test structures and building blocks, and is also used to determine initial guesses. Once successful optimizations have been achieved, the building blocks with associated models and design rules are combined in a library. Once a valid library is constructed, a designer can then use it to construct a new passive device. Design rule compliance can be verified through the use of a geometry 17

46 based design rule checker. If the check fails, then the designer can take one of two routes he or she can either redesign the device until it is compliant, or can attempt to generate models for the section that is causing errors by defining new building blocks and test structures and going through the characterization procedure. Once the design passes the design rule checker, then accurate models of the device are output which can then be simulated in a circuit simulator. 18

47 Modeling Identify Building Blocks, Define Geometries Design and Fabricate Test Structures Perform Measurements, Obtain Initial Guess Data Execute Optimizations, Extract Building Block Equivalent Circuits Associate Building Block Equivalent Circuits and Design Rules in Library/Technology File Design Design Passive Device Design Rule Check Fail Pass Accurate Model Figure Design and Modeling Flowchart 19

48 3.3. Building Blocks The general idea behind the proposed modeling methodology is that accurately modeling small pieces of a structure will allow us to model the behavior of a larger structure composed of some combination of those pieces. This idea, but with many very small pieces, is the premise behind the classical, well understood method of finite element analysis (FEA) [38]. In FEA, a large, complex problem is broken down into a huge number of simple subproblems by segmenting the structure of interest into many pieces and applying the relevant boundary conditions or external excitations to the appropriate elements. Every piece, or element, is characterized by a relatively simple functional mapping (basis function) on its boundaries, which is continuous within itself and between adjacent elements. As the element sizes become smaller, the effect of the simple basis function reduces, and hence the results become more accurate. As is to be expected, the gain in accuracy with finite elements comes at a price. For most nontrivial structures, a large number of elements are needed, and for a threedimensional problem, the complexity of the problem increases dramatically. Computer memory requirements can very quickly become enormous, even using some of the most advanced FEA packages commercially available, with computation times leading into many hours, if not days, on some of the fastest workstations available today. In addition to huge computational expense, if the problem size exceeds available physical memory, a very large part of computer time is wasted in simply performing memory management 20

49 tasks, and in many cases, only a small percentage of actual CPU resources is spent on actual solution computation. In the method presented here, there is no need to segment the problem in to a large number of small pieces in order to obtain accurate results. In this method, relatively large pieces compared to finite elements are considered, even for complex current regions such as corners. The reason this is possible is that there is no assumption made about basis functions within the pieces or building blocks, since their individual behavior is derived from measurements of test structures, or if measurements are not available or possible, them from accurate simulations of the test structures utilizing exhaustive FEA, moment methods or similar procedures. Since basis functions are not assumed, the size of the block has no effect on accuracy, and thus it can be chosen to be relatively large. The main goal is to generate a function that represents the behavior of the block, and then utilize that functional description in the analysis of other structures comprised of those blocks in a specified way. The main restriction on the size of the block is our ability to model its behavior well with a relatively simple system. In a strict sense, this is not as much a restriction as it is a preference - generating intricate models to represent complex behavior is acceptable, although it may be difficult. Our objective is to be able to predict the electrical behavior of arbitrary geometry passive devices in a standard circuit simulator. In order to achieve this, each building block is modeled as a SPICE compatible RLC circuit. For relatively simple uncoupled building blocks, such as for modeling a piece of a straight line, simple RLC models based on the partial element equivalent circuit (PEEC) [39], [40] are used for equivalent 21

50 circuits. In the case of blocks where coupling needs to be taken into account, e.g. coupled material squares (corresponding to coupled adjacent lines or interacting material squares), coupled PEEC models are used, connected by coupling capacitances and mutual inductances (Figure 3.3-1). Although circuit models are being used here, this is not a requirement. Any functional description or data table representing each of the building blocks could be used just as well, however, this would require specialized simulators and tools which may not be readily available. The circuit level modeling approach works well in any standard SPICE compatible circuit simulator. 22

51 1 2 Uncoupled Line Bldg. Block 1 CC CC R L L R 2 C Coupled Line Bldg. Block 2 1 CC L M CC R L L R C C M CC R L L R C CC L M 4 3 Figure Uncoupled and coupled PEEC circuits with associated building blocks The PEEC circuit has been shown to be equivalent to Maxwell's Equations for small sections of material of approximately 1/10 wavelength long. The level of coupling also refers to the level of the equivalent circuit, for example, when considering only second level coupling, that is coupling effects from nearest neighbors only, then we have second order equivalent circuits, as shown on the lower part of Figure For higher order coupling effects to be taken into account, higher order building blocks and equivalent circuits are required. For example, to account for coupling from both the nearest and second nearest neighbor, we would need to include an additional PEEC 23

52 circuit and include capacitive couplings between all the center nodes of the circuits, and include mutual inductances between all left and right side inductors respectively. For more complex building blocks, however, equivalent circuits are derived on a per case basis. This would be required, for example, in the case of a building block representing one square of material surrounded on three sides by material, as might be found at the ends of segments in interdigital capacitors. A possible circuit representing this structure is shown in Figure Figure Interdigital capacitor segment end piece and possible second order (nearest neighbor coupling) equivalent circuit Clearly, the circuit model for the capacitor end piece is fairly complex, but even so, certain behavior may not be adequately predicted using such a model. In order to obtain good models of complex geometry building blocks, we may have to resort to S- parameter table models to capture all electrical behavior within them. 24

53 3.4. Build Block Definition In order to effectively use the building block based method, building blocks for the structures of interest must be defined. The first step involved in accomplishing this is a determination of the kinds of geometries that are to be considered for the design and modeling of a particular kind of device. For example, a particular linewidth and spacing for interdigital capacitors should be fixed. The number of variations possible on the physical layout of a particular type of structure are infinite, however, generating building blocks for every conceivable layout is not practical. In order to utilize the proposed modeling methodology efficiently, design rules must be derived to dictate what geometries of structures will be allowable, and once this is determined, building blocks and test structures can be built and characterized. It should be emphasized that even with one linewidth and spacing, a large variety of structures can de designed, since there is no explicit limit on length or number of segments. In order to determine the actual geometries of the building blocks, some form of current analysis should be performed to ensure that building block boundaries are defined along regions of uniform current flow. Although this is not a requirement in the strictest sense (a large number of context sensitive building blocks can be built up, e.g. a corner adjacent to one square, a corner adjacent to another corner, etc.), it helps simplify the modeling procedure if adhered to. In order to do this, a high speed, low frequency, current visualization tool was developed under this research, and details about it are given in Appendix B. 25

54 In general, the modeling procedure essentially leads to generation of design rules in order to achieve good modeling accuracy. This philosophy is actually adapted widely by analog integrated circuit design houses where only certain geometry transistors are allowable due to the existence of good models for them. These geometry based design rules are easily implementable in most commercially available integrated circuit design packages, and thus these programs can be used for designing passive component in compliance with set design rules. These design rules may seem to be very restrictive at first glance, but even a small set actually can allow for a huge variety of different structures to be designed. For example, consider the case where design rules for serpentine resistors are under development (Figure 3.4-1). For a particular thick film process, minimum linewidth and spacing rules dictate that lines must be a minimum of 5 mils wide with interline spacings of 5 mils. If design rules are established which force 5 mil lines and 5 mils spacings for lines in serpentine resistors designed in this process, with only right angle bends allowed at the ends of lines to connect two adjacent lines together, and with a minimum line length of 35 mils, a wide variety of structures can be designed. All serpentine resistors which comply with the design rules can be as long as desired beyond 35 mils in 5 mil increments, and there are no restrictions on the number of segments. This clearly represents a very large set of resistor values that can be designed and modeled accurately. The allowable geometries can easily be increased by defining new building blocks and test structures, and hence the method is highly expandable. 26

55 Coupled Line Building Block U Building Block Uncoupled Line Building Block Figure Serpentine resistors designed from the same set of building blocks 27

56 3.5. Test Structures Once building blocks have been defined, the next step is to characterize and develop models for them. This is achieved through the use of carefully designed test structures. The test structure set is designed such that it is comprised of all the predefined building blocks. The equivalent circuit of the test structure is constructed by combining the equivalent circuits of each of building blocks of which it is comprised. Once designed and fabricated in the process of interest, high frequency measurements of the test structures are taken which are then used to characterize each of the building blocks. An example of a possible test structure set for the modeling of serpentine resistors is shown in Figure Although some standard formulations exist for obtaining high frequency scattering parameter data sets for some building blocks, such as coupled lines, and T- junctions in microstrip configurations, the measurement based method provides some significant advantages. Since measurements of the devices are taken, no assumptions are made regarding material properties, layered dielectrics, or imperfect substrates, since all these effects are taken into account in the measured data. This makes the modeling procedure entirely process independent. It has been experimentally shown to work on highly nonuniform alumina substrates as well as multilayer low temperature cofired ceramic (LTCC) substrates. Additional process related nonlinearities are also taken into account, such as uneven metal deposition or printing, jagged edges, etc. In addition, with very fine lines, metal loss becomes an important factor, and this too can be taken into 28

57 account by the measurement based method. Test structures are also not limited to 2 dimensions. Structures can easily be defined in 3 dimensions to help characterize and predict the behavior of 3D passives; for example, those that are fabricated in LTCC processes. An important feature of the measurement based method is the ability to collect statistical information on the process of interest. This can be accomplished by fabricating test structures repeatedly on different runs of a process, and extracting building block models for them each time. A range of values for each circuit parameter can be constructed which in turn can generate statistical yield information for the designed passive device. This sort of information would be very important in any kind of volume precision application, for example in high-q filter designs. Coupled Square Primitive U-Shaped Bend Primitive Figure Test structures for serpentine resistor modeling 29

58 One important issue that must be addressed when designing the test structures is that all the required building blocks contribute enough to the overall response to be measurable, that is, the structure must be sensitive to all the building blocks. Since the structure responses are frequency dependent, the various blocks and their corresponding circuit models will have circuit components which will yield different sensitivities to the output parameters at different frequency points. The varying sensitivity of the output parameters with respect to frequency of the individual circuit parameters helps us to extract the circuit parameters for the various blocks Test Structure Equivalent Circuit Extraction In this section an overview of the theory behind extracting equivalent circuits and their corresponding parameters from measured data is presented. As was mentioned above, high frequency measurements using network analysis techniques are performed to obtain two port scattering parameters. In the equations and formulae below, impedance parameters are used, mainly because they are easier to derive analytically. There is no difference in the information obtained from impedance or scattering parameters, however, since they are essentially equivalent due to the existence of known transformations which map one to the other [41]. Due to the extremely high degree of nonlinearity of equations for deembedding the circuit parameters, analytical solutions are seldom possible, optimization of model parameters is usually the only recourse available. The objective of this section is to show 30

59 that, with enough frequency points, and sufficient sensitivity, accurate equivalent circuit extraction of individual building blocks from multi building block test possible. Vandermonde analysis is presented to aid in clarifying how the extraction method works. Sensitivity analysis is also discussed as a tool to help determine the "relative uniqueness" of the extracted parameters. Finally, in order to clarify some of the issues, several simple examples are presented in detail. For an arbitrary passive circuit network, we can obtain multiport parameters such as impedance parameters which are essentially quotient polynomial functions in frequency, and which have the form a( V, ω) Zij ( V, ω) = (3-1) b( V, ω) where V is the passive element circuit parameters vector and ω is frequency in radians per second. Expanding the quotient polynomial, we obtain Z ij a( V, ω) ( V, ω) = = b( V, ω) 2 a0 + a1ω + a2ω + L+ akω 2 b + b ω + b ω + L+ b ω n k n (3-2) where a k and b k represent combinations of various circuit parameter values. Equation 3-2 can be represented by a qth order polynomial by performing a moment matching approximation. This yields an expression of the form 2 3 q c c ω + c ω + c ω + L + c q ω Z ( ) (3-3) ij ω 31

60 where the c k terms represent moments of the system. Moment matching techniques are widely used in integrated circuit interconnect analysis for network simplification and timing analysis [42]. Details of the moment matching approximation can be found in the literature [43]. For a physical circuit whose circuit parameters are not known, measurements can be performed to obtain impedance parameters at different frequencies. The various c k are combinations of the various circuit component parameters and are constant over frequency. At frequencies where nonlinear phenomena such as skin effect start to take place, this assumption no longer holds. Equation (3-3) implies that if measurements of the system can be obtained at different and a sufficient number of frequency points, then the various c k can be deembedded. Systems of this type are known as Vandermonde systems. The Vandermonde formulation proceeds with a linear system of the following form, with the right hand sides of the equations being the measured impedance parameter. 1 1 M 1 ω ω ω M 1 n L L O L ω ω ω q 0 q 1 M q q c1 c 2 = M cq Z Z Z ij ij ij ( ω ( ω M ( ω 0 1 q ) ) ) (3-4) which can also be written as T V c = Z (3-5) Where V is the Vandermonde matrix and is nonsingular for distinct ω k. This equation can be solved using well investigated methods that can take into account problems such 32

61 as ill-conditioning that can easily arise in such systems, especially when large frequency values are used. The fact that we can formulate a non-singular system of equations for a linear network, with each equation generated by a different frequency point, leads to the idea that simply by sampling the system over frequency, we can obtain all the information necessary to deembed the various circuit parameters which comprise that system. Once the polynomial coefficients are obtained, we are faced with the challenge of determining the original circuit parameters from them. This problem is very difficult in general, due to the high degree of nonlinearity that is encountered at this point, since the various polynomial coefficients are comprised of products, sums, or some combination of the different circuit parameters. In most cases, due to the nonlinearity present in these problems, the only practical method for extracting circuit component parameter values from measured impedance or scattering parameters is by a process of nonlinear optimization. There are many optimization techniques available, and some of the more popular ones are the Newton-Raphson algorithm, the steepest descent and other gradient methods, fixed-point routines and hybrid methods, which combine several different methods together. The hybrid methods have gained popularity due to their ability to handle a wide variety of problems with better methods of recovering from incorrect search directions, intelligent error based parameter incrementing, etc. The optimization algorithm chosen in our case was Leavenberg-Marquardt due to its ability to choose between the inverse- Hessian and steepest descent methods, which allowed the search algorithm to switch 33

62 depending on whether RMS error at a particular step was relatively large or small [44]. This algorithm is implemented in the Hspice circuit simulator [45], and this tool that has been used extensively for this purpose in this research. The method generally converged in a reasonable amount of time for many different circuit configurations, with good results. Optimization over many frequency points and a wide band is necessary, in order to insure that the output parameters are sensitive to all of the important circuit parameters at some points over the entire frequency range. Sensitivity is very important, since an output parameter which is not sensitive to a particular circuit parameter over a wide frequency band implies that any value (within a reasonable range) of that circuit parameter will not influence the output response, and hence a completely incorrect value can be extracted. It is also possible (and is usually the case), however, that even over the entire frequency range of interest, a particular circuit parameter does not influence the output response, and in this case the lack of sensitivity is probably valid, and is not a result of an incorrect optimization technique. In actual practice, a low sensitivity usually does imply that the parameter does not affect the output responses significantly. Wide band sampling with sufficient frequency resolution is crucial in order to capture all the major reactive effects over a band of interest. In order to deembed a parasitic, it must be observed, and in most instances parasitics are small enough that they only manifest themselves at higher frequencies. A very important factor which must be considered in any optimization is the initial starting vector. This is usually the factor that determines success or failure of a 34

63 particular optimization run. Initial guesses in this case are obtained from measurement as much as possible and then modified based on geometry of building blocks. Additionally, results obtained from a successful optimization of one test structure can be used as initial guesses for unknown building block circuits of another. First pass initial guesses for the building block circuit parameters are determined based on actual measured scattering parameter data. Formulas found in the literature are used for these guesses [46] [47], and have proved to work well in general. The parameter values yielded by these equations represent overall test structure resistance, capacitance and inductance. In order to apportion them correctly to each building block, appropriate scaling factors must be applied, based on the geometry and area or volume used by the blocks. As an example, consider the building block in Figure It is constructed of 24 building blocks of type 1 and 1 block of type 2. The area of block 2 is 8 times that of block 1. If through measurements, it was determined that the entire structure possessed a capacitance C, then on a per unit area basis, each block would be assigned an initial guess capacitance value of C/32. Correctly apportioned, each block of type 1 would have a capacitance of C/32 and block 2 would have a capacitance of C/4. Similar arguments can be applied to resistance and inductance initial guesses also. In reality, due to the nonuniform current flow in block 2, the optimized values of all components will be significantly different, probably less than type 1 blocks on a per unit basis. This is due to the fact that current does not occupy the complete area of the block, and is concentrated on the inner edges, especially in the corners. 35

64 1 2 Figure Test structure for initial guess computation Case Study: RLC Filter Frequency Resolution and Extraction Example As a simple illustration, consider the case of a low pass filter with a voltage gain transfer function given by V ( ω) 1 = + jωrc 2. (3-6) 1 ω LC A plot of the response for the particular values of L=0.1 µh, and C=1 nf with values of R ranging from 0.05 to 1.6 Ω are shown in Figure Referring to the figure, if frequency samples are taken only at low frequencies (up to 10 MHz), then the system will be seen to have a constant gain response, and a incorrect equivalent circuit will be extracted. Frequency samples over the entire band of interest must be taken, and with considerably good resolution in order to extract a valid model. The issue of resolution is also illustrated in Figure 3.6-2, which is an expanded view of the overshoot region of Figure As mentioned, the plot contains 5 curves, each one for a different resistance value. The effect of the different resistance values can only be seen in the overshoot 36

65 region, with different heights corresponding to different values of resistance, and thus to correctly deembed them, sufficient frequency resolution must be obtained in this area log A w, R, L, C i 20. log A w, 2. R, L, C i 20. log A w, 4. R, L, C i 20. log A w, 8. R, L, C i 20. log A w, R, L, C i e+006 w i e+008 Figure Voltage gain of low pass filter log A w, R, L, C i 20. log A w, 2. R, L, C i log A w, 4. R, L, C i 20. log A w, 8. R, L, C i 20. log A w, R, L, C i e+007 w i e+008 Figure Expanded view of overshoot region in gain response of low pass filter 37

66 Several examples of sensitivity analysis for some different circuits are presented. Actual analytical expressions are only shown in very few cases, since the expressions in general become very complex and are difficult to interpret. The output variables of interest are the impedance parameters Z 11 and Z 21, since the circuits are generally symmetric. Scattering parameters are not used since they are more difficult to calculate, however, well known transformations exist between impedance and scattering parameters, and thus they are essentially equivalent Case Study: Partial Element Equivalent Circuit (PEEC) Extraction and Sensitivity Analysis Complete analytical results are shown for the uncoupled PEEC circuit (Figure 3.3-1, top). Although it is unlikely that we will design any test structure solely modeled by only one PEEC circuit, the procedure and results obtained are instructive. Sensitivity analyses of more complex circuits can be carried out by the use of circuit simulators. For the PEEC circuit, the impedance parameters are given by Z R + jωl 1 ( ω ) = + (3-7) 1+ jωrcs ω LCS jωc 11 2 Z 21 ( ω) 1 = (3-8) jωc Taking derivatives of the impedance parameters with respect to the individual parameters, and normalizing to remove the effects of scaling, result in the following expressions for Z 11 38

67 Z11 1 jωcs( R + jωl) R = 2 2 R 1 + jωrcs ω LCS 1+ jωrcs ω LCS Z ( ω) 11 Z L 11 2 jω jω CS( R + jωl) L = jωrcs ω LCS 1+ jωrcs ω LCS Z ( ω) Z11 1 C = 2 C jωc Z ( ω) (3-9(a-d)) Z11 CS 2 R jωl jωr ω L CS = ( + )( ) 2 2 ( 1+ jωrcs ω LCS) Z 11 ( ω) and for Z 21, we obtain Z21 1 C = 2 = 1 C jωc Z ( ω) Z R 21 Z Z = = = 0. L CS (3-10(a,b)) The sensitivity results for Z 11 are plotted on Figure for a circuit with circuit parameter values given by R=1 Ω, L = 1 nh, C=0.5 pf, and CS = 50 ff. As can clearly be seen on the plot, the various circuit parameters affect the output response to a different degree over a wide frequency range. Clearly, the parameters which affect the response most significantly are L and C, the series inductance and capacitance to ground, followed by shunt capacitance CS, and lastly by series resistance R. It is important to note that the series resistance does not have a sensitivity of 0, as might be expected at high frequencies, rather it has a peak of approximately 0.35 at the resonance frequency of 7.1GHz. Z 21 in this case has a constant normalized sensitivity value of -1, indicating that at all frequencies, Z 21 is influenced equally by the one parameter that it consists of; capacitance to ground. 39

68 30 DL w, R, L, C, CS i DC w, R, L, C, CS i DCS w, R, L, C, CS i DR w, R, L, C, CS i f i Figure Sensitivity plot of Z 11 for PEEC circuit The fact that all the circuit parameters in this case yield good sensitivities implies that the test structure is well designed, and the contribution of the building block can be deembedded. Of course, this was a foregone conclusion for this example, since only one building block was used Case Study: 4 Segment RLC Circuit Extraction and Sensitivity Analysis A second, more detailed example is also now described, showing the sensitivities of impedance parameters to two different resistance values in the circuit shown in Figure Due to the complexity of this problem, only partial results are shown here, a full analysis can be found in Appendix A. The circuit is a four segment RLC ladder network, with the resistance value in the last segment being a different value with respect to the rest of the circuit. Analytical results are shown in the appendix for the impedance 40

69 parameters Z 11 and Z 21 with their normalized sensitivities with respect to R and R2 as shown in the circuit. As will become evident from the analysis details, it is usually not practical to compute the parameters manually, due to the huge complexity of the problem, even for a very simple circuit such as this. + R L R L R L R2 L + V 1 - I1 C C C C I2 V 2 - Figure Circuit for impedance parameter sensitivity analysis. Impedance parameters are defined by the following relationship V1 Z V = 2 Z Z Z I1 I. (3-11) 2 In order to extract Z 11 and Z 21, we can simply open circuit I 2 and calculate the impedance parameter responses as Z 11 V1 = and Z I 1 21 V2 = (3-12) I 1 with V 2 being the voltage across the capacitor in the last segment of the circuit. Node equations can be written, and the voltages at all the nodes computed. Using this approach, we obtain the expressions for the impedance parameters. With the aid of symbolic computation tools, we obtain analytical results, the details of which can be found in the 41

70 appendix. Briefly, we obtain complex quotient polynomial expressions for both impedance parameters of the form 8 0 Θ( ω ) Z 11 = and Z 7 21 = Θ ( ω ) 7 Θ( ω ) Θ( ω ). (3-13) Normalized sensitivities of each of the impedance parameters with respect to the circuit resistances are computed with the first finite difference approximation, which is actually a procedure which is very well suited for use within circuit simulators to compute small signal sensitivities. Most commercial simulators do not have the capability of calculating AC sensitivity, but do have the ability of computing a response several times after altering a particular parameter. The classical definition for normalized sensitivity for a function F to a parameter h is given by S F h = F h h F. (3-14) Using the first finite difference to approximate the first order derivative of F, we obtain the finite difference form of the expression: S F h = F( V, h + h) F( V, h) h h F( V, h), h small (3-15) where V represents the vector of unchanging variables of F, h is the parameter in consideration, and h is the increment in h. h must be kept small with respect to h in order for this expression to be accurate. This expression can also be written as 42

71 S F h = F( V, h( 1 + X )) F( V, h), XF( V, h) X small, (3-16) which is somewhat easier to compute. Using these definitions, the sensitivities of the impedance parameters Z 11 and Z 21 with respect to both resistances R and R2 were calculated. The values for the various circuit elements used were R=0.2 Ω, R2=0.1 Ω, L=0.1 µh, and C=1 nf. The plots for both sensitivities are shown in Figure and Figure The traces labeled DR represent normalized sensitivity with respect to R, and correspondingly, the traces label DR2 represent sensitivity with respect to R2. There are several important issues which surface in these results. One of the most striking factors is that Z 11 is far more sensitive to changes in resistance values than Z 21. This is evidenced by the vertical scale on the plots, where Z 11 reaches a maximum of almost 1, whereas Z 21 does not even reach Additionally, even though the value of R2 is quite small, Z 11 is fairly sensitive to it at about 150 MHz, with a value of approximately By contrast, Z 21 is almost entirely insensitive to R2, with values staying below These results imply that if one is trying to deembed resistance values for a network from measured two-port parameters, including Z 11 in the optimizations is necessary, especially if resistance values are low. A very important factor which has become evident from this example is that the two separate impedance parameters yield completely different information about the network. By using both of them, we are utilizing 2 sets of completely different underlying 43

72 equations, and this can help considerably in the optimization and parameter deembedding process DR w, R, L, C, R2 i DR2 w, R, L, C, R2 i e+007 w i e+008 Figure Sensitivity analysis of Z 11 for circuit of Figure e DR w, R, L, C, R2 i DR2 w, R, L, C, R2 i e+007 w i e+008 Figure Sensitivity analysis of Z 21 for circuit of Figure

73 3.7. Library Based Implementation Once equivalent circuits for the building blocks have been successfully extracted, they can be inserted into a design library. The components in the library will have associated with them the geometries of the various building blocks along with input/output port connectivity information, the developed circuit models, and applicable design rules. In modern day electrical engineering CAD systems, highly flexible rules can be defined for design rule checking purposes for physical circuit design. This kind of tool can be used for this work to check for design rule compliance of designed structures, that is, to make sure that the constructed designs are constructed only from the modeled building blocks. Once a useful library has been developed, it can be used for new component design purposes. A designer can then consult the library to create a new structure, and once complete, run it through the design rule checker to ensure compliance. If the structure is not design rule compliant, the offending portions will be highlighted. The designer can then either modify his or her design to make it compliant, or if preferred, can define the error producing structure as a building block and go through the modeling procedure to characterize it. Once the design passes design rule checks, accurate models can be obtained which can then be simulated in a SPICE compatible circuit simulator to obtain predictions of behavior. 45

74 3.8. Summary In this chapter, a detailed description of the modeling methodology was presented. The concept of building blocks was discussed, and a test structure and measurement based characterization procedure was described. Circuit extraction and nonlinear optimization were discussed at length, along with several examples to illustrate some important issues. A method of implementation of the entire procedure within existing EDA frameworks was also presented. In the following chapters, the discussed modeling method will be applied to the predictive modeling of serpentine resistors, interdigital capacitors and spiral inductors. Additionally, the method will also be applied to some fully 3-dimensional passive structures manufactured in a multilayer low temperature cofired ceramic process. 46

75 CHAPTER IV MODELING OF RESISTORS 4.1. Introduction Resistors are an important component in many electrical systems. They are used in many areas, including circuit termination, filtering, voltage scaling, and in active circuits such as digital/analog converters and operational amplifiers just to name a few. Clearly, in applications where resistors play in integral role in circuit performance, their behavior must be accurately modeled and taken into consideration at design time. For relatively low frequency systems, resistors can be approximated as ideal components, with low error. However, for higher frequencies, even for those available in current CMOS technology, this assumption is no longer valid. The parasitic effects of resistors must be taken into account in order to obtain accurate models at these frequencies. An example of a high frequency passive system which uses resistors is a filter designed to meet the Digital Enhanced Cordless Telecommunications (DECT) standard up to 5.7 GHz. Clearly, in order to design a passive filter up to such a high frequency, the behavior of the passive components which comprise the filter must be accurately modeled up to that frequency. For these structures, coupling and parasitics must be taken 47

76 into account to model non-ideal behavior; for example, at some frequency, and depending upon their geometry, resistors become capacitive and then start to resonate, at which point they become essentially useless as resistors. Additionally, high frequency spectral content within signals can cause glitches and signal integrity problems due to reflections, and these phenomena must also be modeled. Accurately predicting these failure modes is very important to ensure that designs operate as expected at higher frequencies. Accurate modeling of resistors using non-lumped element methods, as discussed earlier, can be difficult and time consuming. In this chapter, the high frequency modeling of serpentine resistors using the methodology presented in this thesis is described [48]. As will be shown, accurate predictive modeling results of a 9 segment serpentine resistor have been obtained and verified experimentally up to 5-10 GHz frequency range. Additionally, the generated circuit model has been used in several circuit configurations, with good results. The circuits themselves have not been verified experimentally, but accurate predictions of the fabricated circuit have been obtained using the measured parameters as a model for the multisegment serpentine resistor in a microwave circuit simulator; Hewlett Packard Microwave Design System (MDS). The results obtained by using the complete circuit model of the resistor in the various circuit configurations, and simulated with a standard circuit simulator are compared against results obtained from MDS. It will be shown that in general, the described method produces results that agree well with MDS predictions, up to GHz in various circuit configurations. 48

77 4.2. Modeling Procedure The procedure for modeling the resistors proceeded in the method described in Chapter 3. A brief description of the various steps involved is now presented. 1. The first step involved a determination of what geometry structures were to be considered and allowed in order to set up a practical set of building blocks and test structures to be measured and characterized. 2. This step required entering the geometry of a target structure into custom current flow visualization software (Appendix B) in order to determine the nature of low frequency current distribution through the device. Since the current visualization software could not model coupling behavior, the generated current distribution plots were only approximate for high frequency behavior, but were useful for helping determine building block geometries. Building blocks were to be cut along cross sections of uniform current distribution only. 3. Once the various building blocks had been determined, the next step was to design test structures the help model the various building blocks accurately. Additionally, a sensitivity analysis needed to be performed on the test structure equivalent circuits to ensure that the various parameters could be accurately deembedded. 4. At this point, test structures are fabricated and tested. High frequency network analysis and DC resistance measurements are taken. 49

78 5. Test data is used to form optimization input files for the test structures. Initial guesses are made based on the measured results for each structure. Once optimization for one structure is complete, the results are used for the remaining optimizations. 6. Circuit models of the building blocks are obtained Detailed Resistor Modeling Procedure The first step involved in the resistor modeling procedure was a determination of what types of resistor geometries were to be modeled. Since the theoretical number of possible layouts for a resistor (or any passive structure) is infinite, a restricted set had to be defined in order to determine a sufficiently small set of primitive blocks that would require characterization. Although at first glance, this type of restriction would seem harsh, it is not impractical. Looking at most designs with integrated passive components, most resistors are laid out in one of two ways; straight lines or serpentine structures, with the former the layout of choice for high frequency applications. In this case, attention was focused on the serpentine case for several reasons. First, serpentine resistors are more efficient in substrate area when compared to straight lines for the same resistance value, and if modeled correctly and efficiently, may have larger application in the high frequency arena. Secondly, the serpentine structure also presents a more difficult modeling problem due to higher levels of parasitics, such as coupling effects between the 50

79 segments of the structure, which could considerably affect the overall system response [49]. Resistor modeling with equal linewidths and spacing were considered. In the case presented here, 25 µm linewidth and spacing resistors were modeled. The serpentine geometry dictated that there were three main fundamental building blocks that required characterization: a square building block with connections on opposite sides, a U-shaped section connecting two parallel segments of the resistor together, and a coupled block segment to characterize line to line coupling behavior on a per square basis. Due to the fact that testing of these structures was required, one more building block was added - the probe pad. The actual sizes of these building blocks could only be determined through the use of the current flow visualization tool. Coupling was only considered with respect to nearest neighbors, but higher order coupling could be taken into account, however, this would require more complex test structures (but possibly not more in number) and a more complex extraction procedure. For the 5-10 GHz range, the higher order coupling would not result in an appreciable increase in modeling accuracy for these structures. The current visualization software was used to predict current flow through a representative serpentine resistor. Plots of current distribution and an enlarged view of the U shaped corner are shown in Figure and Figure and a contour plot showing the current crowding effect, is shown in Figure Referring to the diagrams, the cutoff points for each of the primitives were at the areas where the current contours stopped changing rapidly, thus indicating constant current flow between the boundaries of the building blocks. Using this approach, the pad primitive was taken to be the large 51

80 pad square plus one adjacent line square. The material square and coupled material square were taken as one unit of material square each, and the U shaped primitive was represented by 3 squares on each of the horizontal and vertical axes of the U. Figure Current distribution plot of serpentine resistor structure. 52

81 Figure Enlarged view of U shaped section of serpentine resistor. Figure Current contour plot showing current crowding effects in serpentine resistor 53

82 In order to model the four stated building blocks, two test structures were built (Figure 4.3-4). For clarity, the ground lines and pads are not shown in the figure, but the two test structures are designed for compatibility with a ground-signal-ground coplanar probe system. The first test structure is simply a line with probe pads on its ends; the purpose of this structure is to help characterize basic uncoupled material parameters, including self resistance, inductance, and capacitance. The second test structure is a 3- segment meander resistor; this structure allows passive characterization of the U-shaped corner segments as well as line to line mutual inductance and coupling capacitance. The structures were characterized using D.C. measurements to determine resistances and network analysis techniques up to 20GHz so that parasitics would be observable in the S- parameter response. Pad Primitive Material Square Primitive Coupled Square Primitive U-Shaped Bend Primitive Figure Test structures and primitives for meander resistor modeling. 54

83 It is of interest to note that a structure with first order coupling is actually a 4-port structure, whereas the test structures themselves are only 2-port devices, and thus only standard and repeatable 2-port measurements are necessary. A 4-port device is considerably more difficult to measure in practice than a 2-port, since many different excitation and loading iterations are required. To consider second and higher order coupling requires 6 (or more) port devices, at which point accurate measurement may be prohibitively difficult. Our method of simply measuring two port structures and extracting all required multiport information is a significant advantage over attempting to measure coupling between physically disconnected devices Processing and Measurement The test structure design was deposited on a 96 % alumina substrate which had a surface roughness of approximately +/- 1.5 µm. All processing was done at the Georgia Tech Microelectronics Research Center by MiRC cleanroom staff and students. The processing details can be found in Appendix C. A photograph of the fabricated structures is shown in Figure The test structures were measured using network analysis techniques, a DC curve tracer, and a high precision multimeter. For the high frequency measurements, a HP 8510C network analyzer was used in conjunction with a Cascade Microtech probe station and ground-signal-ground configuration probes. Calibration was accomplished using a supplied substrate and utilization of the line-reflect-match (LRM) calibration method. 55

84 Data was gathered for each of the test structures at over 200 frequency points between 500MHz and 20GHz and stored with the aid of computer data acquisition software and equipment. DC I-V measurements of the test structures were also made in order to determine component resistances. At DC, parasitic capacitance and inductance have no effect on the response and the measured resistance value, once properly apportioned, can be used directly in the models of the building blocks. Figure Photograph of fabricated structures for meander resistor modeling. 56

85 Figure Photograph of predictively modeled 9 segment resistor 4.5. Modeling and Parameter Extraction At this stage, the objective is to generate circuit models for each of the defined building blocks. The circuit topologies for the uncoupled and coupled building blocks are shown in Figure As discussed in Chapter 3, the fundamental circuit is based on the partial element equivalent circuit (PEEC) [39] which has been used for interconnect analysis [40] and general three dimensional high frequency structure simulation [50]. Coupling behavior is represented by the coupling capacitance between the middle nodes of the two PEEC circuits, as well as by mutual inductances between the left upper and left lower branch inductors in the model, and likewise, for the right hand side. These circuits represent models for the building blocks only; the test structure and resistor 57

86 circuits are comprised of many of the building block circuits connected in accordance with the structure geometry Sensitivity Analysis In order to determine whether individual building block circuit components could be deembedded from the designed test structures, a sensitivity analysis was performed. The sensitivity analysis was performed on the test structure equivalent circuits with respect to each building block circuit parameter that was desired to extracted. The results of the sensitivity analysis showed exactly how the S-parameters varied when one circuit parameter was differentially modified. Normalized plots of the various sensitivities are shown. In general, a non-zero non-flat response shows that the output is affected by the parameter over frequency, and thus should be extractable. Test structure 1 sensitivity plots are shown in Figure to Figure As can be seen from the plots, all parameters affect the output in at least one of the real or imaginary parts of the S-parameters, except for some of the pad parameters and shunt capacitances. Clearly though, the response of the structure is dominated by inductive effects. Test structure 1 sensitivity plots are shown in Figure Figure Here also, the output parameters are quite sensitive to all parameters for both the coupled line and U-shaped bend building blocks, except for shunt and coupling capacitances. Additionally, it is interesting to note that mutual inductance starts becoming increasingly important at higher frequencies. 58

87 1.5 1 Normalized Sensitivity L S11 (R) L S11(I) L S21(R) L S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to line inductance in the uncoupled square building block in test structure Normalized Sensitivity C S11 (R) C S11(I) C S21(R) C S21(I) 1.00E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to capacitance to ground in the uncoupled square building block for test structure 1. 59

88 1 0.8 R S11 (R) R S11(I) R S21(R) R S21(I) Normalized Sensitivity E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to line resistance in the uncoupled square building block in test structure Normalized Sensitivity CC S11 (R) CC S11(I) CC S21(R) CC S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to shunt capacitance in the uncoupled square building block in test structure 1. 60

89 Normalized Sensitivity CPAD S11 (R) CPAD S11(I) CPAD S21(R) CPAD S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to capacitance to ground in the probe pad building block in test structure Normalized Sensitivity LPAD S11 (R) LPAD S11(I) LPAD S21(R) LPAD S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to line inductance in the probe pad building block in test structure 1. 61

90 Normalized Sensitivity RPAD S11 (R) RPAD S11(I) RPAD S21(R) RPAD S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to line resistance in the probe pad building block test structure Normalized Sensitivity CCPAD S11 (R) CCPAD S11(I) CCPAD S21(R) CCPAD S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to shunt capacitance in the probe pad building block in test structure 1. 62

91 Normalized Sensitivity C S11 (R) C S11(I) -0.5 C S21(R) C S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to capacitance to ground in the coupled squares building block in test structure Normalized Sensitivity LM S11 (R) LM S11(I) -0.2 LM S21(R) LM S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to mutual inductance in the coupled squares building block in test structure 2. 63

92 Normalized Sensitivity CM S11 (R) CM S11(I) CM S21(R) CM S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to coupling capacitance in the coupled squares building block in test structure Normalized Sensitivity C2 S11 (R) C2 S11(I) C2 S21(R) C2 S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to capacitance to ground in the U- shaped building block in test structure 2. 64

93 Normalized Sensitivity R2 S11 (R) R2 S11(I) R2 S21(R) R2 S21(I) 1.00E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to line resistance in the U-shaped building block in test structure Normalized Sensitivity L2 S11 (R) -0.2 L2 S11(I) L2 S21(R) L2 S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to line inductance in the U-shaped building block in test structure 2. 65

94 Normalized Sensitivity CC S11 (R) CC S11(I) CC S21(R) CC S21(I) E E E E+11 Frequency (Hz) Figure S 21 and S 11 sensitivity with respect to shunt capacitance in the U- shaped building block in test structure Model Extraction The extraction of the circuit model parameters was achieved in several steps. Due to the highly nonlinear nature of the generated system equations with respect to circuit parameter values, a procedure of hierarchical optimization with respect to measured S- parameter and DC resistance data was chosen. All optimizations and simulations were done using the Hspice circuit simulator on Sun Sparcstation 20 series workstations. The starting point or initial guesses of the circuit parameters were crucial for correct optimization results, and in order to achieve this, an initial optimization was done assuming that each test structure was comprised of just one building block, utilized repetitively across the length of the structure on a per square basis. The initial guess for 66

95 these circuit parameters were derived from the measured S-parameters in a test structure, and then dividing by the number of blocks used in order to extract the valid R,L,C, and CC values for the circuit model. This method was very effective for obtaining a good starting point for the optimizations of the test structure circuits. The first test structure optimized was structure 1 shown in Figure The goal was to extract the parameters of the contact pad and the uncoupled material square. The initial guesses were inserted, and the circuit was optimized with respect to measurements up to 10GHz. Once the optimization was complete, the computed models were taken and used as valid model parameters for their respective building blocks for test structure 2, shown in Figure The remaining parameters to be computed for this structure were the line to line coupling parameters (mutual inductance and coupling capacitance), and the parameters for the U-shaped corner. Additionally, line to ground capacitance had to be recomputed for the material square primitive in the presence of adjacent lines. Optimizations were done on measurements performed up to 10GHz. Both optimizations completed with very low residual sum of squares error, indicating accurate results. The modeling results for test structure 1 and 2 are shown in Figure and Figure respectively. The various circuit models and parameters for the different building blocks are shown in Figure

96 1 2 Probe Pad Bldg. Block CC CC 1 2 R L L R C R=0.08 Ohm L= 1.2E-11 H C = 1.4e-15 F CC = 1.8e-15 F Coupled Line Bldg. Block 2 CC 1 L M CC R L L R C C M CC R L L R C 4 CC L M 3 R=0.09 Ohm L= 1E-11 H C = 1.1e-15 F CM=0.4e-15 F CC = 1.4e-15 F LM = U-Shaped Bend Bldg. Block CC CC 1 2 R L L R C R=0.4 Ohm L= 3.7E-11 H C = 5.3e-15 F CC=2.7e-15 F 1 2 Uncoupled Line Bldg. Block 1 CC CC R L L R 2 C R=0.08 Ohm L= 1E-11 H C = 2.7e-15 F CC = 1.2e-15 F Figure Building blocks, equivalent circuits and parameter values for serpentine resistor modeling. 68

97 1.00E E E E-01 S21(R) Measured S21(R) Modeled S21(I) Measured S21(I) Modeled Real S E E+00 Imaginary -2.00E E E E E E E+11 Frequency (Hertz) 2.50E E-01 S11(R) Measured S11(R) Modeled S11(I) Measured S11(I) Modeled S E E-01 Imaginary Real 5.00E E E E E E+11 Frequency (Hertz) Figure Measured vs. modeled results for test structure 1. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response. 69

98 S21(R) Measured S21(R) Modeled S21(I) Measured S21(I) Modeled Real S Imaginary E E E E+11 Frequency (Hertz) S11(R) Measured S11(R) Modeled S11(I) Measured S11(I) Modeled S Imaginary 0.05 Real E E E E+11 Frequency (Hertz) Figure Measured vs. modeled results for test structure 2. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response. 70

99 4.6. Results The computed fundamental building block models were used to predict the behavior of a 9 segment meander resistor constructed using a combination of those blocks. The resistor was then used in several simple circuits to assess the accuracy of the model in common applications. An equivalent circuit of the resistor was constructed by replacing each building block in the structure with its equivalent extracted circuit (Figure 4.6-1). Since only first level coupling was taken into account, each material square in each segment of the resistor was coupled to its nearest neighbor by a pair of mutual inductances and a coupling capacitance. As inferred from the circuit description, the resulting circuit of the 25µm linewidth and 300µm length per segment 9 segment resistor was a complex, highly interconnected system, consisting of approximately 700 nodes. The longest path length of the resistor was approximately 0.35 wavelengths long at 10GHz. In spite of the large circuit size, AC small signal analysis proceeded very quickly, with the entire circuit simulation completed in under 2 minutes. The predicted S- parameters were compared to measured values of the same structure; the results are shown in Figure Both real and imaginary parts of S 11 and S 21 were well predicted up to 5GHz. In comparison, the same structure was designed and simulated in a method of moments solver with a 3GHz meshing frequency. The structure required 72 min. to complete, while consuming approximately 50MB of system memory and utilizing 2 processors in a multiprocessing Sun workstation. Thus, for this example, a speedup factor 71

100 of approximately 35 was obtained. For more complex structures, simulation time of the method of moments solver would increase dramatically, whereas using our approach, simulation time would increase only with the number of elements in the equivalent circuit. Coupled Line Building Block U Building Block Uncoupled Line Building Block Figure Serpentine resistor and associated building blocks. 72

101 S21(R) Measured S21(R) Predicted (This Paper) S21(I) Measured S21(I) Predicted (This Paper) Real S Imaginary E E E E+11 Frequency (Hertz) S11(R) Measured S11(R) Predicted (This Paper) S11(I) Measured S11(I) Predicted (This Paper) S Real Imaginary E E E E+11 Frequency (Hertz) Figure Measured vs. predicted results for 9 segment resistor. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response. 73

102 In addition to confirming an S-parameter match between predicted and measured values, two of these resistors connected in a voltage divider configuration was also considered. Since an actual divider structure was not constructed, the target response was generated by using the measured S-parameters of the resistor as a model, and constructing an equivalent circuit in a RF simulator that was able to utilize the measured data directly (Hewlett Packard MDS). The circuit is shown in Figure The divider circuit generated with our modeling approach was created using standard SPICE netlist techniques. The circuit model for the 9-segment resistor was enclosed within a subcircuit, and then two subcircuits were used to construct the divider. The simulated response of both MDS and the circuit simulator are shown in Figure The predicted resistor model circuit response models the divider behavior extremely well, matching the results generated by MDS up to approximately 10 GHz. In addition, the unusual voltage divider peaking behavior of the MDS response beyond 10 GHz was mimicked by our circuit, with the voltage peak frequency predicted slightly earlier in this case. X X=9 Segment Resistor X + Vout - Figure Resistor divider circuit. 74

103 15 Voltage Magnitude (db) Predicted (This Paper) MDS Result E E E E E+11 Frequency (Hertz) 20 Voltage Phase (degrees) Predicted (This Paper) MDS Result E E E E E+11 Frequency (Hertz) Figure MDS generated vs. predicted results for voltage divider circuit. (a) Voltage magnitude response. (b) Voltage phase response. 75

104 The resistor model was also tested in a 6 segment LC circuit, with the resistor used as a termination. The inductance and capacitance were chosen such that a characteristic impedance per segment of 50Ω was obtained. The circuit is shown in Figure The circuit was again simulated in both MDS (using measured parameters) and in the circuit simulator using the constructed model, but this time, a two port S- parameter simulation was done. The results of the simulation are shown in Figure Both S 11 and S 21, real and imaginary parts are predicted well up to 20GHz. For comparison purposes, the circuit performance using an ideal resistor is shown also in Figure From these plots it is evident that the ideal resistor model does not predict high frequency behavior well. Both circuits simulated here clearly illustrate the importance of modeling resistive passive components along with their associated parasitics in order to obtain accurate simulation results at high frequencies. Port 1 L C L C L C L C L C L C X Port 2 X=9 Segment Resistor L=1nH C = 0.4pF Figure Segment LC circuit with 9 segment resistor used as termination. 76

105 S21(R) MDS S21(R) - This Paper S21(I) MDS S21(I) - This Paper Real S Imaginary E E E+10 Frequency (Hertz) S11(R) MDS S11(R) - This Paper S11(I) MDS S11(I) - This Paper 0.4 S Imaginary -0.6 Real E E E+10 Frequency (Hertz) Figure MDS generated vs. predicted results for 6 segment LC circuit with resistive termination. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response. 77

106 1.00E E E E E-01 S21(R) MDS S21(R) - Ideal R S21(I) MDS S21(I) - Ideal R Real S E E E-01 Imaginary -6.00E E E E E E+10 Frequency (Hertz) 1.00E E E-01 S11(R) MDS S11(R) - Ideal R S11(I) MDS S11(I) - Ideal R 4.00E-01 S E E+00 Imaginary -2.00E E E-01 Real -8.00E E E E+10 Frequency (Hertz) Figure MDS generated vs. results using ideal 17.88Ω resistor for 6 segment LC circuit. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response. 78

107 4.7. Summary In this chapter, accurate modeling of serpentine resistors using the modeling methodology described earlier in this thesis has been achieved and verified experimentally. The entire procedure has been described in detail, including building block and test structure development, equivalent circuit extraction, and model verification, with results presented at each stage. The models have shown accuracy up to ~10 GHz in both direct resistor models as well as within circuits, with simulation speeds far greater than that of conventional electromagnetic or RF simulators. This procedure creates highly flexible circuit level models of the resistors, which are extremely useful since they can be incorporated into the circuit design stage to investigate how they will affect circuit performance, and which cannot easily be obtained from method of moments or other conventional non-lumped element simulation and modeling methods. Additionally, the method is very well suited for circuit design applications, since resistor designs can be changed incrementally, and behavior predictions can be obtained very quickly. In the next chapter, the application of the method to interdigital capacitor modeling will be discussed. 79

108 CHAPTER V MODELING OF INTERDIGITAL CAPACITORS 5.1. Introduction Interdigital capacitors (IDCs) play an important role in integrated electrical systems. They are used in a wide variety of circuits, including resonators, oscillators, and filters, just to name a few. IDCs are used to perform functions including DC blocking, frequency filtering and impedance transformation. They are cheap to manufacture, since they are planar devices, unlike the parallel plate or metal-insulator-metal (MIM) variety. In high frequency systems which use these devices, accurate models of them must be obtained in order to model their behavior at high frequencies. As in the case with the resistors, IDCs suffer from many parasitic effects which can cause them to resonate or behave unexpectedly at high frequencies, and capturing these effects is of paramount importance in order to accurately model systems which use them. In this chapter the application of the developed modeling methodology is applied to the modeling of interdigital capacitors. As will be shown, accurate predictive modeling results of a 10 segment interdigital capacitor have been obtained and verified experimentally up to 5-10 GHz frequency range. Additionally the behavior of a 80

109 fabricated series resistor-capacitor circuit is predicted and verified by constructing a resonant tank circuit in a microwave circuit simulator (Hewlett Packard Microwave Design System (MDS)) using an ideal inductance and the measured RC data against an actual model constructed using the presented method, with good results Modeling Procedure Modeling of interdigital capacitors proceeded in the method described in Chapter 3. A brief description of the various steps involved is now presented. 1. The first step involved a determination of what geometry structures were to be considered and allowed in order to set up a practical set of building blocks and test structures to be measured and characterized. 2. This step required entering the geometry of a target structure into the custom current flow visualization software in order to determine the nature of the current distribution through the device. Building blocks were to be cut along cross sections of uniform current distribution only. In this case, the current visualization software was unable to handle physically disjoint structures, so geometrically equivalent joint structures were used. 3. Once the various building blocks had been determined, the next step was to design test structures the help model the various building blocks accurately. Additionally, a 81

110 sensitivity analysis needed to be performed on the test structure equivalent circuits to ensure that the various parameters could be accurately deembedded. 4. At this point, test structures are fabricated and tested. High frequency network analysis and DC resistance measurements are taken. 5. Test data is used to form optimization input files for the test structures. Initial guesses are made based on the measured results for each structure. Once optimization for one structure is complete, the results are used for the remaining optimizations. 6. Circuit models of the building blocks are obtained Detailed Modeling Procedure The first step involved in the interdigital capacitor and resistor modeling procedure was a determination of which geometry structures were to be modeled. Since the theoretical number of possible layouts for these devices is infinite, a restricted set had to be defined in order to determine a sufficiently small set of primitive blocks that would require characterization. Although at first glance, this type of restriction would seem harsh, it is not impractical. Even with only one linewidth and interline spacing allowed, a huge array of devices can be designed with large line lengths and many segments. The described procedure is equally applicable to electrically long and short structures, since the only limiting factor in this method is the accuracy of the building block, and not on how many are used. 82

111 For the devices discussed in this paper, equal linewidths and spacings of 30 um were considered. The basic structure of the capacitor and resistor lead to the identification of 5 fundamental building blocks that required characterization (Figure 5.3-1). The resistor blocks were the same as those discussed in chapter 5. The first building block was simply a 30um x 30um square of material connected on two opposite sides by additional material. The second building block was two interacting, but physically disconnected squares of material to account for codirectional and contradirectional coupling between segments. The third and fourth blocks were a U-shaped piece of material, used in serpentine resistors to connect adjacent line segments together, and a shielded stub piece to model the end of a capacitor finger surrounded on three sides by the conductor of the opposite terminal. The fifth block was simply a probe pad with a short 1 square stub, necessitated by the fact that all the test structures that would be required to model these blocks needed to be physically tested by probing. 83

112 Material Square Building Block Pad Building Block First Order Coupled Building Block Shielded Stub Building Block Figure Interdigital capacitor and associated building blocks. A representative ladder structure was input in to the current visualization software and analyzed. The output current density and contour plots are shown in Figure and Figure According to the structure geometry, it was assumed that the majority of nonuniform current flow would occur in the T-shaped region connecting the long vertical section and the horizontal segments together, and this could be approximated with a ladder shaped structure. Although the T-section did represent a region of nonuniform current flow, due to a lack of coupling information between the T and the opposite terminal conductor segment, the T section itself was not used as a building block. Instead, a hybrid building block was constructed which comprised 2 adjacent ½ T-sections and 84

113 the stub of the opposite conductor finger, and was named the shielded stub building block (Figure 5.5-1). Examination of the output plots from the current visualization software lead to the determination of the geometries of the various building blocks. The single square and the coupled square building blocks were only one square in width as expected. The U shaped block was a total of 7 squares in length with the two horizontal sections of the U extending for a length of 3 squares each in order for the current flow distribution to be constant across the boundaries of the building block. For the same underlying reason, the shielded stub primitive was determined to be 9 squares long. The probe pad primitive was the same size as previously mentioned due to the simple current flow through the feed line interface and into the actual device. Figure Contour and indexed color intensity plots of current distribution in ladder shaped structure. 85

114 Figure Contour plot of current in T-shaped section within ladder structure. Three test structures were built in order to model the stated building blocks, (Figure 5.3-4). The test structures are designed for compatibility with a ground-signalground coplanar probe system, but for clarity, the ground lines and pads are not shown in the figure. The first test structure is simply a line with probe pads on its ends; the purpose of this structure is to help characterize basic uncoupled material parameters, including self resistance, inductance, and capacitance. The second test structure is a 3-segment meander resistor; this structure allows passive characterization of the U-shaped corner segments as well as line to line mutual inductance and coupling capacitance. The third structure is a simple interdigital capacitor. The purpose of this structure is to help characterize the shielded stub primitive and also refine coupling capacitances. As might 86

115 be expected, mutual inductances have almost no effect on this structure until the device is conducting at high frequencies. Test Structure 1 Test Structure 2 Pad Primitive Material Square Primitive Coupled Square Primitive U-Shaped Bend Primitive Test Structure 3 Shielded Stub Primitive Figure Test structures and building blocks for interdigital capacitor and serpentine resistor modeling. 87

116 5.4. Processing and Measurement The test structure resistor material was Ti/Au deposited on a 96% alumina substrate. An electron beam evaporation system was used to deposit 0.04µm of titanium followed by a 0.2 µm layer of gold. The thin layer of titanium was used to improve adhesion of the gold to the substrate. Following deposition, the resistors were defined using standard photolithography and etch back. The photoresist was hard baked for five minutes at 125 C in order to stabilize it before etching. The gold was etched in a heated KCN solution for 1 minute followed by a buffered oxide etch to remove the titanium. Due to the surface roughness of the substrate - approximately +/- 1.5 µm, the edges of the resistor were jagged, but the lines were continuous. A photograph of several fabricated structures are shown in Figure 5.4-1, Figure 5.4-2, and Figure The test structures were measured using a network analyzer, and a high precision multimeter. For the high frequency measurements, a HP 8510C network analyzer was used in conjunction with a Cascade Microtech probe station and ground-signal-ground configuration coplanar probes. Calibration was accomplished using a supplied impedance standard substrate and utilization of the line-reflect-match (LRM) calibration method. Data was gathered for each of the test structures at over 200 frequency points between 45MHz and 20GHz and stored with the aid of computer data acquisition software and equipment. 88

117 Figure Fabricated interdigital capacitor - test structure 3. Figure Fabricated interdigital capacitor 10 segment capacitor predictively modeled. 89

118 Figure Fabricated RC structure predictively modeled Modeling and Parameter Extraction Following measurement of test structures, the next step is to extract circuit models for all the building blocks from which the test structures are comprised. As with the resistor case, the fundamental circuit used is the partial element equivalent circuit (PEEC) which has been used extensively for interconnect and arbitrary shaped conductor high frequency analysis. The PEEC circuit takes into account couplings, but does not take into account retardation effects. Depending on actual building block geometries, the PEEC circuit model is modified as needed. For example, for modeling of coupling behavior, coupling capacitances and mutual inductances are included between parallel segments, 90

119 and for complex geometries, such as the shielded stub, additional elements and ports are added as well. The building blocks, extracted circuits and parameter values are shown in Figure Sensitivity Analysis A sensitivity analysis was performed on the test structures with respect to the individual building block circuit components to determine their relative importance and the level of influence on the test structure S-parameter output responses. The sensitivity responses for test structures 1 and 2 are not shown here since they are almost identical to the sensitivities obtained in the serpentine resistor modeling case, since the same test structures were used there (although fabricated on a different run). The reader is referred to chapter 5 for an investigation of these results. Results for test structure 3 are presented here. A significant difference in sensitivity to different circuit parameters is shown here when compared to the other two cases, mainly due to the fact that the two terminals of the structure are physically disconnected. In particular, there is very low sensitivity to inductance, especially at low frequencies, in both self and mutual inductances. This is easily explained by the fact that current flow is practically zero at low frequencies, but begins to increase at higher frequencies as the capacitor begins to conduct. Clearly, for accurate inductance extractions, results from the fully connected structures must be used, due to their high degree of sensitivity of S-parameters to the various inductances. 91

120 From the sensitivity response plots, it is evident that for interdigital capacitors, the most critical parameters are coupling capacitance, the capacitance between the shield and the opposite conductor in the shielded stub primitive, followed by line to ground capacitances. The next tier of importance goes to line and mutual inductances which start becoming important at higher frequencies. Line resistance have a relatively small effect in the frequency range of interest, since the IDC test structure is essentially an open circuit, and thus exhibits very high impedance Normalized Sensitivity DCM S11(R) DCM S11(I) -0.4 DCM S21(R) DCM S21(I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line to line coupling capacitance (CM). 92

121 Normalized Sensitivity DCC2 S11(R) DCC2 S11(I) -0.1 DCC2 S21(R) DCC2 S21(I) 1.00E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to stub to line coupling capacitance (C2) in the shielded stub Normalized Sensitivity DCSQ S11(R) -0.2 DCSQ S11(I) DCSQ S21(R) DCSQ S21(I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line to ground capacitance in the IDC fingers. 93

122 Normalized Sensitivity DCC S11(R) -0.1 DCC S11(I) DCC S21(R) DCC S21(I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line to ground capacitance in the shielded stub Normalized Sensitivity DLSQ S11(R) DLSQ S11(I) DLSQ S21(R) DLSQ S21(I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line inductance in finger segments. 94

123 Normalized Sensitivity DLC S11(R) DLC S11(I) DLC S21(R) DLC S21(I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line inductance in shielded stub Normalized Sensitivity DLM S11(R) DLM S11(I) DLM S21(R) DLM S21(I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line to line mutual inductance between finger segments. 95

124 Normalized Sensitivity DRSQ S11(R) DRSQ S11(I) DRSQ S21(R) DRSQ S21(I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line resistance in finger segments Normalized Sensitivity DRC S11(R) DRC S11(I) DRC S21(R) DRC S21(I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line resistance in shielded stub. 96

125 Model Extraction Circuit model parameter extraction proceeded in several steps. Due to the highly nonlinear nature of the problem, a procedure of hierarchical optimization with respect to measured S-parameter and DC data was chosen. Initial guesses for the various parameters were derived from actual measurement data. All optimizations and simulations were done using the Hspice circuit simulator on Sun SPARCstation 20 series workstations. Details of the extraction method can be found in chapter 3. Test structure 1 was initially optimized in order to extract the parameters of the contact pad and the uncoupled material square. The initial guesses were inserted, and the circuit was optimized with respect to measurements up to 10GHz. Once the optimization was complete, the computed models were taken and used as valid model parameters for their respective building blocks for test structure 2. The parameters to be computed for this structure were the first order line to line coupling parameters (mutual inductance and coupling capacitance), and the parameters for the U-shaped corner. Additionally, line to ground capacitance needed to be recomputed for the material square building block in the presence of adjacent lines. Lastly, the third test structure was optimized to extract the value of the shielded stub primitive and to refine the values of the coupling capacitances. All optimizations completed with very low residual sum of squares error, indicating accurate results. The modeling results for test structures 1, 2 and 3 are shown in Figure 5.5-2, Figure 5.5-3, and Figure respectively. The extracted circuit models and parameters are shown in Figure

126 1 2 Uncoupled Line Bldg. Block C C CC 1 2 R L L R C R=0.07 Ohm L= 1E-11 H C = 2.9e-15 F CC = 1.2e-15 F Coupled Line Bldg. Block Shielded Stub Bldg. Block 1 CC 1 L M R L L R C R L L R C C2 CC C M 2 CC 4 R L L R C C C L M R=0.07 Ohm L= 1E-11 H C = 1.1e-15 F CM=1.9e-15 F CC = 1.2e-15 F LM = R=0.6 Ohm L= 1E-10 H C = 7.1e-15 F C2=3.3e-15 F 1 2 Probe Pad Bldg. Block CC C C 1 2 R L L R C R=0.08 Ohm L= 1.2E-11 H C = 3.6e-15 F CC = 1.5e-15 F 1 2 U-Shaped Bend Bldg. Block CC C C 1 2 R L L R C R=0.3 Ohm L= 3.7E-11 H C = 5.3e-15 F CC=2.7e-15 F Figure Building blocks, equivalent circuits, and parameters for IDC and resistor modeling. 98

127 5.00E E E E-01 Meas. S11(R) Modeled S11(R) Meas. S11(I) Modeled S11(I) 3.00E-01 S E E E E E E E E E E+11 Frequency (Hertz) 1.00E E E E E-01 Meas. S21(R) Modeled S21(R) Meas. S21(I) Modeled S21(I) S E E E E E E E E E E+11 Frequency (Hertz) Figure S-parameter measured and modeled results for test structure 1. 99

128 3.50E E E-01 Meas. S11(R) Modeled S11(R) Meas. S11(I) Modeled S11(I) S E E E E E E E E+10 Frequency (Hertz) 1.00E E E E-01 Meas. S21(R) Modeled S21(R) Meas. S21(I) Modeled S21(I) S E E E E E E E E+10 Frequency (Hertz) Figure S-parameter measured and modeled results for test structure

129 1.00E E E E-01 Meas. S11(R) Modeled S11(R) Meas. S11(I) Modeled S11(I) 2.00E-01 S E E E E E E E E E+10 Frequency (Hertz) 5.00E E E-01 Meas. S21(R) Modeled S21(R) Meas. S21(I) Modeled S21(I) S E E E E E E E+10 Frequency (Hertz) Figure S-parameter measured and modeled results for test structure

130 5.6. Results The extracted building blocks were used to predict the behavior of a ten segment interdigital capacitor, with each segment having a line length of 600 um. In addition, a series resistor capacitor structure was fabricated, and the behavior of a RLC resonator circuit was predicted. The RLC resonator circuit itself was not fabricated, but its behavior was simulated by use of the HP MDS simulator which is able to take measured S- parameter datasets and use them directly as models of structures. Both the capacitor and RC circuit were modeled in Hspice by constructing them out of the building block pieces. The performance of the capacitor was compared against measured data, and the performance of the RLC resonant circuit was compared against the output generated from MDS. The equivalent circuit for the interdigital capacitor was constructed by replacing the different geometrical sections with the applicable building block circuit models. Each square of material in the finger segment was modeled with coupled building blocks, which were cascaded in order to generate the required line length. Since only first order coupling was considered, coupling only to the nearest neighbor pieces of material was considered. The ends of each finger were modeled by replacing the stub and surrounding material by the shielded stub primitive, and the probe pads were modeled with their associated circuits. The various building blocks and their locations in the capacitor are shown above in Figure Since most of the building blocks occurred in a regular and repetitive manner, many subcircuit calls could be used to simplify the overall circuit 102

131 construction. The finished circuit was quite complex, with over 1000 nodes, but AC analysis completed in under a minute. The predicted and measured results are shown in Figure As can be seen, the building block based prediction agrees very well with actual measurements, in both the S11 and S21 responses, up to approximately 10 GHz. The next structure considered was the resistor-capacitor series circuit. A 9- segment serpentine resistor with each segment being 600 µm long was placed in series with the 10 finger interdigital capacitor (Figure 5.4-3). An important point to note here is that the longest line segment in this system is over 5.6 mm in length, which is electrically over 3/5 wavelength long at 10 GHz. The equivalent circuit for this system was developed using the same procedure as above, except that the parallel coupled lines in the resistor were connected together by the U shaped building block circuit. Once the circuit for the series RC circuit was obtained, it was used to predict the voltage magnitude and phase response of a RLC resonant circuit terminated in a 50 Ω impedance (Figure 5.6-1). 103

132 L = 10nH Vout R Series RC C 50 Ohm Figure RLC resonant tank circuit. The RLC resonator is a good demonstration circuit since both capacitance and resistance need to be modeled correctly in order to predict the output resonance point and the shape of the curve. As mentioned earlier, the actual response of the RLC resonator was generated artificially from the HP MDS circuit simulator, in which the RC series combination was modeled using the measured S-parameter data directly. The voltage magnitude and phase data was then compared to results obtained from simulations of the building block based equivalent circuit. The results are shown in Figure As can be seen, we have extremely good agreement in both magnitude and phase responses up to approximately 10 GHz. The point of resonance is predicted well, with only a slight divergence developing beyond that point. 104

133 1.00E E E E-01 Meas. S11(R) Predicted S11(R) Meas. S11(I) Predicted S11(I) 2.00E-01 S E E E E E E E E E+10 Frequency (Hertz) 5.00E E E-01 Meas. S21(R) Predicted S21(R) Meas. S21(I) Predicted S21(I) S E E E E E E E E+10 Frequency (Hertz) Figure Measured and predicted results for 10 segment interdigital capacitor. 105

134 0-5 Voltage Magnitude(dB) V(dB) - MDS V(dB) - Predicted 1.00E E E+10 Frequency (Hz) Voltage Phase (degrees) V(Phase) - MDS V(Phase) - Predicted 1.00E E E+10 Frequency (Hz) Figure Actual (MDS) and predicted resonator voltage magnitude and phase. 106

135 5.7. Conclusion In this chapter, the modeling method presented in this thesis has been applied to the modeling of interdigital capacitors and also to a series resistor capacitor circuit. A 10 segment interdigital capacitor and a electrically long series serpentine resistor capacitor structure have been modeled predictively with accurate results up to 10 GHz, only using data gathered from 3 test structures. In addition, the resonance of a RLC tank circuit has been predicted well using the developed models. Complete circuit models of all the structures have been developed, and fast simulation speeds on the order of a few minutes have been obtained. In the next chapter, the modeling method will be applied to the modeling of a spiral inductor. 107

136 CHAPTER VI MODELING OF PLANAR SPIRAL INDUCTORS 6.1. Introduction Planar spiral inductors are used extensively in modern integrated circuits, in both silicon and gallium arsenide technologies. They are particularly common in microwave integrated circuits where they usually are an integral component within the system. These spiral inductors are usually important enough in these type of circuits that it is not uncommon that they occupy 50% or more of overall integrated circuit die area. Inductors are used in key circuit building blocks such as oscillators, matching circuits and filters. Inductors are usually designed to have current flowing in a spiral pattern to generate mutual inductance between currents traveling in the same direction within a structure. For standard components, this has meant that the inductor usually consists of a core with a solenoid around it. These kind of structures have not been very amenable to miniaturization in the surface mount arena, and as a result they have tended to remain quite large, and considerably more so than their resistor and capacitor counterparts. Miniaturization and integration of inductors is very attractive, whenever system size reductions and board space conservation are important. 108

137 Successful design of systems using spiral inductors requires that accurate models of them exist, particularly at high frequencies. It is particularly important to account for losses (both substrate and conductor) to correctly predict the quality (Q) factor, which is very important for designs. Accurate models of spiral inductors are quite difficult to obtain, and they usually do not predict Q factors well. In this chapter the developed modeling methodology will be applied to the predictive modeling of spiral inductors. Accurate results as compared to a method-of-moments simulator will be shown for a 4 turn spiral inductor for both Q-factor and Z-parameter responses up to and exceeding the first self-resonance. In addition, the model validity will be verified in several different LC resonant circuits, with good results Modeling Procedure Modeling of spiral inductors proceeded using the same flow as was discussed in Chapter 3. The various step involved are now briefly described. 1. The first step involved a determination of what geometry structures were to be considered and allowed in order to set up a practical set of building blocks and test structures to be measured and characterized. In this case, considerably larger structures were considered than in the previous resistor and capacitor examples. 2. In this phase, the actual geometries of the various building blocks are determined. This is accomplished by entering the geometry of a target structure into the custom current flow visualization software and examining the output current distribution. 109

138 Building block boundaries are cut across sections of approximately uniform current distribution only. 3. Once the various building blocks have been determined, the next step is to design test structures the help model the various building blocks accurately. Additionally, a sensitivity analysis is performed on the test structure equivalent circuits to ensure that the various parameters can be accurately deembedded. 4. At this point, test structures are fabricated and tested. High frequency network analysis and DC resistance measurements are taken. In this case, test structures and the devices were not actually fabricated, due to the unavailability of a two layer process. All structures were simulated in a method of moments (MoM) simulator to approximate actual fabricated behavior. 5. MoM simulation data is used to form optimization input files for the test structures. Initial guesses are made based on the measured results for each structure. Once optimization for one structure is complete, the results are used for the remaining optimizations. 6. Circuit models of the building blocks are obtained. The models, with associated design rules are combined in a library which can then be used for device and circuit design applications. 110

139 6.3. Detailed Modeling Procedure The first step involved in the spiral inductor modeling procedure was a determination of which geometry structures were to be modeled. As in the earlier cases, a restricted set was defined in order to simplify the problem. The set size, though small, was still adequate to help model a wide range of different structures. For modeling inductors, much larger block sizes were used than was the case for either the serpentine resistors or interdigital capacitors. For the devices discussed in this chapter, equal linewidths and spacings of 10 mils (250 µm) were considered. The basic structure of the inductors lead to the identification of 3 fundamental building blocks that required characterization (Figure 6.3-1). The first building block was simply a 10 mil x 10 mil square of material connected on two opposite sides by additional material. The second building block was two interacting, but physically disconnected squares of material to account for capacitive and inductive coupling between segments. The third and fourth blocks were a U-shaped piece of material, used in the second test structure to connect adjacent line segments together, and a coupled corner piece to model corner effects and the coupling between two of them. The U-shaped piece itself is not needed for spiral inductor modeling, but it is required in the second test structure (shown below) that will be used. A pad was not used in this case since the structures were physically tested. The addition of a probe pad would not add any more test structures, however. 111

140 Coupled Corner Building Block Uncoupled Square Building Block Coupled Square Building Block Figure Spiral inductor and associated building blocks. A representative spiral inductor structure was input in to the current visualization software and analyzed. The output current density and contour plots are shown in Figure and Figure According to the structure geometry, it was assumed that the majority of nonuniform current flow would occur in the corner regions, and the presence of both X and Y directed gradients in those regions confirmed the assumption. Examination of the output plots from the current visualization software lead to the determination of the geometries of the various building blocks. The single square and the coupled square building blocks were only one square in width as expected due to the fact that their was no spatially differential current flow across their boundaries. The L shaped corner sections were taken to be 3 squares long (the corner square plus one square on 112

141 either side of the corner connection points) due to the fact that the current flow became uniform again about 1 ½ squares away from the corners. The U-shaped bend was taken to be 7 squares in length as in both the resistor and capacitor cases. As mentioned earlier, the U-shaped bend is not used directly in spiral inductor modeling, but is required in coupling capacitance and mutual inductance extraction in the second test structure, as will be described. Figure Indexed color intensity plots of current distribution in spiral inductor. 113

142 Figure Contour plot of X and Y directed current gradients showing current crowding in spiral inductor. Three test structures were built in order to model the stated building blocks, (Figure 6.3-4). The first test structure is simply a material line; the purpose of this structure is to help characterize basic uncoupled material parameters, including self resistance, inductance, and capacitance. The second test structure is a 3-segment meander resistor; this structure requires characterization of the U-shaped section even though it is not used in the spiral inductor, but its main purpose is to characterize line to line mutual inductance and coupling capacitance. The third structure is a coupled line with a coupled corner bend. The purpose of this structure is to help characterize the coupled corner building block. This structure also uses the U-shaped building block and the coupled line building blocks. 114

143 Test Structure 1 Uncoupled Material Square Test Structure 2 Coupled Material Square U shaped Bend Test Structure 3 Coupled Corner Primitive Figure Test structures and building blocks for spiral inductor modeling. 115

144 6.4. Method-of-Moments Simulation The test structures and benchmark spiral inductors were not actually fabricated for this research, due to the inaccessibility of a two layer high frequency process at that time. Instead, all structures were modeled in a 2 ½-D method of moments (MoM) simulator (Hewlett-Packard Momentum) in order to generate results that mimicked actual fabricated structure behavior. All simulations were run on four hypersparc processor Sun SPARCstation 20 series computers, equipped with 512 MB RAM and 4GB disk space. The MoM input substrate was 20 mil thick alumina of dielectric constant 9.6 with a ground plane present on the underside of the substrate. The simulations themselves were set up with a 3 GHz meshing frequency for S-parameter simulations from 100 MHz to 20 GHz. The conductor material was 10 mils wide, with a resistance of 0.1 Ω/square. Simulations for all the test structures completed within one hour each. A benchmark 4 turn spiral inductor was simulated for model verification purposes, but in this case, the simulation required over two hours complete Modeling and Parameter Extraction Once the simulations of the test structures had completed, the next step was to extract circuit models for all the building blocks from which the test structures were comprised. As with the resistor and capacitor cases, the fundamental circuit used for long 116

145 lengths of line was the unretarded partial element equivalent circuit (PEEC). Although the structures in this case were quite long electrically, and in spite of the fact that retardation was not modeled directly in the PEEC circuit, accurate results were still obtained. Depending upon actual building block geometries, the PEEC circuit model is modified as needed. For example, for modeling of coupling behavior, coupling capacitances and mutual inductances are included between parallel PEEC segments. The coupled corner building blocks are also modeled using coupled PEEC circuits for the actual corner sections but also including coupled material square building blocks on one edge, with the actual coupling component absorbed into the coupling portion of the corner coupling circuit parameters. The shown circuit model is duplicated on both sides of the diagonal cut line. The building blocks, extracted circuits and parameter values are shown in Figure Sensitivity Analysis A sensitivity analysis was performed on the test structures with respect to the individual building block circuit components to determine their relative importance and the level of influence on the test structure S-parameter output responses. Although the geometries of test structures 1 and 2 are similar to both those of the resistor and capacitor, they are much larger in actual dimensions. A square of material in this case was taken to be 10 x 10 mils (250 um x 250 um) in size, about a factor of eight larger than in the previous cases. All the test structures exhibit considerably different S-parameter 117

146 sensitivity responses to the individual circuit components than in previous cases, mainly because of much larger sizes. Sensitivities were computed using the finite difference method discussed in Chapter 3. Sensitivity plots for test structure 1 are shown in Figure to Figure 6.5-4, for test structure 2 in Figure to Figure , and for test structure 3 in Figure to Figure As can be seen in the plots, all parameters are capable of influencing the S-parameter response considerably, especially at higher frequencies, including resistance and shunt capacitance components. Due to the relatively high sensitivity responses of all the components, they could all be deembedded with repeatability from the circuit optimization procedure. As compared to the sensitivity plots generated from the resistor and capacitor structures, in this case all the parameter sensitivities were much higher because of the overall larger size of the structures. 118

147 Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 1 with respect to line-to-ground capacitance in the uncoupled square building block Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 1 with respect to line inductance in the uncoupled square building block. 119

148 Normalized Sensitivity S11 (R) S11 (I) -1.5 S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 1 with respect to line resistance in the uncoupled square building block Normalized Sensitivity S11 (R) S11 (I) -0.3 S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 1 with respect to shunt capacitance in the uncoupled square building block. 120

149 Normalized Sensitivity S11 (R) S11 (I) -8 S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 2 with respect to line-to-line coupling capacitance in the coupled squares building block Normalized Sensitivity S11 (R) S11 (I) -8 S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 2 with respect to line-to-ground capacitance in the U building block. 121

150 3 2 Normalized Sensitivity S11 (R) -2 S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 2 with respect to shunt capacitance in the U building block Normalized Sensitivity S11 (R) -6 S11 (I) -8 S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 2 with respect to line-to-line mutual inductance in the coupled squares building block. 122

151 Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 2 with respect to line-to-ground capacitance in the coupled squares building block Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 2 with respect to line inductance in the U-shaped building block. 123

152 Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line inductance in the uncoupled squares section of the coupled corner building block Normalized Sensitivity S11 (R) S11 (I) -4 S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line resistance in the uncoupled squares section of the coupled corner building block. 124

153 Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to shunt capacitance in the uncoupled squares section of the coupled corner building block Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line-to-line coupling capacitance in the coupled corner building block. 125

154 5 4 3 Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line-to-ground capacitance in the coupled corner building block Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to shunt capacitance in the coupled corner building block. 126

155 5 4 3 Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line-to-line mutual inductance in the coupled corner building block Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line inductance in the coupled corner building block. 127

156 5 4 3 Normalized Sensitivity S11 (R) S11 (I) S21 (R) S21 (I) E E E+10 Frequency (Hz) Figure S 21 and S 11 sensitivity of test structure 3 with respect to line resistance in the coupled corner building block Model Extraction Circuit model parameter extraction proceeded in several steps. Due to the highly nonlinear nature of the problem, a procedure of hierarchical optimization with respect to MoM generated S-parameter data was chosen. Initial guesses for the various parameters were derived from actual measurement data. All optimizations and simulations were done using the Hspice circuit simulator on Sun SPARCstation 20 series workstations. Details of the extraction method can be found in Chapter 3. Test structure 1 was initially optimized in order to extract the parameters of the uncoupled material square. The initial guesses were inserted, and the circuit was optimized with respect to measurements up to 10 GHz. Once the optimization was 128

157 complete, the computed models were taken and used as valid model parameters for their respective building blocks for test structure 2. The parameters to be computed for this structure were the first order line to line coupling parameters (mutual inductance and coupling capacitance), and the parameters for the U-shaped corner. Additionally, line to ground capacitance was recomputed for the material square building block in the presence of adjacent lines which provided a shielding effect. The third test structure was optimized in order to extract the model for the coupled corner building block. All optimizations completed with low residual sum of squares error, indicating accurate results. The modeling results for test structures 1, 2 and 3 are shown in Figure 6.5-2, Figure 6.5-3, and Figure respectively. The extracted circuit models and parameters are shown in Figure

158 1 2 Uncoupled Line Bldg. Block 1 CC CC R L L R 2 C R=0.06 Ohm L= 7.1E-11 H C = 3.1e-14 F CC=3.5E-14 F Coupled Line Bldg. Block 2 CC 1 L M CC R L L R C C M CC R L L R C 4 CC L M 3 R=0.06 Ohm L= 5.7E-11 H C = 2.1e-14 F CC=3.5E-14 F CM=5.0e-15 F LM = U-Shaped Bend Bldg. Block 2C 4 Coupled Corner Bldg. Block 1C 1 2 U 3 CC CC 1 2 R L L R C Eq. circuit on each side of diagonal cut line 1 U 2 CC L M CC R L L R C C M CC R L L R C CC L M 2 C 1 CC CC R L L R 2 C 1 C R=0.45 Ohm L= 2.9E-11 H C = 1.8E-13 F CC=5.5E-14 R=0.37 Ohm L= 2.0E-10 H C = 2.0E-14 F CM=4.0E-15 F CC=1.0E-14 LM = 0.20 R=0.1 Ohm L= 1.1E-10 H C = 3.7E-14 F CC=1.0E-15 F Figure Building blocks, equivalent circuits, and parameters for spiral inductor modeling. 130

159 3.50E E E E E E E E E-02 MoM S11(R) -1.00E-01 Modeled S11(R) -1.50E-01 MoM S11(I) Modeled S11(I) -2.00E E E E+10 Frequency (Hz) 1.00E E E E E E E E E-01 MoM S21(R) Modeled S21(R) -8.00E-01 MoM S21(I) Modeled S21(I) -1.00E E E E+10 Frequency (Hz) Figure S-parameter measured and modeled results for test structure

160 5.00E E E E E E E E E E-01 MoM S11(R) Modeled S11(R) MoM S11(I) Modeled S11(I) -5.00E E E E+10 Frequency (Hz) 1.00E E E E E E E E-01 MoM S21(R) -6.00E-01 Modeled S21(R) -8.00E-01 MoM S21(I) Modeled S21(I) -1.00E E E E+10 Frequency (Hz) Figure S-parameter measured and modeled results for test structure

161 1.00E E E E E E E E E E-01 MoM S11(R) Modeled S11(R) MoM S11(I) Modeled S11(I) -1.00E E E E+10 Frequency (Hz) 1.00E E E E E E E E E E-01 MoM S21(R) Modeled S21(R) MoM S21(I) Modeled S21(I) -1.00E E E E+10 Frequency (Hz) Figure S-parameter measured and modeled results for test structure

162 6.6. Results The extracted building blocks were used to predict the electrical behavior of a four turn rectangular spiral inductor (Figure 6.6-1). The inductor was designed with the longest outside segment length being 230 mils, yielding an overall size of over 2000 mils, which is over one wavelengths long at 2 GHz. As before, all the building block models were extracted from the test structures only.. In addition, the operation of the inductor in actual circuits was tested. Since no structures were physically fabricated, all comparisons were made to the method-of-moments simulator results. Additionally, the circuits were not actually constructed, but were simulated within the Microwave Design System environment using the S-parameter data as a model. 134

163 170 mil 230 mil Figure turn spiral inductor predictively modeled. It is of interest to note that none of the test structures were designed to be inductors, and that none of them had current in parallel branches flowing in the same direction as is usually found in inductive components. The equivalent circuit for the spiral inductor was constructed by replacing the different geometrical sections with the applicable building block circuit models. Each parallel square slice of material in parallel line segments was modeled with coupled building blocks, which were cascaded in order to generate the required line length. The corners were modeled using the couple corner building blocks. The various building blocks and their locations within the inductor are shown above in Figure Since most of the building blocks occurred in a regular and repetitive manner, many subcircuit calls could be used to simplify the overall 135

164 circuit construction. The finished circuit consisted of the 4 turn inductor consisted of over 2000 elements and 600 nodes. For the spiral inductor modeling case, an impedance parameter analysis was done, to investigate input impedance and phase characteristics of the inductor. Z-parameter data was obtained from measured S-parameter data using the MDS software and the circuit configuration shown in Figure (top), a similar circuit was used to generate the Z- parameter data from the developed model Figure (bottom). The predicted and actual (MoM generated) Z-parameter results are shown in Figure and Figure As can be seen, the building block based prediction agrees very well with actual measurements, in both the Z 11 (db) and phase responses, up to the first self-resonance, and actually quite well beyond that also. At these higher frequencies beyond the first self-resonance, general behavior patterns are predicted quite well, although offset slightly in frequency. For most practical applications, the only useful range of any passive component will be well below the first self-resonance, since beyond that point the component exhibits characteristics of its reactive counterpart due to a phase inversion. 136

165 1 Port 1 Inductor S-Parm. Dataset 2 Port 2 Port 1 Port 2 Figure Z-parameter circuit configurations for inductor analysis (top) MDS configuration (bottom) circuit predictive model configuration. 137

166 70 60 Z11(dB) Z11(db) - Modeled Z11(db) - MDS E E E+10 Frequency (Hz) Figure Measured and predicted results for Z11(dB) of four turn spiral inductor Z11(phase) E E E+10 Frequency (Hz) Z11(phase) - Modeled Z11(phase) - MDS Figure Measured and predicted results for Z11(phase) of four turn spiral inductor. 138

167 To test the validity of the developed inductor circuit model, the model was used in several different tank circuit configurations. All of the following circuit comparisons have been made with respect to circuits simulated within the MDS simulator using S- parameter data directly as a model for the inductor. In the first circuit, a 1 pf capacitor was placed in parallel with the inductor, with a 50 Ω terminating resistor and an AC small signal excitation (Figure 6.6-5). The voltage magnitude and phase data was then compared to results obtained from circuit simulations of the building block based equivalent circuit. The results are shown in Figure and Figure As can be seen, we have extremely good agreement in both magnitude and phase responses up to approximately 10 GHz. The point of resonance is predicted well, as can be more clearly seen in the phase plot since the lossy metal used (0.1 Ω/square) does not show a well pronounced notch in the voltage response. C=1pF Vout 50 Ohm 4-turn inductor Figure LC resonant tank circuit. 139

168 5.00E E+00 Voltage Magnitude (db) -5.00E E E E E+01 Modeled Vout(dB) MDS Vout(dB) -3.00E E E E+10 Frequency (Hz) Figure Actual (MDS) and predicted LC circuit output voltage magnitude Voltage Phase (degrees) Modeled Vout(phase) MDS Vout(phase) E E E+10 Frequency (Hz) Figure Actual (MDS) and predicted LC circuit output voltage phase. 140

169 A second, more ambitious LC resonant circuit was also constructed, but this time with two of the inductors in parallel with each other. All manufactured circuit results were generated by MDS as before, and all predictions using the circuit model were obtained from a circuit simulator. The constructed circuit is shown in Figure Actual and predicted circuit responses are shown in Figure and Figure As can be seen from the plots, both output voltage magnitude and phase, as well as the selfresonance frequency, are predicted well. Additionally, behavior beyond the first resonance is also tracked, except for some deviations in magnitude and offsets in frequency. As mentioned earlier, components are almost never used in circuits beyond their self-resonant frequency, and thus accurate predictions up to that point are essential, but beyond that have limited use. C=5pF Vout 50 Ohm 2 4-turn inductors Figure LC circuit with 2 4-turn inductors in parallel. 141

170 5.00E E+00 Voltage Magnitude (db) -5.00E E E E E+01 Modeled Vout(dB) MDS Vout(dB) -3.00E E E E+10 Frequency (Hz) Figure Actual (MDS) and predicted LC circuit output voltage magnitude. 1.50E E+02 Voltage Phase (degrees) 5.00E E E E E+02 Modeled Vout(phase) MDS Vout(phase) -2.00E E E E+10 Frequency (Hz) Figure Actual (MDS) and predicted LC circuit output voltage phase. 142

171 6.7. Conclusion In this chapter, the modeling method presented in this thesis has been applied to the modeling of spiral inductors and to several LC resonant circuits. A 4 turn spiral inductor has been modeled accurately using building blocks derived from test structures which are of entirely different geometries than the inductor itself, except for the presence of the common building blocks. Accurate results for the electrically long inductor have been obtained up to the first resonance, but with good behavior beyond that also. The inductor model was tested in two different LC resonant circuits, with good predictions of the resonant frequency in both cases. Complete circuit models for the inductors were developed which simulated within a circuit simulator within 1 minute. 143

172 CHAPTER VII MODELING OF FULLY 3-DIMENSIONAL PASSIVE DEVICE 7.1. Introduction The latest advances in integrated passive manufacturing include the ability to fabricate multilayer passive structures. Technologies such as low temperature cofired ceramic (LTCC) are becoming mainstream, and offer potentially huge savings in overall printed circuit board area. LTCC processes have the advantage of supporting a large number of layers of ceramic tape (well over 30), each capable of accepting a conductor layer. In addition, stacked via technology has been developed, allowing for connectivity between layers. As can be envisioned, a large number of passive components could possibly be moved away from the printed circuit board and integrated into a LTCC substrate within a package, thereby yielding very compact circuit boards. LTCC technology clearly shows considerable potential as an enabling technology for the next generation of highly compact systems. Successful design of LTCC structures requires that accurate models of the various LTCC components exist or can be easily obtained. For high frequency designs, most LTCC structures are electrically long, and due to their full 3-dimensional geometries, 144

173 have very complex field patterns. Standard modeling methods for microstrip or stripline based structures do not apply for these components, and usually the full wave 2 ½-D or 3-D solution methodologies must be used, such as the method of moments, spectral domain, finite element and finite difference time domain methods. These methods, especially the finite element and finite difference time domain method, are very accurate although very computationally expensive, and for complex 3-D structures, analysis can take many hours, and even days utilizing state-of-the-art computers and software. Due to this drawback, this type of analysis is not well suited for the iterative nature of passive component design, and is probably one of the principle factors which has contributed to the slow progress of heavily integrated LTCC substrates. In this chapter, the modeling methodology developed under this research will be applied to structures manufactured in a LTCC process. Accurate results will be shown for the predictive modeling of full 3-D solenoid style multilayer spiral inductors with interactions. In addition, modeling results will be shown for gridded plate capacitors. In all cases, results have been accurate up to the first self-resonance, beyond which the structures have limited use. A 2 ½-D or 3-D simulation of the LTCC structures was not done, primarily due to a lack of detailed information about the process and the difficulty involved in setting up an accurate run. In order to correctly define the input structure in order to obtain as much accuracy as possible, detailed information regarding the process characteristics must be taken into account. This includes setting up a multi-dielectric system, with varying dielectric thicknesses based upon the presence of metal on a layer or not. This is a result 145

174 of the characteristic humping which occurs in regions where metal is printed coincidentally on several different layers. Additionally, complex via geometries must be taken into account, including catch pads and bulging effects between layers of tape. It should be stressed that simply obtaining all the correct geometries and dielectric thicknesses would require a considerable amount of test structure design, fabrication, cross-sectioning, and measurement, and would probably require a significant amount of time to complete. Also, entering all the required geometries into a field solver would be a painstaking and difficult task. Once everything is entered, and because of the resulting non-planar input definition, it is very probable that a very large number of mesh points will be required to solve the system accurately, which in turn could take a long time to solve. Using the building block based modeling method, circuits have been developed for these structures that are comprised of relatively few components and simulate in a circuit solver in approximately one minute. The results presented in this chapter show the true potential of the developed modeling method. Properly utilized, the building block based modeling method can be an enabling technology for component design in multilayer passive component fabrication processes. 146

175 7.2. Modeling Procedure The modeling procedure involved in this case was somewhat different than for the planar devices discussed in earlier chapters. A brief outline of the steps involved is described below. 1. The first step involved a determination of what geometry structures were to be considered and allowed in order to set up a practical set of building blocks and test structures to be measured and characterized. For the 3-D inductors, this meant that the widths and separations of the top and bottom conductors that comprised the solenoid as well as the spacings in between parallel solenoids had to be fixed. For the gridded capacitor, this implied that the geometry of each grid square was fixed. 2. The custom current visualization software was not designed to analyze 3-D structures, and hence was not used for differential current flow analysis. Instead, building block sizes were determined based on symmetry and repetition within the structure. As an example, for the solenoid inductor, one building block was defined to be one turn. 3. Test structures for modeling the building blocks were designed, along with target structures against which the models were verified. Additionally, a small signal frequency dependent sensitivity analysis was performed on the test structure equivalent circuits to ensure that the building block circuit parameters could be successfully deembedded. 4. The structures are physically designed (12-layer LTCC process) and fabricated. LTCC process access was granted by National Semiconductor Corp. High frequency 147

176 S-parameter measurements of the devices are taken by on-wafer ground-signalground probing. 5. The measured data is used to create circuit optimization input files for the test structure equivalent circuits. Initial guesses are made based on the measured results for each structure. Once optimization for one structure is complete, the results are used for the remaining optimizations. 6. Circuit models of the building blocks are obtained Detailed LTCC Structure Modeling Procedure The first step involved in the LTCC modeling procedure was a determination of what types of structures and geometries were to be modeled. As mentioned above, two structures were considered for this process solenoid spiral inductors and gridded plate capacitors. Solenoid inductors were chosen since inductive components are very useful in high frequency RF designs, and most designs currently employ only planar inductors. However, solenoid inductors may be preferable over planar inductors due to more confined field patterns, and possibly smaller area. The 3-D nature of solenoid inductors requires that modeling be achieved using full wave 3-D solvers, which can result in impractically long run times for design purposes. While full 3-D analysis is extremely useful for obtaining detailed information about the structure under analysis, including field patterns, current density plots, etc., it is not well suited for a design process which is 148

177 usually iterative in nature. The building block-based modeling method could potentially produce vast improvements in modeling and simulation time for these devices. Gridded plate capacitors were also chosen to be modeled in the LTCC process. Large area metal deposition is difficult to achieve in LTCC technology, and as a result a maximum metal area design rule restriction is usually enforced. LTCC technology is very well suited for fabrication of large valued two-layer metal-insulator-metal (MIM) capacitors for use in applications such as power supply decoupling and filtering. In order to make large capacitors which adhere to the maximum metal area requirements requires that they be manufactured with gridded instead of solid conductor plates. Solid plate capacitors could be used, but then their sizes would be restricted. Modeling of gridded plate capacitors are very important to ensure that they function as intended at high frequencies. The modeling method developed under this work would prove very useful and efficient in the modeling of these gridded structures, as compared to other nonlumped element techniques. The solenoid inductors were designed to have an upper and a lower conductor on different layers, with connections between them made by stacked vias. Both conductors were separated by 6 layers of ceramic tape (to reduced capacitive coupling between the conductors), and were connected by stacked vias (6 layers deep with catch pads on each layer) such that a solenoidal pattern of current flow through the structure was obtained. A diagram showing the general inductor geometry is shown in Figure The metal conductors were designed to be 10 mils wide, with a spacing between adjacent coils of 30 mils. The bottom conductor was laid out at angle to facilitate connections between the via 149

178 stacks connecting the layers. Interactions between inductors were also modeled, and a spacing of 10 mils between parallel solenoids was specified, with via stacks from one solenoid being directly opposite via stacks of the parallel solenoid. Top Conductor Input Via Stack Output Bottom Conductor Figure Solenoid inductor geometry. The gridded plate capacitors were also specified with a metal width of 10 mils, with a hole of 40 x 40 mils between the metal lines. The structure was two-layer, with a separation distance of only one layer of ceramic tape in order to maximize capacitance. It was specified that the upper and lower conductors were completely coincident, so that the metal lines of the top conductor completely overlapped the metal lines on the lower conductor. A representative structure is shown in Figure Ground planes for all devices were specified to be on the lowest layer of the LTCC structure. All connections to the devices were made using a ground-signal-ground probe pad pattern on the top later, 150

179 with connections made to the devices using stacked vias and interconnect. All interconnect to and between structures was drawn on a single layer. Figure Gridded plate capacitor geometry Solenoid Inductor and Gridded Plate Capacitor Building Blocks Current visualization of the solenoid inductors was not possible, since the custom software was unable to handle full 3-D structures. Instead, in this case, a symmetry based approach was taken. It was unlikely that the current flow at any point in the structure was constant, since the current was constantly changing direction, however, the current flow pattern would be the same from coil to coil. Because of this, each coil with its associated vias was taken to be a single building block for modeling the solenoid coil. Each segment 151

180 of the coil (the top and bottom conductors and the vias) were modeled with different circuit models. Parallel coil building blocks were also modeled as two parallel, single coils, connected with coupling capacitances and mutual inductances. For a fixed coil geometry, these were the only building blocks defined for solenoid inductor modeling a rather aggressive but not unpractical set. In addition, the probe pad and interconnect squares were also defined as building blocks. The various building block geometries are shown in Figure Gridded plate capacitor modeling only required three building blocks. Two of them; the probe pad and the interconnect material square building blocks were already included in the solenoid inductor building block set. The only additional block that was required was the gridded capacitor square block, consisting of surrounding metal lines and one grid hole. The resulting building block is shown in Figure

181 Top Metal Via Coil 1 on this axis Bottom Metal Coil 2 on this axis Coil Building Block - includes top conductor, 2 vias and bottom conductor Coupled Coils Building Block for modeling interactions between parallel solenoids Top metal layer GSG probe pad Uncoupled Interconnect Square Building Block Via to interconnect layer Interconnect Layer Vias to ground Ground Direction of current flow through building block GSG Probe Pad Building Block Figure Solenoid inductor building blocks. 153

182 Gridded Plate Capacitor Building Block Figure Gridded plate capacitor building block Solenoid Inductor and Gridded Plate Capacitor Test Structures There were a total of five building blocks defined for the modeling of solenoid inductors and gridded plate capacitors. The building blocks for the inductor were a single coil; 2 coupled coils; the probe pad and the interconnect square. The capacitor building blocks included the gridded capacitor square building block, as well as the probe pad and interconnect square blocks which were also used for the inductor. The fact that two of the building blocks were shared allowed for designing and manufacturing only one set of test structures for both the inductor and capacitor. This building block definition lead to the design of 4 test structures. The first test structure was simply a line consisting of interconnect material, with the probe pads on its ends. Modeling of this test structure would allow for 154

183 characterization of the probe pad building block and the interconnect square building block. The models generated by this block could be shared between both the inductor and capacitor. The 2nd test structure was a single inductor coil with probe pads. This structure allowed for the modeling of the uncoupled inductor coil building block. The next test structure was a serially connected 3-segment parallel coil inductor. This structure helped characterize coupling between parallel coils. The last test structure was a simple gridded plate capacitor, which would allow for the characterization of the gridded capacitor square building block. It is noteworthy that this last test structure was the only additional structure required to model these complex gridded plate capacitors. The various test structures are shown in Figure and Figure

184 Interconnect Line Bldg. Block Test Structure 1 Probe Pad Bldg. Block Test Structure 2 Inductor Coil Bldg. Block Test Structure 3 Coupled Inductor Coils Bldg. Block Figure Test structures for solenoid inductor modeling. 156

185 Test Structure 4 Gridded Capacitor Plate Bldg. Block Figure Additional test structure for gridded plate capacitor modeling Structure Fabrication and Measurement The test structure coupon was physically design within the Cadence Virtuoso design environment. A custom technology file for a 12-layer process was developed, and a process design rule compliant test structure coupon was produced. The design was fabricated at the National Semiconductor Corp. LTCC fabrication facility through the RF/Wireless design group. The size of the completed coupon was approximately 2.25 x Each layer of ceramic tape was specified to be 3.6 mils thick with a dielectric 157

186 constant of 7.8. The metal lines were drawn to be 10 mils wide, and the vias were a diameter of 5.6 mils. The designed mask of the LTCC coupon is shown in Figure with a photograph of the top side of the fabricated coupon in Figure and the bottom side showing the last embedded layer in Figure Manufactured characteristics of lines and vias are also shown in Figure 7.5-4, Figure 7.5-5, and Figure It is clear from these photographs that lines and vias are not very uniform in this process. The test structures were measured using network analysis techniques. Since very low loss metal was used in the manufacturing process, DC resistance measurements were unreliable and were not used. For the high frequency measurements, a HP 8510C network analyzer was used in conjunction with a Cascade Microtech probe station and ground-signal-ground configuration probes. Calibration was accomplished using a supplied substrate and utilization of the line-reflect-match (LRM) calibration method. Data was gathered for each of the test structures at over 200 frequency points between 45MHz and 5GHz and stored with the aid of computer data acquisition software and equipment. Data points beyond 5 GHz were not taken since most of the devices were already in resonance before that point. 158

187 Figure Physical layout of LTCC coupon 159

188 Figure Photograph of top side of fabricated LTCC coupon. 160

189 Figure Photograph of bottom side of LTCC coupon with last embedded layer partially visible. 161

190 Figure Photograph of cross section of metal line in a LTCC structure along the line length (photograph courtesy of National Semiconductor Corp.) 162

191 Figure Photograph of cross section of metal line across line width (short) (photograph courtesy of National Semiconductor Corp.) 163

192 Figure Photograph of cross section of 2 via stack (photograph courtesy of National Semiconductor Corp.) 7.6. Modeling and Parameter Extraction As in previous cases, the fundamental circuit model used for modeling segments of building blocks was the partial element equivalent circuit (PEEC) with modifications made as necessary. However, in this case shunt capacitances were excluded from the model, since they apparently had very little effect on any of the output responses of the 164

193 previously discussed passive devices, as can be seen in their small-valued sensitivity responses to these parameters. The physical structure of the probe pad was quite complicated (Figure 7.3-1), but the section which was populated with parallel long stacked vias belonged to the ground plane, and hence it was anticipated that it did not contribute significantly to the overall S- parameter responses. A simple PEEC circuit was used in this case, and as can be seen later, was able to model the pad behavior adequately. The interconnect material square also was modeled with a simple PEEC circuit, and this too gave good results. The inductor coil was modeled with two separate PEEC circuit models; one each for the upper and lower conductors of the inductor, and two LC circuits; one each for the via stacks connecting the two conductors. Due to the geometry of the inductor coils, it was assumed that the majority of coupling would occur between adjacent via posts, and in order to model this, mutual inductances and coupling capacitances were added between the via stacks. This coupling mechanism was modeled accurately, and correctly helped model the behavior of parallel inductor coils as will be shown later. The gridded capacitor plate building block was modeled with four sets of coupled PEEC circuits which represented the metal conductors surrounding the cavity in the capacitor building block Sensitivity Analysis In order to determine whether individual building block circuit components could be deembedded from the designed test structures, a sensitivity analysis was performed. 165

194 The sensitivity analysis was performed on the test structure equivalent circuits with respect to each building block circuit parameter that was desired to extracted. The results of the sensitivity analysis showed exactly how the S-parameters varied when one circuit parameter was differentially modified. Normalized plots of the various sensitivities are shown. In general, a non-zero non-flat response shows that the output is affected by the parameter over frequency, and thus should be extractable. Test structure 1 sensitivity responses are shown in Figure Figure In this set of plots the sensitivities with respect to line resistances were close to zero and are not shown, but apart for that, all the capacitive and inductive parameters show that they affect the output response substantially, particularly at higher frequencies. Test structure 2 responses, shown in Figure Figure , show similar results for the reactive components. It is interesting to note, however, that conductance to ground of the top conductor does influence the output response considerably. Line resistances have a measurable effect for these structures also. Test structure 3 data is shown in Figure and Figure , and large sensitivity responses are obtained for both the coupling capacitance and mutual inductance. Finally, test structure 4 sensitivity plots are shown in Figure Figure As might be expected, the largest sensitivity response occurs for capacitance between the conductors, but the plots also show considerable sensitivity responses for the capacitances to ground of both upper and lower conductors, as well as to inductances, particularly at higher frequencies when the device starts to conduct. 166

195 0.5 0 Normalized Sensitivity S11(R) -2.5 S11(I) S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 1 with respect to capacitance to ground in the interconnect line building block Normalized Sensitivity S11(R) S11(I) -3 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 1 with respect to line inductance in the interconnect line building block. 167

196 Normalized Sensitivity S11(R) -3 S11(I) S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 1 with respect to capacitance-to-ground in the probe pad building block Normalized Sensitivity S11(R) -2 S11(I) S21(R) -2.5 S21(I) 1.00E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 1 with respect to line inductance in the probe pad building block. 168

197 5 4 3 Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to capacitance-to-ground of the top conductor in the inductor coil building block Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line inductance of the top conductor in the inductor coil building block. 169

198 Normalized Sensitivity S11(R) -0.2 S11(I) S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line resistance of the top conductor in the inductor coil building block Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line conductance of the top conductor in the inductor coil building block. 170

199 5 4 3 Normalized Sensitivity S11(R) S11(I) -4 S21(R) -5 S21(I) 1.00E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to lineto-ground capacitance of the bottom conductor in the inductor coil building block Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line inductance of the bottom conductor in the inductor coil building block. 171

200 Normalized Sensitivity S11(R) -0.2 S11(I) S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line resistance of the bottom conductor in the inductor coil building block Normalized Sensitivity S11(R) S11(I) S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to line conductance to ground of the bottom conductor in the inductor coil building block. 172

201 5 4 3 Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to via capacitance in the inductor coil building block Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 2 with respect to via inductance in the inductor coil building block. 173

202 5 4 3 Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 3 with respect to coupling capacitance in the interacting inductor coil building block Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 3 with respect to line-to-line mutual inductance in the interacting inductor coil building block. 174

203 5 4 3 Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to capacitance-to-ground of the top plate in the gridded capacitor building block Normalized Sensitivity S11(R) S11(I) S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to capacitance-to-ground of the bottom plate in the gridded capacitor building block. 175

204 5 4 3 Normalized Sensitivity S11(R) S11(I) S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to mutual capacitance between the plates in the gridded capacitor building block Normalized Sensitivity S11(R) -3 S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to mutual inductance between the plates in the gridded capacitor building block. 176

205 5 4 3 Normalized Sensitivity S11(R) S11(I) -4 S21(R) S21(I) E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to line inductance for both plates in the gridded capacitor building block Normalized Sensitivity S11(R) S11(I) -0.8 S21(R) -1 S21(I) 1.00E E E+10 Frequency (Hz) Figure S 11 and S 21 sensitivity responses of test structure 4 with respect to line resistance for both plates in the gridded capacitor building block. 177

206 Model Extraction The building block equivalent circuits were extracted from the test structure circuits by a process of nonlinear optimization with respect to measured S-parameters. Initial guesses for the blocks were computed directly form the measured data as described in detail in Chapter 3. All optimizations were accomplished utilizing the Star-Hspice circuit simulator on Sun SPARCstation computers. The test structures referred to in this section are shown in Figure and Figure The first test structure optimized was structure 1. This test structure allowed for characterization of the probe pad and the interconnect square building blocks. Optimization was performed over the range of measured data; 45 MHz to 5 GHz. Data beyond 5 GHz was not used due to the fact that all the structures were well beyond their self-resonant frequencies by that point. The next structures optimized were test structures 2 and 3, which allowed the behavior characterization of the single inductor coil, and also the coupled inductor coils building blocks. The models for the pad and interconnect generated by test structure 1 were used here also. The last test structure optimized was test structure 4, and from this device the behavior of the gridded plate capacitor square building block was deembedded. All test structures optimized accurately, and the results of the optimizations are shown in Figure Figure Impedance parameter plots are shown for the inductor and capacitor test structures (structures 2-4), since their behavior can be more easily understood in terms of input impedance and phase. The measured S-parameter data was converted to Z-parameter data using the Microwave Design System (MDS) software, and the circuit setup shown in Figure

207 1 Port 1 Inductor S-Parm. Dataset 2 Port 2 Figure Z-parameter MDS circuit configuration for inductor and capacitor analysis. 179

208 R = 1E-3 R L L R L = 1.8E-10 C C = 3.1E-13 Ground Probe Pad Building Block R = 1E-3 R L L R L = 8.3E-11 C C = 2.8E-14 Interconnect Square Building Block 1 2 Top Metal Via 1 Ri Li Li Ri Ci Rg1 Lvia Cvia Ri2 Li2 Li2 Ri2 Ci2 Rg2 Lvia Cvia 2 Top Conductor Via Stack Bottom Conductor Via Stack Bottom Metal Ri = 1E-2 Li = 7.4E-11 Ci = 1.0E=13 Lvia = 4.9E-10 Cvia = 8.6E-13 Ri2 = 1.7E-2 Li2 = 4.4E-10 Ci2 = 1.8E-13 Inductor Coil Building Block Lvia Lvia 1 1 Ri 2 Li Li Ri Ci Rg1 Cvia Ri2 Li2 Li2 Ri2 Ci2 Rg2 Cvia Coil 1 on this axis Top Conductor Lm Cm Lvia Bottom Conductor Via Stack Lvia Coil 2 on this axis 3 Ri Li Li Ri Ci Rg1 Cvia Ri2 Li2 Li2 Ri2 Ci2 Rg2 Cvia 4 Top Conductor Coupled Via Stack Bottom Conductor Via Stack Coupled Inductor Coil Building Block Lm = 0.4 Cm = 1.4E=13 All other parameters from inductor coil building block. Additional via couplings inserted as needed. 1a 2a 4a 3a 1a 1(a,b) 2(a,b) 1b 2b 4b 3b 1b Coupled PEEC Circuits 3(a,b) 4(a,b) Gridded Capacitor Plate Building Block A B D C B A L M R L L R CM C1 L M R L L R C2 C D R = 0.47E-1 L = 9.1E-10 C1 = 1.3E-14 C2 = 1.0E-14 CM = 0.89E-13 LM=0.9 Figure Building blocks, equivalent circuits and parameter values for solenoid inductor and gridded plate capacitor modeling. 180

209 1.00E E E E E-01 S E E E E-01 S21(R) Meas. S21(R) Modeled -8.00E-01 S21(I) Meas. S21(I) Modeled -1.00E E E E+10 Frequency (Hz) 4.00E E-01 S11(R) Meas. S11(R) Modeled S11(I) Meas. S11(I) Modeled 2.00E-01 S E E E E E E+10 Frequency (Hz) Figure Measured vs. modeled results for test structure 1. (a) S 21 real and imaginary response. (b) S 11 real and imaginary response. 181

210 80 70 Z11(dB) - MDS Z11(dB) - Modeled Z11(dB) E E E+10 Frequency (Hz) Z11(Phase) Z11(Phase) - MDS Z11(Phase) - Modeled E E E+10 Frequency (Hz) Figure Measured vs. modeled results for test structure 2. (a) Z 11 magnitude response. (b) Z 11 phase response. 182

211 Z11(dB) Z11(dB) - MDS Z11(dB) - Modeled 1.00E E E+10 Frequency (Hz) Z11(Phase) Z11(Phase) - MDS Z11(Phase) - Modeled 1.00E E E+10 Frequency (Hz) Figure Measured vs. modeled results for test structure 3. (a) Z 11 magnitude response. (b) Z 11 phase response. 183

212 60 50 Z11(dB) - MDS Z11(dB) - Modeled 40 Z11(dB) E E E+10 Frequency (Hz) Z11(Phase) - MDS Z11(Phase) - Modeled Z11(Phase) E E E+10 Frequency (Hz) Figure Measured vs. modeled results for test structure 4. (a) Z 11 magnitude response. (b) Z 11 phase response. 184

213 7.7. Results Once the building block equivalent circuits had been deembedded, they were used to predict the behavior of several different inductors with interactions between them (Figure 7.7-1), and also the behavior of a large gridded plate capacitor. All of these structures would be very difficult and time-consuming to model with a fully 3-D nonlumped element simulation and modeling method due to their complex geometries and 3- dimensional nature. The structure equivalent circuits were generated by replacing each geometrical building block with its associated circuit. Small signal simulation times usually was within 1 minute using Sun SPARCstation computers. Figure Fabricated solenoid inductors. 185

214 Figure shows 5 different inductors that were fabricated. The top right and lower right inductors represent test structures 2 and 3 respectively. The modeling method was tested on the two inductors on the left hand side; the four coil inductor with six turns per coil, and the four coil inductor with 8 turns per coil. These structures were electrically long, with both being greater than 1 wavelength long at 1 GHz. The predicted electrical behavior of the input impedance, in magnitude and phase, for the 4 coil, 6 turn per coil inductor are shown in Figure and Figure As can be seen in the plots, the modeling method shows very good agreement with the actual values in both magnitude and phase responses, up to the first self-resonant frequency. Z 11 magnitude and phase results are also shown for the 4 coil, 8 turn per coil series connected inductor in Figure and Figure Again, for this test case we have good agreement in both response, with the self resonant frequency being predicted quite well. As has been mentioned, most passive devices are usually only useful well before they become self-resonant, since after that point they reverse their phase characteristics and start to behave like their reactive counterparts. 186

215 Z11(dB) E+08 Z11(dB) - Actual Z11(dB) - Predicted Frequency (Hz) 1.00E+09 Figure Measured and predicted results for Z 11 (db) for 4-coil, 6 turn per coil inductor Z11(Phase) E+08 Z11(Phase) - Actual Z11(Phase) - Predicted Frequency (Hz) 1.00E+09 Figure Measured and predicted results for Z 11 (phase) for 4-coil, 6 turn per coil inductor. 187

216 Z11(dB) E+08 Z11(dB) - Actual Z11(dB) - Predicted Frequency (Hz) 1.00E+09 Figure Measured and predicted results for Z 11 (db) for 4-coil, 8 turn per coil inductor Z11(Phase) E+08 Z11(Phase) - Actual Z11(Phase) - Predicted Frequency (Hz) 1.00E+09 Figure Measured and predicted results for Z 11 (phase) for 4-coil, 8 turn per coil inductor. 188

217 In addition to testing building block model validity on the solenoid inductors, the gridded plate capacitor models were also tested on a large gridded parallel plate capacitor. An illustration of the capacitor is shown in Figure Each plate of the capacitor had outside dimensions of 400 x 250 mil, and was thus quite large electrically. Only two building blocks were required for modeling this device; the probe pad and the gridded capacitor plate building block. The electrical prediction results for the Z 11 parameter are shown in Figure and Figure As with the inductor cases discussed above, both magnitude and phase responses agree well with actual measurements, with the self- resonant frequency being predicted accurately. Figure Large gridded plate capacitor used to test capacitor building block model validity. 189

218 70 60 Z11(dB) - Actual Z11(dB) - Predicted 50 Z11(dB) E E E+10 Frequency (Hz) Figure Measured and predicted results for Z 11 (db) for large capacitor Z11(Phase) - Actual Z11(Phase) - Predicted 40 Z11(Phase) E E E+10 Frequency (Hz) Figure Measured and predicted results for Z 11 (phase) for large capacitor. 190

219 7.8. Summary In this chapter, the test structure and building block predictive modeling method developed under this research work was applied to the modeling of complex full 3-D passive structures, and accurate results were obtained and experimentally verified. For all benchmark structures, accurate predictions of electrical behavior in both magnitude and phase, up to their respective self-resonant frequencies were obtained. Since complete circuit element models for the structures were constructed, small signal analysis occurred at very high speed in a standard circuit simulator. For the structures discussed in this paper, simulations completed in under 1 minute for all cases. This particular application demonstrates the potential of the building block and test structure modeling method. Models of full 3-D structures manufactured in an inhomogeneous environment with varying conductor and dielectric thicknesses, as is usually the case for a LTCC process, are usually obtained from very complex full 3-D simulation methods or less accurate 2 ½-D solvers. These simulations can take an impractically long time to complete, and are not well suited for circuit design applications, which are usually iterative in nature. The modeling method developed under this research could prove to be of significant use in simulation and modeling in integrated passive component technologies such as LTCC. 191

220 CHAPTER VIII CONCLUSIONS AND RECOMMENDATIONS 8.1. Summary of Research and General Conclusions A novel methodology for the modeling of 2 and 3 dimensional integrated passive devices with interactions has been presented in this dissertation. The method is based upon defining geometrical building blocks, and modeling them by the use of test structures, measurement, and nonlinear optimization. The method yields equivalent circuit (although table lookup models can also be used) building blocks that can be used to model any structure designed using a combination of those blocks. Since measurements of test structures are performed, manufacturing process effects are taken into account in the models. The method is general, since any type of structure can be modeled using the same technique, whether it be a resistor, capacitor, or inductor. It is also versatile, in that the number of structures that can be accurately designed and modeled with a given building block set is very large. Additionally, the method is expandable, since new building blocks can be defined, characterized and added to the modeled library on an as-needed basis. The building blocks are modeled by equivalent circuits, although direct multiport 192

221 parameters can be used, and as a result, large circuits of passive structures are developed. Small signal simulations of these circuits usually occur within a few minutes, which is considerably faster than most general numerical full wave methods. Implementation and ease of use are often overlooked issues in modeling research. This method is easily implementable in a modern circuit design CAD framework, since characterized building blocks can easily be inserted in a library, and block geometries, circuit models, and design rules can all be associated together. The use of this method then does not require any special software beyond what is found in most circuit design houses, and only requires minimal training to use correctly. The method has been tested and experimentally verified on a number of different structures, including serpentine resistors, interdigital capacitors, planar spiral inductors, and full 3-D solenoid inductors and gridded parallel plate capacitors. The only structure not experimentally verified was the planar spiral inductor, due to difficulty in gaining access to multilayer fabrication facilities at that time. Benchmark structures comprised of modeled building blocks were designed to test the validity of the modeling method. In all cases, good predictions of electrical behavior were obtained. Several circuits were also built with the help of Hewlett-Packard Microwave Design System (MDS) to test model validity in actual circuits. Good results were obtained here also. One circuit design that was used quite often was the RLC resonant tank circuit. This circuit was very useful for determining model accuracy, since the position of the resonance was determined by component capacitance and inductance, and the actual shape of the resonance was determined by component resistance. In general, good matches were obtained using the 193

222 developed circuit model when compared to using the measured data directly as a model of the device. While the results for the planar structures are accurate, the true potential of the modeling method can be seen in the modeling results for the completely 3-dimensional structures designed and fabricated in the low temperature cofired ceramic (LTCC) process. Modeling of fully 3-D structures can usually only be accomplished by the use of numerical full wave methods, such as the finite element method which is actually used quite often for LTCC modeling work. As discussed in Chapter 2, numerical methods usually require a structure to be meshed into small segments based upon current flow or geometrical considerations. Equations are formulated locally for each segment, which are then combined to obtain a solution for the entire structure. For complex geometries, the number of mesh points increase, which directly leads to longer run times. The two structures modeled in the LTCC process - the multilayer solenoid inductor, and the gridded plate parallel plate capacitor, both had many regions of complex geometry and rapidly changing current flow. Without taking into account processing effects such as varying dielectric thicknesses, and complex via geometries that often occur in a LTCC process, models of such structures would more than likely generate very large matrices using a numerical method, and would take extremely long to solve. The developed method, on the other hand, has produced circuit models of various structures which all simulate in under a minute in a standard circuit simulator, and produce accurate results. This developed method could very well prove to be an important technique for circuit design in multilayer processes such as LTCC. 194

223 8.2. Discussion Several important issues which should be considered in order to obtain successful optimizations and building block models are now discussed. Many of the issues presented here are the result of experience gained under this research, and will help guide the reader in obtaining successful results themselves Test Structure Design When designing test structures, it is always a good idea to incorporate a simple straight line test structure, as has been done in all cases in this thesis. Apart for modeling an uncoupled square, it allows for an investigation of basic material properties. A good estimate of basic material parameters is crucial for optimization starting points, especially when attempting a multi-building block optimization. Modeling of coupling is extremely important. In order to model coupling behavior, it would be a good idea to have two distinctly different types of test structures; physically connected (such as a serpentine resistor) and physically disconnected (such as an interdigital capacitor). In a physically connected structure there is significant current flow through the device. Since mutual inductance is affected by current flow, it s effect will be observable and will be easy to extract. For a physically disconnected device, the major signal transmission mechanism is capacitive coupling, and since the output response is highly dependent upon it, it will be easy to deembed. If only one test structure is used for deembedding both coupling components, one will affect the output response 195

224 much more than the other, and thus the weaker one may be more difficult to extract. Using both test structures essentially eliminates the lack of sensitivity issue. The coupling information from both of these structures can be combined to develop a single coupled building block Number of Test Structures In theory, and as has been the case for all the examples presented in this thesis, only a minimum number of test structures have been used. It may be advisable, however, to design and use more test structures rather than just the minimum required. The additional test structures should be comprised of the same building block set, but used in different configurations, just so that the extracted models can be verified in more cases before finally being entered into a library Simultaneous Optimization Once initial modeling of building blocks is complete, a few large test structures can be optimized together to fine tune the extracted building blocks. This can be achieved by the use of simultaneous optimization, where the equivalent circuits for each of the building blocks are forced to be the same for each structure, and all structures are simultaneously optimized with respect to their individual measured results. Simultaneous optimization is considerably more complex and time consuming than single structure optimization, but it has the advantage of being far more likely to uniquely deembed building block circuit models. The reason for this is simple if the 196

225 same model is tested in several different environments (test structures) and must work for all of them, then it is more likely to be generally correct Recommendations The modeling methodology has shown good results for both planar and 3-D structures. Further work in validating the method for both kinds of structures is definitely warranted. Various recommendations for the further development of the modeling method are given and listed separately for clarity, and to help properly direct research initiatives in this area Recommendations for Building Blocks New building blocks can be defined to take into account higher order couplings. It will very interesting to investigate higher order mutual inductance effects, since mutual inductance decreases much more slowly than coupling capacitance with distance. Additionally, a comprehensive library of modeled building blocks for various substrates and processes can be gradually built up, ultimately developing a library of components which can be used for actual circuit and system design work. Building block circuit models can be improved so that they take into account retardation. This is especially important when attempting to model structures that are quite large. As a starting point, the rpeec (retarded partial element equivalent circuit) 197

226 circuit might be used, but then modified later as needed. Development of a method to model building blocks directly with S-parameters will also be very useful Recommendations for Test Structure Design In order to ensure accurate building block models are developed, a more comprehensive test structure set can be constructed and used in the building block model extraction stage, as outlined above. Since accurate building block models are crucial to modeling success, significant effort needs to be expended to ensure the models are as accurate as possible. A large number of structures should also be built to test model validity Recommendations for Statistical Modeling One advantage that this method definitely has over others is that statistical models for the building blocks can be developed. This can be achieved by fabricating test structures on various runs of a process and extracting building blocks each time. Statistical models for each of the building blocks can be developed over time, and these can be used to intelligently predict fabricated passive component yield. A probability density function approach to achieving intelligent yield estimations based upon fabricated test structures can be found in [51]. Statistical modeling and accurate yield prediction are very important for reducing production costs. 198

227 Recommendations for Parameter Extraction and Optimization The use of simultaneous optimization techniques can help ensure model validity. This should be used in the future, at least after initial model extraction, to refine all the extracted building block models. Development of methods to help with optimization initial guesses is also worthy of attention, since in many cases successful optimization convergence and the number of iterations required is highly dependent upon a good starting point. This is especially true when trying to optimize many parameters at the same time Recommendations for Implementation The developed modeling method is highly amenable to implementation within an existing EDA framework. A successful implementation can not only aid research efforts, but can also help the method gain wider acceptance and industrial use. It is a well known fact that many good ideas never get implemented, simply because it is too difficult or cumbersome to do so Final Conclusions This research program has allowed us to develop a novel, accurate, and practical, modeling method for predicting the high frequency behavior of small geometry passive devices. This thesis has described the modeling method in detail, and it has been demonstrated on a variety of two and three-dimensional devices. Good results have been 199

228 obtained for all structures, but in the author s opinion, the results for the LTCC structures are particularly impressive. Miniaturized and integrated passive structures will undoubtedly find increasing use in modern and future compact, lightweight, and high performance devices. I believe the predictive modeling method, once properly developed and matured, can be used to great advantage for the successful design and manufacture of such systems. 200

229 APPENDIX A SENSITIVITY ANALYSIS OF 4 SEGMENT RLC CIRCUIT A.1. Introduction In this appendix, a detailed sensitivity analysis of simple RLC circuit is presented. The circuit is a 4 segment RLC ladder network, with the resistance value in the last segment being a different value with respect to the rest of the circuit. Analytical results are shown for the impedance parameters Z 11 and Z 21 with their normalized sensitivities with respect to the various circuit parameters shown in the circuit. Actual equations for the various sensitivities are not presented, but the manner in when they are computed is, along with all associated plots. The circuit under analysis is shown in Figure A.1-1. As can be seen, the value of the resistance R2 in the last RLC segment is different from all other resistances in the circuit. This analysis will show the relative importance of the Z 11 and Z 21 parameters to the circuit parameters. 201

230 + R L R L R L R2 L + V1 - I1 C C C C I2 V2 - Figure A.1-1 Circuit for impedance parameter sensitivity analysis. Circuit impedance parameters are defined by V1 Z V = 2 Z Z Z I1 I 2 (A-1) and are computed by using standard nodal equation formulations. With the use of software symbolic mathematical tools, the following relationships were derived for Z 11 and Z 21. Z 11 = k0 + k1ω + k2ω + k3ω + k4ω + k5ω + k6ω + k7ω + k8ω l ω + l ω + l ω + l ω + l ω + l ω + l ω + l ω (A-2) where the k i and l i are given by the following expressions 202

231 k 0 k = j( 9CR + CR ) k = 10CL 9R C 6RR C k = j( 2C R + 6C LR + 24C LR + 5C R R) 3 = k = 11R LC + 10RR LC + 15L C + C R R (A-3) k = j( 3C R LR + 5C L R + 16C L R + C R L) k = ( 3C RL R2 + 7L C + 3C R L ) 6 2 k k = j( C L R + 3C RL ) = C L The denominator terms are given by l 1 = j4c l = jc( CR + 7CR) l = jc( 2R C 4RR C 10CL) l = C( C R R + 4C LR + 8C LR) (A-4) l = jc( R LC + 6L C + 2RR LC ) l = C( 2C L R + C L R ) l 7 = jc L 4 3 Z 21 has a simpler representation, in that the numerator of the expression simply has a 1 in it, whereas the denominator is the same as for Z 11. The expression for Z 21 is given by 203

232 Z 21 = l ω + l ω + l ω + l ω + l ω + l ω + l ω + l ω. (A-5) It is strikingly clear from the polynomial coefficients of these expressions that the terms are extremely nonlinear, and that solving for them would be a very difficult if not impossible task. It is for this reason that during the parameter extraction process nonlinear optimization is utilized, with a large number of frequency points over a wide frequency band. The sensitivity analysis is conducted over a frequency band of interest and with high resolution in order to determine which parameters affect the output responses, and to what degree. This analysis helps determine whether the circuit (which originated from a test structure) is adequate to deembed the parameters of interest. A sensitivity value of 0 implies that the circuit parameter does not influence the output at all over the band of interest, whereas large values imply a large influence. Parameters which affect the output values considerably will be more easy to deembed than those of lower sensitivity. Taking into account a wide range of frequencies also helps in establishing uniqueness, since the different parameters affect the output response differently over a frequency band, and in order to minimize error over the entire band, a unique value is likely to be extracted. It is possible, however, that the sensitivity responses of several different parameters for one of the impedance parameters track each exactly over a band. In this case, unique parameter extraction from that particular output parameter will not be possible, and additional equations must be obtained - for example, from the other impedance parameter. 204

233 Normalized circuit sensitivities are computed over frequency and with respect to each of the circuit parameters for the circuit shown above. Clearly, deriving symbolic results for the sensitivities would be a complex and pointless task, due to the very complicated expressions that would be generated. For this reason, numerical normalized sensitivities are computed. The equation for sensitivity of F with respect to parameter h this is given by S F h = F( V, h + h) F( V, h) h h F( V, h), h small (A-6) where V represents the vector of unchanging variables of F, h is the parameter in consideration, and h is the increment in h. h must be kept small with respect to h in order for this expression to be accurate. With some manipulation, this then results in impedance parameter sensitivity equations of the form DR( ω, R, L, C, R2) = Z11( ω, 105. R, L, C, R2) Z11( ω, R, L, C, R2) Z11( ω, R, L, C, R2) (A-7) for normalized sensitivity of Z 11 with respect to R over frequency. Similarly formed equations can be obtained for all the circuit parameters and other impedance parameters. This form of the equation is excellent for implementation on computers. Several plots are now presented for the impedance parameters and sensitivities for the circuit being discussed. Some representative circuit values are chose with R=0.2 Ω, R2=0.1 Ω, L=0.1 µh, and C=1 nf for these computations. Direct impedance parameter 205

234 plots are shown in Figure A.1-2, with Z 11 sensitivities in Figure A.1-3 and Figure A.1-4, and Z 21 sensitivities in Figure A.1-5 and Figure A.1-6. Several interesting issues arise from these results. Z 11 and Z 21 are much more sensitive to changes in C and L as opposed to R and R2, as evidenced by the vertical scale on the plots. However, sensitivity with respect to the resistances is not 0, although it is fairly small. However, actual optimization results show that even this small sensitivity is adequate to deembed both R and R2. Another point of interest is that the sensitivities of C and L to Z 11 are almost identical, and track each other over the entire frequency band, in both the real and imaginary parts of the response. This implies that dembedding C and L uniquely will be difficult, even though Z 11 is highly sensitivity value to both the parameters. In looking at the sensitivity of Z 21 with respect to C and L, it is clear that they are not identical, and do not track each other over the band. Utilization of this fact is what enables us to extract the C and L values. This illustrates the importance of utilizing at least two different parameters and not just one in order to obtain successful optimizations. In all of the research work completed under this program, optimizations were performed using two two-port parameter values. 206

235 10 5 Re Z11 w, R, L, C, R2 i Re Z21 w, R, L, C, R2 i w i Im Z11 w, R, L, C, R2 i Im Z21 w, R, L, C, R2 i w i Figure A.1-2. Z 11 and Z 21 real and imaginary components for RLC circuit 207

236 Re DL w, R, L, C, R2 i Re DC w, R, L, C, R2 i w i Im DL w, R, L, C, R2 i Im DC w, R, L, C, R2 i w i Figure A.1-3. Z 11 sensitivity with respect to C and L for RLC circuit, real and imaginary parts. 208

237 Re DR w, R, L, C, R2 i Re DR2 w, R, L, C, R2 i w i Im DR w, R, L, C, R2 i Im DR2 w, R, L, C, R2 i w i Figure A.1-4. Z 11 sensitivity with respect to R and R2 for RLC circuit, real and imaginary parts. 209

238 40 20 Re DL w, R, L, C, R2 i Re DC w, R, L, C, R2 i w i Im DL w, R, L, C, R2 i Im DC w, R, L, C, R2 i w i Figure A.1-5. Z 21 sensitivity with respect to C and L for RLC circuit, real and imaginary parts. 210

239 Re DR w, R, L, C, R2 i Re DR2 w, R, L, C, R2 i w i Im DR w, R, L, C, R2 i Im DR2 w, R, L, C, R2 i w i Figure A.1-6. Z 21 sensitivity with respect to R and R2 for RLC circuit, real and imaginary parts. 211

240 APPENDIX B CURRENT FLOW VISUALIZATION SOFTWARE B.1. Introduction A key issue in the proposed modeling methodology is the determination of the sizes and shapes of the various building blocks. Since the method is based on connecting various blocks together, it is desirable to verify for simple structures in a fairly tightly constrained design rule set, that the addition of a piece of material does not affect the current flow through the building block in question. This implies that simple building blocks should be designed such that they have constant input and output impedance in a structure regardless of which blocks are attached to them; that is, the building blocks are context insensitive. This is not a requirement in a less constrained design rule environment in which a larger number of possible geometry structures are allowed. In this case we could have separate, context sensitive models for a material square, for example, for which in one instance it is connected to another material square, and in the other it is connected to a corner piece. In this article, building blocks of the first type will be discussed. 212

241 For illustrative purposes, consider the two structures shown in Figure B.1-1. In this example, we will try to determine if the shaded piece is a valid corner building block structure. Simply by visual inspection, it is difficult to ascertain that the current flow through the blocks is the same in both instances, that is, the current distribution across the boundaries of the building block does not change for either case. A well known example of this situation is the 2/3 rd rule for corners in which a corner is assumed to have 2/3 rd the resistance value of a square in a straight piece of material due to the nonuniform current flow through that piece. Possible Corner Building Block Figure B.1-1. Possible corner building block and usage in two structures 213

242 B.2. Algorithm For this research, a software program was written to help visualize the current flow through arbitrary geometry 2 dimensional planar passive devices. The main program is essentially a two dimensional circuit solver and a voltage and current visualization tool. The voltage and current distributions and their corresponding 2 dimensional gradients can be viewed graphically as indexed colormaps or contour plots. The software takes as input a description of the structure to be solved, as well as the input and output positions, which can be entered using a mouse on a graphical user interface window. Next, a 2 dimensional circuit is constructed with a user controlled accuracy by specifying a grid size. An example schematic of a 6x6 impedance grid is shown in Figure B.2-1. Each grid point represents a sample point within the structure of interest. In actual modeling computations, a much denser grid is used in order to capture the current and voltage distribution at many points within the structure. A structure pattern is defined by open circuiting impedance branches (admittance values of 0). For example, the S shape, shown by diagonal hatching in Figure B.2-2 can be created by open circuiting the impedance branches coincident with the cross hatched and the diagonal hatched regions. 214

243 Figure B.2-1. Representative impedance grid. Each box represents and impedance. 215

244 Figure B.2-2. Definition of S-shaped region on impedance grid. B.2.1. Network Solution Methodology Once the structure has been defined, the next step is to generate the sparse modified nodal admittance (MNA) matrix [43]. This is accomplished using the element stamp method, in which each impedance is represented in the MNA matrix with 4 216

245 positive or negative admittances. For example, for an impedance Z connected between nodes i and j in an impedance grid, entries would be inserted into the overall MNA matrix as shown in the right hand side of Figure B.2-1. i col V i Z j row i 1/Z row j -1/Z col V j -1/Z 1/Z Figure B.2-1. Impedance and corresponding entries in MNA matrix. Once the admittance matrix is established, input and output connection terminals for the structure are defined. An ideal current source is inserted between these points, and the output point is grounded. The insertion of the current source allows us to set up a nonsingular set of equations which can be solved for nodal voltages throughout the structure. Current flow in the x and y directions can also be calculated from the voltage distribution by the computing the voltage gradients, since impedance is assumed to be spatially constant. The system is finally solved using lower-upper matrix decomposition (LU) techniques to compute the voltage and current distribution within the structure [52]. Remapping routines then take the results and remap them graphically to correspond with the drawn structure. Current flow can be analyzed by viewing the x and y gradients of the voltage, since the grid impedance is fixed. 217

246 B.2.2. Mathematical Implementation Matlab was used as the implementation environment. The generalized system formulation is given by [ ][ V ] [ I] M = (B-1) where M is the MNA matrix, V is the vector of node voltages, and I is the right hand side current vector. A LU decomposition formulation modifies the equation to [ L ][ U ][ V ] [ I ] which can be solved in two steps using an auxiliary vector Z as M M = (B-2) [ LM ][ Z] = [ I] [ U ][ V ] = [ Z] M (B-3) Once the vector V has been computed, it must be then remapped back to the geometry of the structure under analysis, that is converting a 1 dimensional matrix into a 2 dimensional matrix. This can be accomplished fairly easily, if a left to right node numbering scheme is used in the generation of the MNA matrix, as is best illustrated by Figure B

247 2D Voltage Mesh Matrix Voltage Vector V 1 V 2 V n V 1 V n+1 V n+2 V 2n V 2 V n 2 -n+1 V n 2 V n 2 -n+2 V n V n+1 V n 2 Figure B.2-1. Mapping operation between computed voltage vector and 2D voltage matrix for actual geometrical structure being analyzed. The software is highly efficient in terms of both speed and memory requirements. Sparse matrix routines are used, which yield great savings in terms of memory. For example, a 60x60 grid would represent a 3600 element circuit and hence a tableau matrix size of 3600x3600. If sparsity were not used, this matrix would occupy over 100 MB of memory using IEEE 64-bit floating point precision. However, using sparse matrix techniques, a "virtual" 3600x3600 matrix is constructed using indexing, with most matrices having densities of less than 0.1% and memory requirements on the order of 100KB - a savings of 4 orders of magnitude. A sparsity plot of an MNA matrix developed for solving a resistor current distribution is shown in Figure B.2-2. This matrix is only % dense. 219

248 Figure B.2-2. MNA matrix sparsity pattern for serpentine resistor analysis. 220

249 Figure B.2-3 Contour and indexed image plots of current distribution for two different geometry bends 221

250 B.3. Visualization Results An example of the output generated by the software can be seen in Figure B.2-3. The program shows the current flow contour (x and y current gradient) and color indexed (magnitude of current gradient) image plots of current flow through the structures considered in Figure B.1-1. As can be seen, the current distribution through the corners in both cases is considerably different. This implies that a single square corner is not an appropriate building block, since the current flow and thus impedance across the corner square is modified when additional material is attached to it. Visualization results for a gridded metal plate are presented. The input and output points are at the stubs on the left and right hand sides of the structure. Gridded plates occur in many technologies where it is not possible to achieve good meal coverage. The grid used in this case was 120 x 120, yielding a total of 14,400 grid points. Several output plots for this case are shown, including indexed color plots which show current intensity, contour plots which show current crowding, as well as some cross section current gradient profiles. Figure B.3-1 shows the current intensity plot through the structure. Actual current profiles through sections A-A, B-B, and C-C are shown in Figure B.3-4, Figure B.3-5, and Figure B.3-6 respectively. The magnitude of the current gradient is shown in a contour plot in Figure B.3-2, and a overlay plot of X and Y directed current gradients illustrating the current crowding effect is shown in Figure B

251 Figure B.3-1. Indexed current intensity plot of gridded structure. 223

252 Figure B.3-2. Current gradient magnitude contour plot. 224

253 Figure B.3-3. Contour plots of X and Y directed current gradients showing current crowding effects. 225