Microelectronic Devices and Circuits Lecture 13  Linear Equivalent Circuits  Outline Announcements Exam Two 


 Allen Cross
 2 years ago
 Views:
Transcription
1 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large signal models, w. charge stores pn diode, BJT, MOSFET (subthreshold and strong inversion) Small signal models; linear equivalent circuits General two, three, and four terminal devices pn diodes: Linearizing the exponential diode Adding linearized charge stores BJTs: Linearizing the F.A.R. βmodel Adding linearized charge stores MOSFETs: Linearized strong inversion model Linearized subthreshold model Adding linearized charge stores Clif Fonstad, 10/27/09 Lecture 13 Slide 1
2 Subthreshold Operation of MOSFETs, cont. t ox 0 x D t n The barrier at the n p junction is lowered near the oxidesi interface for any v GS > V FB. The barrier is lowered by φ(x) φ p for 0 < x < x D. (This is the effective v BE on the lateral BJT between x and x dx.) V FB < v GS < V φ(0,y) T G v S DS > 0 D φ n v DS x Injection n n p v BS = 0 The barrier lowering (effective forward bias) (1) is controlled by v GS, and (2) decreases quickly with x. v BE,eff (x) B 0 L y = [φ(x) φ p ] v GS φp Clif Fonstad, 10/27/09 Injection occurs over this range, Lecture 13 Slide 2 but is largest near x = 0. φ p φ(x) φ p φ n φ p φ(x) 0 φ(x)φ p L φ(0) Plot vs y at fixed x, 0 < x < x D. Plot vs x at fixed y, 0 < y < L. φ m t ox x d x y
3 Subthreshold Operation of MOSFETs, cont. To calculate i D, we first find the current in each dx thick slab: S V FB < v GS < V T G v DS > 0 D t ox 0 x xdx n n p x D v BS = 0 x n' x,0 0 L ( ) $ n i e q"(x,v GS )/ kt n' x,l ( ) = n i e q"(x,v GS )/ kt #1 n'(x,0) " n'(x,l) di D (x) = qd e L Clif Fonstad, 10/27/09 y ( ) " n' x,0 ( )e #qv DS / kt W dx # W L D e qn i 1" e "qv DS ( / kt ) )e q$(x,v GS )/ kt dx Lecture 13 Slide 3
4 Subthreshold Operation of MOSFETs, cont. Integrating this from x = 0 to x = x D using the approximate value for the integral derived in Lecture 9, and approximating the relationship between Δφ(0) and Δv GS as linear, i.e. Δφ(0) Δv GS /n, we arrived at: i D, s"t (v GS,v DS,0) # W L µ $ * kt ' e C ox & ) % q ( where & ( n " ' 1 1 * )( C ox # Si qn A [ ] 2 $2% p 2 [ n "1] e q { v GS "V T } nkt 1" e "qv DS / kt ( ) * (,( = Variations on this form: It is common to see i D,st written using the factors K and γ we defined earlier, and with kt/q replaced by V t, the thermal voltage, and [n 1] replaced in the prefactor. Written this way, we have: ( ) 2 $ i D,s"t (v GS,v DS,0) # K V t 2 ["2% p ] e { vgs "VT } nv t 1" e "v DS /V t with " # 2$ qn Si A, K # W (, * L µ * " * ec * ox, n(v BS ) % ) 1 [ ] C ox * 2 &2' p & v BS. * Clif Fonstad, 10/27/09 Lecture 13 Slide 4
5 Subthreshold Output Characteristic We plot a family of i D vs v DS curves with (v GS V T ) as the family variable, after first defining the subthreshold diode saturation current, I S,st : 2 $ I S,s"t # K V t [ ] 2 "2% p = KV 2 t [ n "1] 10 1 I S,st 10 2 I S,st 10 3 I S,st 10 4 I S,st log i D,st (v GS V T ) = 0.06xn Volts (v GS V T ) = 0.12xn Volts (v GS V T ) = 0.18xn Volts (v GS V T ) = 0.24xn Volts v DS { i D,s"t (v GS,v DS,0) # I S,s"t e v GS "V T } nv t 1" e "v DS /V t ( ) Clif Fonstad, 10/27/09 Lecture 13 Slide 5
6 Large Signal Model for MOSFET Operating Subthreshold The large signal model for a MOSFET operating in the weak inversion or subthreshold region looks the same model as that for a device operating in strong inversion (v GS > V T ) EXCEPT there is a different equation relating i D to v GS, v DS, and v BS : We will limit our model to v GS " V T, v DS > 3V t and v BS = 0. D i D G i G (= 0) i D (v GS, v DS ) i G,s"t (v GS,v DS,v BS ) = 0 S,B { i D,s"t (v GS,v DS,0) # I S,s"t ( 1" $v DS )e v GS "V To } nv t 1" e "v DS /V t ( ) 1 for v DS > 3 V t Early effect Clif Fonstad, 10/27/09 Lecture 13 Slide 6
7 Large signal models with charge stores: A pn diode: BJT: npn (in F.A.R.) B IBS qbc ib IBS B C qab!fib q AB : Excess carriers on pside plus excess carriers on nside plus junction depletion charge. q BE : Excess carriers in base plus EB junction depletion charge q BC : CB junction depletion charge MOSFET: nchannel G qg qbe D E qdb id B q G : Gate charge; a function of v GS, v DS, and v BS. q DB : DB junction depletion charge q SB : SB junction depletion charge Clif Fonstad, 10/27/09 S qsb Lecture 13 Slide 7
8 Signal notation: A transistor circuit, whether digital or analog, is typically connected to several DC power supplies that establish the desired DC "bias" currents and voltages throughout it. It also typically has one or more time varying input signals that result in time varying currents and voltages (one of which is the desired output of the circuit) being added to the DC bias currents and voltages. Each voltage and current in such a circuit thus has a DC bias portion and a signal portion, which add to make the total. We use the following notation to identify these components and the total: i A (t) = I A i a (t) v AB (t) = V AB v ab (t) Total: lowercase letter and uppercase subscript. Bias: uppercase letter and subscript. Signal: lowercase letter and subscript. Clif Fonstad, 10/27/09 Lecture 13 Slide 8
9 DC Bias Values: To construct linear amplifiers and other linear signal processing circuits from nonlinear electronic devices we must use regions in the nonlinear characteristics that are locally linear over useful current and voltage ranges, and operate there. To accomplish this we must design the circuit so that the DC voltages and currents throughout it "bias" all the devices in the circuit into their desired regions, e.g. yield the proper bias currents and voltages: I A, I B, I C, I D, etc. and V AG, V BG, V CG,V DG, etc. This design is done with the signal inputs set to zero and using the large signal static device models we have developed for the nonlinear devices we studied: diodes, BJTs, MOSFETs. Working with these models to get the bias values, though not onerous, can be tedious. It is not something we want to have to do to find voltages and currents when the signal inputs are applied. Instead we use linear equivalent circuits. Clif Fonstad, 10/27/09 Lecture 13 Slide 9
10 Linear equivalent circuits: After biasing each nonlinear devices at the proper point the signal currents and voltages throughout the circuit will be linearly related for small enough input signals. To calculate how they are related, we make use of the linear equivalent circuit (LEC) of our circuit. The LEC of any circuit is a combination of linear circuit elements (resistors, capacitors, inductors, and dependent sources) that correctly models and predicts the firstorder changes in the currents and voltages throughout the circuit when the input signals change. A circuit model that represents the proper first order linear relationships between the signal currents and voltages in a nonlinear device is call an LEC for that device. Our next objective is to develop LECs for each of the nonlinear devices we have studied: diodes, BJTs biased in their forward active region (FAR), and MOSFETs biased in their subthreshold and strong inversion FARs. Clif Fonstad, 10/27/09 Lecture 13 Slide 10
11 Creating a linear equivalent circuit, LEC: Consider a device with three terminals, X, Y, and Z: q X (v XZ, v XY ) q Y (v YZ, v YX ) X i X (v XZ, v YZ ) i Y (v XZ, v YZ ) Y Z Suppose, as is our situation with the large signal device models we have developed in 6.012, that we have expressions for the currents into terminals X and Y in terms of the voltages v XZ and v YZ : i X (v XZ,v YZ ) and i Y (v XZ,v YZ ) and that we similarly have expressions for the charge stores associated with terminals X and Y: q X (v XZ,v YZ ) and q Y (v XZ,v YZ ) Clif Fonstad, 10/27/09 Lecture 13 Slide 11
12 Creating an LEC, cont.: We begin with our static model expressions for the terminal characteristics, and write a Taylor's series expansion of them about a bias point, Q, defined as a specific set of v XZ and v YZ that we write, using our notation, as V XZ and V YZ For example, for the current into terminal X we have: i X (v XZ,v YZ ) = i X (V XZ,V YZ ) "i X (v XZ #V XZ ) "i X YZ #V YZ ) "v XZ "v Q YZ Q(v 1 2 " 2 i X 2 "v XZ Q (v XZ #V XZ ) 2 1 " 2 i X 2 2 "v YZ YZ #V YZ ) Q(v 2 1 " 2 i X (v XZ #V XZ )(v YZ #V YZ ) even higher order terms 2 "v XZ "v YZ Q For sufficiently small* (v XZ V XZ ) and (v YZ V YZ ), the second and higher order terms are negligible, and we have: i X (v XZ,v YZ ) " i X (V XZ,V YZ ) #i X (v XZ $V XZ ) #i X (v YZ $V YZ ) #v XZ #v Q YZ Q i X (V XZ,V YZ ) = I X (V XZ,V YZ ) [ v XZ "V XZ ] # v xz [ v YZ "V YZ ] # v yz Clif Fonstad, 10/27/09 Lecture 13 Slide 12 * What is "sufficiently small" is determined by the magnitude of the higher order derivatives.
13 Creating an LEC, cont.: So far we have: Next we define: i X (v XZ,v YZ ) " I X (V XZ,V YZ ) # $i X v xz $i X v yz $v XZ $v Q YZ Q [ i X " I X ] # i x "i X "v XZ Q # g i "i X "v YZ Q Replacing the partial derivatives with the conductances we have defined, gives us our working form of the linear equation relating the incremental variables: i x " g i v xz g r v yz Doing the same for i Y, we arrive at i y " g f v xz g o v yz g f # $i Y where $v XZ Q A circuit matching these relationships is seen below: x v xz z i x g i g r v yz g f v xz g o # $i Y $v YZ Q Clif Fonstad, 10/27/09 Lecture 13 Slide 13 g o i y y v yz z # g r
14 Creating an LEC, cont.: This linear equivalent circuit is only good at low frequencies: i x x y v g xz g r v yz g f v g v i o yz xz z z To handle high frequency signals, we linearize the charge stores' dependencies on voltage also. q X (v XZ, v XY ) q Y (v YZ, v YX ) i y Z Their LECs are linear capacitors: "q X "v XZ Q X i X (v XZ, v YZ ) i Y (v XZ, v YZ ) # C xz "q Y "v YZ Q # C yz "q X "v XY Q Y $ # C xy = "q Y & % "v YX Q Clif Fonstad, 10/27/09 Lecture 13 Slide 14 ' ) (
15 Creating an LEC, cont.: Adding these to the model yields: i x C x xy y v C xz xz g i g o v g g f v r v yz C yz yz xz z z Two important points: #1 All of the elements in this LEC depend on the bias point, Q: g i = "i X, g r = "i X, g f = "i Y, g o = "i Y, C xz = "q X, C xy = "q X, C yz = "q Y "v XZ "v Q YZ "v Q XZ "v Q YZ "v Q XZ "v Q XY "v Q YZ Q #2 The devicespecific nature of an LEC is manifested in the dependences of the element values on the bias currents and voltages, rather than in the topology of the LEC. Thus, different devices may have LECs that look the same. (For example, the BJ and FET LECs may look similar, but some of the elements depend much differently on the bias point values.) Clif Fonstad, 10/27/09 Lecture 13 Slide 15 i y
16 Linear equivalent circuit (LEC) for pn diodes (low f): We begin with the static model for the terminal characteristics: i D (v AB ) = I S e qv AB kt "1 [ ] Linearizing i D about V AB, which we will denote by Q (for quiescent bias point): i D (v AB ) " i D (V AB ) #i D #v AB Q [ v AB $V AB ] IBS I S A id We define the equivalent incremental conductance of the diode, g d, g d " #i D #v AB Q = q kt I S eqv AB / kt $ and we use our notation to write: I D = i D (V AB ), ending up with qi D kt i d = [ i D " I D ], v ab = [ v AB "V AB ] i d = g d v ab The corresponding LEC is shown at right: id a g d b B vab vab g d " q I D kt Clif Fonstad, 10/27/09 Lecture 13 Slide 16
17 LEC for pn diodes (high f): At high frequencies we must include the charge store, q AB, and linearize its two components*: A q DP (v AB ) = "AqN Ap x p q AB = q DP q QNR,p"side Depletion layer charge store, q DP, and its linear equivalent capacitance, C dp : ( v AB ) # "A 2q$ Si N Ap % b " v AB ( ) IBS B qab C dp (V AB ) & 'q DP 'v AB Q = A q$ Si N Ap ( ) 2 % b "V AB a Diffusion charge store, q QNR,pside, and its linear equivalent capacitance, C df : q QNR,p"side (v AB ) = i D[ w p " x p ] 2 2D e C df (V AB ) " #q QNR,p$side #v AB Q = q I D kt [ w p $ x p ] 2 g d b C d [ ] 2 = g d % d with % d " w p $ x p 2D e 2D e Clif Fonstad, 10/27/09 Lecture 13 Slide 17 * This discusion assumes an n p diode)
18 Linear equivalent circuit for BJTs in FAR (low f): In the forward active region, our static model says: [ ] i B (v BE,v CE ) = I BS e qv BE kt "1 i C (v BE,v CE ) = # o [ 1 $v CE ]i B (v BE,v CE ) = # o I BS e qv BE kt "1 [ ] 1 $v CE [ ] We begin by linearizing ic about Q: i c (v be,v ce ) = "i C v be "i C v ce = g m v be g o v ce "v BE "v Q CE Q We introduced the transconductance, g m, and the output conductance, g o, defined as: g m " #i C #v BE Q g o " #i C #v CE Q Evaluating these partial derivatives using our expression for i C, we find: g m = q kt " I o BS eqv kt BE [ 1 #V CE ] $ qi C kt [ ] # $ # I C or $ I C ' g o = " o I BS e qv BE kt 1 Clif Fonstad, 10/27/09 Lecture 13 Slide 18 % & V A ( * )
19 LEC for BJTs (low f), cont.: Turning next to i B, we note it only depends on v BE so we have: i b (v be ) = "i B v be = g # v be "v BE Q The input conductance, g π, is defined as: g " # $i B $v BE Q (Notice that we do not define g π as qi B /kt) To evaluate g π we do not use our expression for i B, but instead use i B = i C /β o : g " # $i B = 1 $i C = g m = q I C $v BE % Q o $v BE % Q o kt % o Representing this as a circuit we have: i b b c v be g! v! g m v! g o e e Clif Fonstad, 10/27/09 (Notice that v be is also called v π ) Lecture 13 Slide 19 i c v ce
20 LEC for BJTs (high f): To extend the model to high frequency we linearize the charge stores associated with the junctions and add them. The basecollector junction is reverse biased so the charge associated with it, q BC, is the depletion region charge. The corresponding capacitance is labeled C µ. B qbc qbe ib IBS C E!FiB q BC (v BC ) " #A 2q$ Si [% b,bc # v BC ]N DC C µ (V BC ) " #q BC #v BC Q = A q$ Si N DC [ ] 2 % b &V BC The baseemitter junction is forward biased and its dominant charge store is the excess charge injected into the base; the baseemitter depletion charge store less important. 2 D q BE (v BE ) " Aqn e i e qv BE / [ kt #1] " w 2 B, eff i C (v BE ) N AB w B, eff 2D e The linear equivalent capacitance is labeled C π. Clif Fonstad, 10/27/09 Lecture 13 Slide 20
21 LEC for BJTs (high f), cont: C π can be written in terms of g m and τ b : C " (V BE ) # $q BE $v BE Q % w 2 B,eff 2D e qi C kt = g m& b " b # w B,eff 2 D e Adding C π and C µ to our BJT low frequency LEC we get the full BJT LEC: i b C µ i c b c v be g! v! g m v! g o C! e e 2 v ce Clif Fonstad, 10/27/09 g m = q I C kt g " = g m # F ( ) g o = $ I C = I C V A C µ C % = A = g m & b q" Si N DC [ ] 2 # b $V BC Lecture 13 Slide 21
22 LEC for MOSFETs in saturation (low f): In saturation, our static model is: (Recall that α 1) i G (v GS,v DS,v BS ) = 0 i B (v GS,v DS,v BS ) " 0 i D (v GS,v DS,v BS ) = K 2# v $V v GS T ( BS) [ ] 2 [ 1 %( v DS $V DS,sat )] with K & W L µ * ec ox and V T = V To '( 2( p$si $ v BS $ 2( ) p$si Note that because i G and i B are zero they are already linear, and we can focus on i D. Linearizing i D about Q we have: i d (v gs,v ds,v bs ) = "i D "v GS Q v gs "i D v ds "i D v bs "v DS "v Q BS Q = g m v gs g o v ds g mb v bs We have introduced the transconductance, g m, output conductance, g o, and substrate transconductance, g mb : g m " #i D #v GS Q g o " #i D #v DS Q g mb " #i D #v BS Q Clif Fonstad, 10/27/09 Lecture 13 Slide 22
23 LEC for MOSFETs in saturation (low f), cont.: A circuit containing all these elements, i.e. the actual LEC, is: i g g d v gs v g m v gs g mb v bs g ds o s s v bs i b b Evaluating the conductances in saturation we find: i d g m " #i D #v GS Q g o " #i D #v DS Q = K [ $ V %V (V ) GS T BS ][ 1 &V DS ] ' 2K I D $ = K [ 2$ V %V (V ) GS T BS ] 2 & ' & I D g mb " #i D #v BS Q = % K [ $ V GS %V T (V BS )][ 1 &V DS ] #V T #v BS Q = ( g m Clif Fonstad, 10/27/09 Lecture 13 Slide 23
24 LEC for MOSFETs in saturation (high f): For the high frequency model we qdb linearize and add the charge qg stores associated with each pair id of terminals. G Two, q SB and q DB, are depletion region charge stores associated qsb with the n regions of the source S and drain. They are relatively straightforward compared to q G., as we will see below. q SB and q DB contribute two capacitors, C sb and C db, to our LEC. The gate charge, q G, depends in general on v GS, v DS, and v GB (= v GS v BS ), but in saturation, q G only depends on v GS and v GB (i.e. v GS and v BS ) in our model, adding C gs and C gb. When v GS V T the drain is ideally decoupled from the gate, but in any real device there is fringing capacitance between the gate electrode and the drain diffusion that we must include as C gd, a parasitic element. Clif Fonstad, 10/27/09 Lecture 13 Slide 24 D B
25 LEC for MOSFETs in saturation (high f), cont.: Adding all these capacitors to our LEC yields: g i g C gd i d d v gs s C gs g m v gs g mb v bs g o s We find the following results: C gs " #q G #v GS Q v bs C sb C db v ds b i b = 2 3 W LC * ox C gb C sb,c gb,c db : depletion capacitances C gd = W C * * gd, where C gd is the GD fringing and overlap capacitance per unit gate length (parasitic) g m " 2K I D # g o " $ I D g mb = % g m, where % = & 2 2' p (V BS Clif Fonstad, 10/27/09 Lecture 13 Slide 25
26 LEC for MOSFETs in saturation when v bs = 0: A very common situation in many circuits is that there is no signal applied between on the base, i.e. v bs = 0 (even though it may be biased relative to the source, V BS 0). In this case the MOSFET LEC simplifies significantly: The elements that remain retain their original dependences: C gs " #q G #v GS Q i g = 2 3 W LC * ox C db : depletion capacitance C gd g d v gs v C gs g m v ds gs g o C db s,b s,b g m " 2K I D # g o " $ I D C gd = W C * * gd, where C gd is the GD fringing and overlap capacitance per unit gate length (parasitic) Clif Fonstad, 10/27/09 Lecture 13 Slide 26 i d
27 LEC for Subthreshold MOSFETs, v BS = 0: Our large signal model for MOSFETs operated in the subthreshold FAR (v DS >> kt/q) and v BS = 0, is: D i D G i G (= 0) S,B i D (v GS, v DS ) i G,s"t (v GS,v DS,v BS ) = 0 { i D,s"t (v GS,v DS ) # I S,s"t ( 1" $v DS )e v GS "V To } nv t Like a MOSFET in saturation with v bs = 0, the LEC has only two elements, g m and g o, but now g m is quite different: g m " #i D q = #v GS nkt I S,s$t ( 1$ %V DS )e q ( V GS $V to ) nkt = qi D nkt Q g o " #i D #v DS Q = % I S,s$t e q ( V GS $V to) nkt & % I D ' or & I * D ), ( V A Clif Fonstad, 10/27/09 Lecture 13 Slide 27
28 LEC for Subthreshold MOSFETs, v BS = 0, cont.: The LEC for MOSFETs in subthreshold FAR (v DS >> kt/q) and v BS = 0, is: i g g d v gs v g m v gs g ds o s,b s,b g m = q I D nkt The charge store q DB is the same as q DB in a MOSFETs operated in strong inversion, but g G is not. g G is the gate capacitance in depletion (V FB < v GB < V T ), so it is smaller in subthreshold. g o " # I D Clif Fonstad, 10/27/09 Lecture 13 Slide 28 G qg i d D S,B id qdb
29 LEC for Subthreshold MOSFETs, v BS = 0, cont.: Adding the linear capacitors corresponding to the charge stores we have: C gs " #q G #v GS Q i g C gd g d v gs v C g m v ds gs gs g o C db s,b s,b $ = W L C ox C gd = W C * * gd, where C gd 1 2C $ 2 ox ( V GS %V FB ) & Si qn A is the GD fringing and overlap i d * See Lecture 9, Slides 7 and 8, for q G and the derivation of C gs. C db : depletion capacitance g m = q I D nkt g o " # I D Notice that as before, C gd is zero in our ideal model. It a parasitic that cannot be avoided and must be included because it limits device and circuit performance. Clif Fonstad, 10/27/09 Lecture 13 Slide 29
30 Comparing the low frequency LECs: All of our circuit design will be done for operation at "low" frequencies, that is where the charge store capacitances play a negligible role. Thus it is interesting to compare our three transistor LECs when this is true. They all have the same topology, but differ importantly in g i and g m : i in in out v in g i g m v in g o v out common common Bias dependences: i out BJT ST MOS SI MOS g i : q I C " F kt 0 0 g m : q I C kt qi D n kt 2KI D # g o : $ I C $ I D $ I D ST = subthreshold SI = strong inversion * We will say more about the significance of these Clif Fonstad, 10/27/09 differences when we study amplifier design. Lecture 13 Slide 30
31 The importance of the bias current: A very important observation is that all of the elements in the three LECs we compared depend on the bias level of the output current, I C, in the case of a BJT, or I D, in the case of a MOSFET: Bias dependences: BJT ST MOS SI MOS g i : q I C " F kt 0 0 g m : q I C kt q I D n kt 2KI D # g o : $ I C $ I D $ I D ST = subthreshold SI = strong inversion The bias circuitry is a key part of any linear amplifier. The designer must establish a stable bias point for all the transistors in the amplifier to insure that the gain remains constant and stable. We will study amplifier design and practice beginning with Lecture 17. Clif Fonstad, 10/27/09 Lecture 13 Slide 31
32 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Summary Reminder Exam Two In ~ 1 wk., Thursday, Nov. 5, 7:309:30 p.m. SubThreshold Refs Lecture 12 slides; Subthreshold writeup Notation Total = Bias Signal i A (t) = I A v AB (t) = V AB i a (t) v ab (t) Large signal model Design and analysis of bias conditions Linear equivalent circuits Signal portion design/analysis Small signal models; linear equivalent circuits Everything depends on the bias point The value of each element in an LEC depends on the bias point (often the bias current). Concentrate for now on low frequency LECs Full spectrum LECs with capacitors will only be used to find the upper bound on the low frequency range of operation. We won't see them again until Lecture 23. Clif Fonstad, 10/27/09 Lecture 13 Slide 32
33 MIT OpenCourseWare Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit:
Electronic Devices and Circuits Lecture 14  Linear Equivalent Circuits  Outline Announcements
6.012 Electronic Devices and Circuits Lecture 14 Linear Equivalent Circuits Outline Announcements Handout Lecture Outline and Summary Review Adding refinements to large signal models Charge stores: depletion
More informationElectronic Devices and Circuits Lecture 18  Single Transistor Amplifier Stages  Outline Announcements. Notes on Single Transistor Amplifiers
6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,
More informationElectronic Devices and Circuits Lecture 15  Digital Circuits: Inverter Basics  Outline Announcements. = total current; I D
6.012  Electronic Devices and Circuits Lecture 15  Digital Circuits: Inverter asics  Outline Announcements Handout  Lecture Outline and Summary The MOSFET alpha factor  use definition in lecture,
More informationBipolar junction transistor operation and modeling
6.01  Electronic Devices and Circuits Lecture 8  Bipolar Junction Transistor Basics  Outline Announcements Handout  Lecture Outline and Summary; Old eam 1's on Stellar First Hour Eam  Oct. 8, 7:309:30
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationMicroelectronic Devices and Circuits Lecture 9  MOS Capacitors I  Outline Announcements Problem set 5 
6.012  Microelectronic Devices and Circuits Lecture 9  MOS Capacitors I  Outline Announcements Problem set 5  Posted on Stellar. Due net Wednesday. Qualitative description  MOS in thermal equilibrium
More information6.012 MICROELECTRONIC DEVICES AND CIRCUITS
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.012 MICROELECTRONIC DEVICES AND CIRCUITS Answers to Exam 2 Spring 2008 Problem 1: Graded by Prof. Fonstad
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationReview  Differential Amplifier Basics Difference and commonmode signals: v ID
6.012 Microelectronic Devices and Circuits Lecture 20 DiffAmp Anal. I: Metrics, Max. Gain Outline Announcements Announcements D.P.: No Early effect in large signal analysis; just LECs. Lec. 21 foils useful;
More informationElectronic Devices and Circuits Lecture 5  pn Junction Injection and Flow  Outline
6.012  Electronic Devices and Circuits Lecture 5  pn Junction Injection and Flow  Outline Review Depletion approimation for an abrupt pn junction Depletion charge storage and depletion capacitance
More informationLecture 16 The pn Junction Diode (III)
Lecture 16 The pn Junction iode (III) Outline I V Characteristics (Review) Small signal equivalent circuit model Carrier charge storage iffusion capacitance Reading Assignment: Howe and Sodini; Chapter
More informationChapter 13 SmallSignal Modeling and Linear Amplification
Chapter 13 SmallSignal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 131 Chapter Goals Understanding of concepts related to: Transistors
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationCMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well
6.01  Microelectronic Devices and Circuits Lecture 16  CMOS scaling; The Roadmap  Outline Announcements PS #9  Will be due next week Friday; no recitation tomorrow. Postings  CMOS scaling (multiple
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationLecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationLecture 16  The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003
6.012  Microelectronic Devices and Circuits  Spring 2003 Lecture 161 Lecture 16  The pn Junction Diode (II) Equivalent Circuit Model April 8, 2003 Contents: 1. IV characteristics (cont.) 2. Smallsignal
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationLecture 29  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 20, 2007
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 291 Lecture 29  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 20, 2007 Contents: 1. Nonideal and secondorder
More informationLecture 17  The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003
6.012  Microelectronic Devices and Circuits  Spring 2003 Lecture 171 Lecture 17  The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation
More informationChargeStorage Elements: BaseCharging Capacitance C b
ChargeStorage Elements: BaseCharging Capacitance C b * Minority electrons are stored in the base  this charge q NB is a function of the baseemitter voltage * base is still neutral... majority carriers
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and crosssectional area 100µm 2
More informationFigure 1: MOSFET symbols.
c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationMOSFET Capacitance Model
MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: nchannel MOSFET Source Gate L Drain W L EFF Poly Gate oxide nactive psub depletion region (electrically
More informationThe Gradual Channel Approximation for the MOSFET:
6.01  Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationEE 330. Lecture 35. Parasitic Capacitances in MOS Devices
EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A  β β VXX Q 2
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat AbuTaha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationLecture #27. The Short Channel Effect (SCE)
Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 21: Bipolar Junction Transistor Administrative Midterm Th 6:308pm in Sibley Auditorium Covering everything
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX =  4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationLecture 28  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 18, 2007
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 281 Lecture 28  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 18, 2007 Contents: 1. Secondorder and
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More information6.012 Electronic Devices and Circuits
Page 1 of 1 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.12 Electronic Devices and Circuits Exam No. 1 Wednesday, October 7, 29 7:3 to 9:3
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationMetaloxidesemiconductor field effect transistors (2 lectures)
Metalidesemiconductor field effect transistors ( lectures) MOS physics (brief in book) Currentvoltage characteristics  pinchoff / channel length modulation  weak inversion  velocity saturation 
More informationDepartment of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM
Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Homework 4 Due on March 01, 2018 at 7:00 PM Suggested Readings: a) Lecture notes Important Note:
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and MK Lee 1. The purest semiconductor crystals it is possible
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationECE 546 Lecture 11 MOS Amplifiers
ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Threeterminal device whose voltagecurrent relationship is controlled by a third voltage
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to MetalOxideSemiconductor FieldEffect transistors (MOSFET) by considering the following structure:
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationRecitation 17: BJTBasic Operation in FAR
Recitation 17: BJTBasic Operation in FAR BJT stands for Bipolar Junction Transistor 1. Can be thought of as two pn junctions back to back, you can have pnp or npn. In analogy to MOSFET small current
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationChapter 5 MOSFET Theory for Submicron Technology
Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are
More informationECE 497 JS Lecture  12 Device Technologies
ECE 497 JS Lecture  12 Device Technologies Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationECE343 Test 2: Mar 21, :008:00, Closed Book. Name : SOLUTION
ECE343 Test 2: Mar 21, 2012 6:008:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Crosssection and layout
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ualwell TrenchIsolated
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationCircuits. L2: MOS Models2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. GNumber
EE610: CMOS Analog Circuits L: MOS Models (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling
ELEC 3908, Physical Electronics, Lecture 19 BJT Base Resistance and Small Signal Modelling Lecture Outline Lecture 17 derived static (dc) injection model to predict dc currents from terminal voltages This
More informationDevice Physics: The Bipolar Transistor
Monolithic Amplifier Circuits: Device Physics: The Bipolar Transistor Chapter 4 Jón Tómas Guðmundsson tumi@hi.is 2. Week Fall 2010 1 Introduction In analog design the transistors are not simply switches
More informationLecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER
Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multistage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationLECTURE 3 MOSFETS II. MOS SCALING What is Scaling?
LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of
More informationReview 5 unknowns: n(x,t), p(x,t), J e. Doping profile problems Electrostatic potential Poisson's equation. (x,t), J h
6.012  Electronic Devices and Circuits Lecture 3  Solving The Five Equations  Outline Announcements Handouts  1. Lecture; 2. Photoconductivity; 3. Solving the 5 eqs. See website for Items 2 and 3.
More informationECE 305 Fall Final Exam (Exam 5) Wednesday, December 13, 2017
NAME: PUID: ECE 305 Fall 017 Final Exam (Exam 5) Wednesday, December 13, 017 This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the ECE policy,
More informationELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling
ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationLongchannel MOSFET IV Corrections
Longchannel MOSFET IV orrections Three MITs of the Day The body ect and its influence on longchannel V th. Longchannel subthreshold conduction and control (subthreshold slope S) Scattering components
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE ptype doped Si (N A = 10 15 to 10 16 cm 3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationBJT Biasing Cont. & Small Signal Model
BJT Biasing Cont. & Small Signal Model Conservative Bias Design Bias Design Example Small Signal BJT Models Small Signal Analysis 1 Emitter Feedback Bias Design Voltage bias circuit Single power supply
More informationLecture 17 The Bipolar Junction Transistor (I) Forward Active Regime
Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Outline The Bipolar Junction Transistor (BJT): structure and basic operation I V characteristics in forward active regime Reading Assignment:
More informationEE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances
EE 435 Lecture 37 Parasitic Capacitances in MOS Devices String DAC Parasitic Capacitances Parasitic Capacitors in MOSFET (will initially consider two) Parasitic Capacitors in MOSFET C GCH Parasitic Capacitors
More informationECE342 Test 2 Solutions, Nov 4, :008:00pm, Closed Book (one page of notes allowed)
ECE342 Test 2 Solutions, Nov 4, 2008 6:008:00pm, Closed Book (one page of notes allowed) Please use the following physical constants in your calculations: Boltzmann s Constant: Electron Charge: Free
More informationELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and SelfHeating
ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and SelfHeating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationECE321 Electronics I
EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman ZarkeshHa Office: EE Bldg. 3B Office hours: Tuesday :3:PM or by appointment Email: payman@ece.unm.edu Slide: 1
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationSemiconductor Physics fall 2012 problems
Semiconductor Physics fall 2012 problems 1. An ntype sample of silicon has a uniform density N D = 10 16 atoms cm 3 of arsenic, and a ptype silicon sample has N A = 10 15 atoms cm 3 of boron. For each
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cutoff. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More information