Characterizing the Behavior of a Probabilistic CMOS Switch Through Analytical Models and Its Verification Through Simulations

Transcription

1 Characterizing the Behavior of a Probabilistic CMOS Switch Through Analytical Models and Its Verification Through Simulations PINAR KORKMAZ, BILGE E. S. AKGUL and KRISHNA V. PALEM Georgia Institute of Technology 1. ABSTRACT Noise immunity and low-energy comuting have become limiting factors in semiconductor roadma as feature sizes shrink. By viewing noise as a resource rather than as an imediment, we resent a new aroach to low-energy comuting. The subject of our study is the robabilistic cmos (cmos) inverter, whose behavior is rendered robabilistic by noise. Summarized through the concet of an energy-robability relationshi for cmos inverters based on ami 0.5µm and tsmc 0.5µm rocesses, we quantitatively show that significant energy savings are ossible when a robabilistic inverter is switched with robability 1/ < < 1, and that these savings increase exonentially as is lowered. We also quantitatively show that increasing the noise rms has the effect of increasing energy er switching ste quadratically. Furthermore, we demonstrate the effects of the noise bandwidth and the outut samling frequency on the robabilistic behaviour of cmos inverters.. INTRODUCTION As cmos devices scaling aroach the nano-meter region, the imact of dee submicron noise has become an imortant challenge, esecially due to noise being seen as an obstacle to reliable comutation. Another significant challenge to cmos design is achieving low energy consumtion for cmos circuits, which has traditionally been addressed by voltage scaling. However, the utility of voltage scaling is decreasing, because lowering the voltage levels, therefore bringing the signal level closer to the noise level reduces noise immunity, and leads to unreliable comuting. In [3] and [4], as a aradigm shift from revious aroaches to overcome these dual challenges to cmos design, noise is viewed as a resource (rather than an imediment) for achieving low energy comuting. In the heart of this new aroach is a robabilistic switch or inverter, whose outut is guaranteed to be correct only with a robability, 0.5 < < 1. It was shown in [19] that by using the robabilistic inverter as a building block, the energy erformance metric at the alication level can be imroved uto a factor of 1900, for a robabilistic string classification alication. In this context, it is crucial to understand the device level behavior of these robabilistic devices which serve as the key building blocks for robabilistic system-on-a-chi (SoC) imlementations. Therefore, in this work, we rovide a comrehensive characterization of a robabilistic cmos (cmos) switch (inverter). Our study is centered on conventional inverters couled with noise to induce the robabilistic behavior. We consider the thermal noise and ower suly noise as the sources of randomness. Secifically, we characterize the robability of correctness () and the energy consumed er switching (E) of such an inverter, which we refer to as the E- relationshi. Furthermore, we characterize the robabilistic behavior for two scenarios of thermal noise source, wherein the thermal noise is couled to the inut or the outut of the inverter. In addition, we establish the imact of the equivalent bandwidth of the noise (see Section 8 for details) on the robabilistic behavior of the cmos Pinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem School of Electrical and Comuter Engineering, Georgia Institute of Technology, USA korkmaz@ece.gatech.edu, bilge@ece.gatech.edu, alem@ece.gatech.edu This work is suorted in art by DARPA Seedling Contract #F CREST Technical Reort, No. TR , Aug 005, Pages 1 35.

2 CREST Technical Reort, No. TR , Aug 005 inverter. We also characterize the imact of the outut samling frequency on the robabilistic behavior of the cmos inverter. In Section 3, we rovide a summary of the background for our work. Following this, we define the robabilistic switch in Section 4, wherein we also rovide a cmos imlementation of the robabilistic switch (inverter). In Section 5, we resent analytical models characterizing the E- relationshi of the robabilistic inverter, where we study both the thermal and ower-suly noise sources lus the two different coulings of thermal noise. In Section 6, we validate our analytical models through comarisons of analytical results with the results of circuit simulations in HSice. In Section 7, we rovide an imroved analytical model characterizing the E- relationshi, wherein we include the short-circuit energy consumtion of the inverter in calculating the energy consumed by the inverter. In addition, we validate the imroved analytical model via comarisons of the model results with the HSice simulation results. In Section 8, we deict the imact of the equivalent bandwidth of the noise, and the outut samling frequency on the robabilistic behavior of the cmos inverter. In Section 9, we show the effect of the surious switchings resulting due to the inut-couled noise on the energy consumtion of a cmos inverter. We conclude the aer in Section BACKGROUND Energy efficiency has become an imortant design criterion for cmos circuits, esecially due to the increasing ubiquity of mobile and ortable alications. One common technique for reducing energy is reducing the suly voltage. For examle, in [8], the effect of voltage suly and threshold voltage scaling on the energy and erformance of a ring oscillator is studied. Similarly, Kuroda et al. [1] describe a variable suly voltage scheme, wherein the suly voltage is changed adatively deending on the required frequency of oeration. However, there are two drawbacks of reducing the suly voltage. One drawback is the increase in the delay of gates. To overcome this roblem, the threshold voltage is also scaled (see [6, 8]). The other drawback of reducing the suly voltage is the degradation of noise immunity of the circuits [6]. In 003 ITRS roadma [9], for examle, it is stated that increasing noise sensitivity has become an imortant issue in the design of devices, circuits and systems due to the reduction in oerating voltage by 0% er technology node. The reduction of the feature sizes leads to a decrease in the number of doants and channel electrons in the active regions of the device [3]. There are random fluctuations in the hysical quantities of the devices such as the channel current resulting from the doants and channel electrons. From the central limit theorem [1], the magnitude of the random variations is inversely roortional to the number of random variables. Thus, as the devices shrink, the random variations become more rominent. Sano [3] has investigated the intrinsic current fluctuations in very small Si-MOSFETs using Monte Carlo device simulations and has found that the normalized standard deviation of the drain current increases as the device width is reduced to the dee submicron regime. Starting from the early work of Stein [5], the limitations that noise is imosing on the scaling of suly voltage and switching energy consumtion of the circuits have been studied. For examle, Natori and Sano [15] have derived a minimum energy consumtion-reliability relationshi for ractical electronic circuits and investigated the scaling limits imosed by thermal noise on digital MOS circuits. Similarly, Kish [10] has studied the otential difficulties of scaling with high density integration due to thermal noise and Hegde and Shanbhag [8] have derived information-theoretic lowerbounds on energy consumtion of noisy digital gates. Differing from the above aroaches, that is, rather than treating noise as an imediment to overcome, but viewing it as a resource of randomness, Palem [17, 18] outlined a framework for robabilistic switches and comutational models based on these switches. These robabilistic comutational models were used to derive low-energy comutational latforms for robabilistic algorithms [14]. Palem s work has shown that well-characterized noise is of significant value in realizing low-energy comuting latforms for robabilistic alications.

3 3 CREST Technical Reort, No. TR , Aug 005 In order to extend Palem s work to the cmos domain, the relationshis between the robability of a switching ste being correct,, and the oerating voltage, as well as the amount of noise in the system, were studied by Cheemavalagu, Korkmaz and Palem [3]. In the center of this work is a cmos inverter, whose robabilistic behavior is characterized as a function of the energy it consumes er switching. Subsequently, this work was extended in [4], wherein an extensive characterization of the relationshis between the noise, oerating voltage, the associated robabilistic behavior, and the energy consumed er switching ste is resented. In this aer, we further extend these characterizations by considering different tyes of noise coulings. Our model has been imroved to characterize the robabilistic behavior induced due to ower suly noise (in addition to thermal noise). We also study the effect of the equivalent bandwidth of the noise, as well as the outut samling frequency on the robabilistic behavior. 4. DEFINITIONS AND CONCEPT In this section, we first define the concets of robabilistic switch and robabilistic switching. introduce a cmos inverter realization of the robabilistic switch. Then we 4.1 Probabilistic Switch We define a switch as a digital device with one inut and one outut. Our choice of the single inut, single outut device is due to the simlicity of the analysis. The outut of the switch is a function, f, of the inut of the switch. The switching is defined as the invocation of the function f, which also corresonds to the event when the outut is comuted. The switching takes finite amount of time T s. The switch and its associated switching can be either deterministic or robabilistic. If we denote the outut of the switch by Y (t) and the inut of the switch by X(t), where t denotes time, then for a deterministic switch, Y (t ) = f(x(t 1 )), where f:{0,1} {0,1} is a function of a single bit, t is the oint in time when the switching ends, and t 1 denotes the oint in time when the switching starts. On the other hand, for a robabilistic switch, { f (X (t1 )) with robability (1/ < < 1) Y (t ) = f (X (t 1 )) with robability 1 In Figure 1, we show a robabilistic switch and a mathematical equivalent of this robabilistic switch; for simlicity, the binary inut is denoted by X and the binary outut is denoted by Y (t is omitted). In the equivalent structure (shown on the righthand side of the figure), every switching is associated with a coin toss, and the outcome of the coin toss is denoted by j. The deterministic switch of the equivalent structure comutes a function g with inuts X and j, and the outut Y of this switch is Y (t ) = g (X, j, t ) = { f (X(t1 )) if j = T f (X(t 1 )) if j = F Since robability is a real number between 1/ and 1, the coin toss should be biased so that it can lead to values of other than 1/. We will introduce the robabilistic cmos inverter in the next section where a conventional cmos inverter is couled with external noise to roduce a robabilistic cmos inverter. The external noise couled to the cmos inverter can be associated with the inut j that is shown in Figure 1. However, when we describe the energy consumtion associated with the robabilistic inverter (in Section 5), we do not consider any additional energy cost due to the generation of j, that is the generation of the external noise in the context of the robabilistic cmos inverter. We note that, in the current reort, the external noise couled to the cmos inverter is a Gaussian random rocess. (1) ()

4 4 CREST Technical Reort, No. TR , Aug 005 Inut (X) Probabilistic Switch Outut(Y) equivalent Inut (X) Deterministic Switch j (the outcome of a coin toss) Outut (Y) Y = f (X) with robability Y = f (X) with robability 1 - Y = g(x, j) = f (X) if j = T f (X) if j = H Figure 1. Definition of a robabilistic switch 4. cmos Inverter Realization of a Probabilistic Switch A cmos inverter is a digital gate that executes the inversion function with one inut and one outut. The switching in this case is the invocation of the inversion function, which, in the context of the cmos inverter, corresonds to the flow of the switching current through the outut caacitance of the inverter. In the context of the switch described in Section 4.1, for a deterministic inverter, Y (t ) = X(t 1 ) where Y and X denote the binary values of the outut and the inut of the inverter, resectively, t denotes the oint in time when the switching ends, and t 1 denotes the oint in time when the switching starts. In addition, the switching time T s = (t t 1 ) is equivalent to the roagation delay of the inverter. For a robabilistic inverter, on the other hand, { X (t1 ) with robability (1/ < < 1) Y (t ) = X (t 1 ) with robability 1- In this aer, the robability results from the noise couled to the cmos inverter. For examle, Figure (c) shows the outut waveform of a cmos inverter which is couled with thermal noise at its inut and has a robability arameter = Because of the noise, the outut voltage of the inverter undergoes transitions to binary 0, while it should be at binary 1, and vice versa. Figures (a) and (b) show the inut and outut waveforms of a deterministic cmos inverter, resectively. Noise in digital cmos ICs can be modeled as coming from the evaluation nodes (inut/outut), ower lines, or ground lines [4]. In Section 5.1, we characterize the robabilistic behavior of a cmos inverter, wherein we consider the thermal noise couled to the inut or the outut of the inverter as shown in Figure 3. In Section 5., we deict the imact of ower suly noise on the robabilistic behavior of the cmos inverter. The thermal and ower suly noise sources are random rocesses that are characterized by a Gaussian distribution. We note that, in Figure, the inut and outut of the cmos inverter, denoted by V in and V out, resectively, are continuous signals. However, the mathematical definition of the robabilistic inverter, which is rovided in (3), is based on binary inut and outut signals. Hence, it is necessary to define the binary equivalents of the continuous inut and outut signals. For the sake of simlicity, we assume that the transfer characteristics of the cmos inverter is idealized as shown in Figure 4(a) as oosed to the realistic transfer characteristics, which is shown in Figure 4(b). Using this idealized transfer characteristics, the binary inut and outut values X and Y associated with the continuous inut and outut signals (V in and V out ) of the cmos inverter are defined as follows: (3) Y (t) = { 1 if Vout (t) V m 0 otherwise (4)

5 Vout (V) Vout (V) Vin (V) 5 CREST Technical Reort, No. TR , Aug (a) u Time (sec) 100u 1 (b) u Time (sec) 100u (c) u 100u Time (sec) Figure. (a) Inut voltage of a deterministic cmos inverter (b) Outut voltage of as deterministic cmos inverter (c) Outut voltage of a robabilistic cmos inverter with robability arameter = 0.89 for the same inut Outut couling Inut couling V S V in V o * V n V out C V S * V n V in V out C (a) (b) Figure 3. The two ways in which thermal noise is couled to a deterministic inverter yielding its robabilistic variant X (t) = { 1 if Vin (t) V m 0 otherwise In equations (4) and (5) V m denotes the midoint voltage of the cmos inverter, which is defined as the oint where the outut voltage of the inverter becomes the same as the inut voltage of the inverter during switching (see Figure 4(b)). We idealize the transfer characteristics of the cmos inverter as shown in Figure 4(a), because the use of this (5)

6 6 CREST Technical Reort, No. TR , Aug 005 V out V out V out Midoint voltage V m V in V V m V in m (a) (b) (c) V in Figure 4. (a) Our idealization to the transfer characteristics of a cmos inverter (b) Realistic transfer characteristics of a cmos inverter (c) Traditional ideal transfer characteristics of a cmos inverter when V m = idealization in deriving the robabilistic behavior has rovided reasonable accuracy when analytical results are comared against the simulation results wherein accuracy is defined as the degree of the closeness of the analytical results to the simulation results. We note that, this idealization has resulted in slightly better accuracy than the traditional idealization of the transfer characteristics of the cmos inverter (see Figure 4(c)). 5. CHARACTERIZATION OF THE PROBABILISTIC BEHAVIOR OF A CMOS INVERTER As stated in Section 4., the robabilistic behavior of a cmos inverter is induced by the noise couled to it. In the current aer, we consider the thermal noise sources couled to the inut or the outut of the inverter (see Figure 3) and the ower suly noise on the ower suly ( ) line. In Section 5.1 below, we resent the analytical model characterizing the robability arameter of a cmos inverter when thermal noise is couled to its inut or outut. In Section 5., we model the imact of ower suly noise on the robabilistic behavior of the cmos inverter. In Section 5.3, we establish the E- relationshi of a robabilistic inverter, which characterizes the energy consumed by a cmos inverter er switching ste as a function of its robability arameter. 5.1 Analytical Modeling of the Probability Parameter () of a cmos Inverter with Inut- or Outut-couled Thermal Noise In the cases that the noise is couled to the inut or the outut of the inverter (see Figure 3), we use the aroximations shown in Figure 5, wherein the inverter is aroximated as an ideal switch in series with a resistor and a caacitor to simlify the analysis. Similar aroximations of an inverter were used in [5, 15, 10]. In this aroximation, the resistor R is the effective on-resistance of each transistor [15] and the caacitor C corresonds to the outut caacitance of the inverter. We assume that the ideal switch switches at V m which corresonds to the midoint voltage of the cmos inverter as exlained before in Section 4.. In the case that thermal noise is couled to the outut of the cmos inverter, referring to Figure 5(a), the inut voltage (V in ) controls the osition of the ideal switch. However, in the case that thermal noise is couled to the inut of the inverter, the osition of the ideal switch is controlled by V s + V n wherein V s denotes the noise-free art of the inut voltage and V n denotes the noise voltage. In the sequel, we will derive an analytical exression modeling the robability arameter of a cmos inverter using the aroximations shown in Figure 5. Referring to the mathematical definition of the robabilistic inverter rovided in Section 4, the switching time T s corresonds to the RC delay of the aroximated circuit. In this section we do not consider the (low-

7 7 CREST Technical Reort, No. TR , Aug 005 V dd Aroximated V in * V n V out C V in R * V n V out C (a) * V s V n V out C Aroximated (b) R * V s +V n V out C Figure 5. The aroximations to a cmos inverter (a) when thermal noise is couled to inverter s outut (b) when thermal noise is couled to inverter s inut ass) filtering imact of the RC network on the noise. We assume that the noise is samled at the beginning of the switching and held at the samled value during switching; and the samling eriod of the noise is larger than T s. Hence, in the case of inut-couled noise, an error that occurs at the inut of the inverter roagates to the outut of the inverter. In addition, we assume that V out is samled at the same eriod as the noise is samled. We refer to the samling eriod of the noise as t sn, and the samling eriod of V out as t so. These assumtions on t sn and t so are valid throughout the current section. Later, in Section 8, we will revisit this toic, and study the filtering imact of the RC network as well as the imact of varying t sn and t so on the robabilistic behavior of the inverter. In this aer, to model the thermal noise and ower suly noise, resectively, by following the aroach of [5] and [0], we assume that our noise sources are random rocesses that are characterized by Gaussian distribution with standard deviation σ. We refer to σ as the root mean square (rms) value of the noise. The noisy outut (inut) voltage V out (V in ) is reresented as two Gaussian curves each of which has a standard deviation of σ as shown Figure 6. More secifically, when the binary value of the outut (inut) is 1 (corresonding to the curve on the right), the mean value of the outut (inut) voltage is Volts, whereas when the binary value of the outut (inut) is 0, corresonding to the curve on the left, the mean value of the outut (inut) voltage is 0 Volt. The robability of the outut (inut) digital value 0 being treated as 1 is reresented by the shaded area under the two Gaussian curves. Similarly, the robability of the outut (inut) digital value 1 being treated as 0 is reresented by the unshaded area under the two Gaussian curves. In the case of outut-couled noise, the robability of 1 being treated as 0 (e 10 ) and robability of 0 being treated as 1 (e 01 ) are described by e 10 = V m ( ) 1 ex (x ) πσ σ dx (6)

8 8 CREST Technical Reort, No. TR , Aug 005 Probability density Digital 0 Digital 1 σ σ 0 V m Voltage Probability of 1 being treated as 0 = Probability of 0 being treated as 1 e 10 e 01 Figure 6. The digital values 0 and 1 reresented by the two Gaussian curves e 01 = V m ( 1 ex πσ x σ ) dx (7) On the other hand, when the thermal noise is inut-couled, e 10 is reresented by (7) and e 01 is reresented by (6) since the errors e 10 and e 01 are associated with the outut voltage, which is identical to the inverse of the inut voltage. The robability of being correct () is equal to the average value of robability of being correct for the switchings from 1 to 0 and 0 to 1 and described by = 1 e 01 + e 10 (8) Relacing the integrations of (6) and (7) into (8) yields the following relationshi between and, wherein is the robability of being correct for a cmos inverter that is either inut- or outut-couled with thermal noise with an rms value of σ. = ( ) 4 erf Vm + 1 ( ) σ 4 erf Vdd V m σ In (9) erf is the error function defined as erf(x) = / x π e u du for a real number x. V m, as stated before, is the midoint voltage of the inverter, and exressed as follows: V m = 0 µ V T + n µ (W/L) n (W/L) V T n (10) µ 1 + n µ (W/L) n (W/L) Here, V T and V T n are the threshold voltages of the PMOS and NMOS transistors in that order; µ n and µ are the average mobility of electrons and holes resectively, and (W/L) n /(W/L) is the ratio of the asect ratio of the NMOS transistor to the asect ratio of the PMOS transistor [7]. (9)

9 9 CREST Technical Reort, No. TR , Aug 005 * V * V V in V out C V in V n * V out C CMOS gate (a) CMOS gate (b) Figure 7. Coulings of the ower suly noise to the cmos (inverter) gate: (a)power suly noise only (b) Power suly noise in conjuction with outut-couled thermal noise V * n Aroximated V * n V in V out C 1 V in R V out C Figure 8. The aroximation to a cmos inverter couled with ower suly noise 5. Analytical Modeling of the Probability Parameter () of a cmos Inverter with Power Suly Noise Couling In this section, we develo an analytical model characterizing the robabilistic behavior of a cmos inverter. We assume that the ower suly voltage has a Gaussian distribution with an rms value in the order of a few hundred milivolts. This assumtion is based on the stochastic modeling of ower suly noise resented in [0], where it is concluded that ower suly noise can be modeled as a random signal with a Gaussian distribution, esecially for large chis having large number of cells/blocks. In the sequel, we refer to the rms value of ower suly noise as σ. Our analytical model considers two cases of ower suly noise couling. In the first case, the ower suly noise, denoted as V, is the only noise source couled to the inverter as shown in Figure 7(a). Figure 7(b), on the other hand, illustrates the second case where the ower suly noise, is couled to the inverter in conjuction with the outut-couled (thermal) noise source, denoted as V n Analytical Modeling of the Probability Parameter () of a cmos Inverter Couled with Only Power Suly Noise. In the case that the cmos inverter is couled with only the ower suly noise (as shown in Figure 7(a)), the aroximation illustrated in Figure 8 is utilized to simlify the analysis. Similar to the case of inverter couled with thermal noise, the inverter is aroximated as an ideal switch. Referring to Figure 8, if the ower suly noise is not resent, and when V in =, the ideal switch will

10 10 CREST Technical Reort, No. TR , Aug 005 be in osition 1, that is, the NMOS transistor will be on and the PMOS transistor will be off. Similarly, if the ower suly noise is not resent, and V in = 0, the ideal switch will be in osition, that is the PMOS transistor will be on, and the NMOS transistor will be off. However, due to the ower suly noise, the PMOS transistor may become on, even in the case that V in = and it may become off, even in the case that V in = 0. In the case that V in = 0, the gate to source voltage (V gs ) of the PMOS transistor is V gs = V g V s = 0 ( + V ) = V Since V gs is a linear combination of the inut signal V g (constant) and the random signal V, V gs is also a random signal having a Gaussian distribution with an rms value of σ [1]. If V gs dros below the threshold voltage of the PMOS transistor ( V T ), the PMOS transistor becomes off causing the outut node to become a high imedance node. In this case, the outut node may have a binary value of 0 or 1. We assume that the robability of the outut voltage (V out ) being 0 or 1 is 1 for both cases. The robability of V gs being smaller than V T can be found using (1). ( ) P r ( V gs < V T ) = 1 1 erf V T σ If V gs is greater than ( V T ), then the ideal switch in Figure 8 is in osition, and the noise source V will constitute an offset on. V out is described with the Gaussian distribution (corresonding to the curve on the right in Figure 6), where the rms value of the Gaussian distribution is σ. Thus, for an inverter couled only with ower suly noise, in the case that V in = 0, the robability of error (the robability of 1 being interreted as 0) is described by e 10 = P r( V gs V T ) ( ( )) 1 1 erf V m + P r( V gs < V T ) 1 σ Referring to Figure 8, in the case that V in =, the gate to source voltage (V gs ) of the PMOS transistor is described by V gs = V g V s = ( + V ) = V The PMOS transistor may become on, that is the ideal switch in Figure 8 might erroneously switch to osition, if V gs is greater than the threshold voltage ( V T ) of the PMOS transistor. However, not every value of V gs can cause an incorrect transition at the outut from binary 0 to 1. We refer to the value of V gs above which we observe incorrect transitions at the outut as V m (a ositive real number). Below, we will derive V m using Schichman-Hodges MOSFET model [7]. Referring to Figure 9, which shows the inut and outut voltages of an inverter with an additional DC voltage of V gs on its ower suly, in the case V in =, and V out =, the gate to source and drain to source voltages of the PMOS and NMOS transistors, V gs, V ds, V gsn and V dsn, resectively, are described below by equations 15 and 16. (11) (1) (13) (14) V gs = V V ds = V V gsn = V dsn = (15) (16)

11 11 CREST Technical Reort, No. TR , Aug 005 V gs V in = V out = C Figure 9. The inut and outut voltages of the inverter in the case that there is a DC voltage of V gs on the ower suly line Using Schichman-Hodges MOSFET model, the drain currents of the PMOS and NMOS transistors are described by ( I d = µ W ( L I dn = µ W ) n L Solving for V m in I d = I dn, we find that ) C ox (Vm V T ) n C ( 3 ox 4 V ) dd V Vdd T n (17) V m = (µn /µ ) ( W L ( W L ) ) n ( 3Vdd 4 V T n ) + V T (18) Using equation (18) and through HSice simulations, we have found that V m is aroximately equal to. Using (14), we find that the following condition for V should hold in order that an error occurs at the outut V V m (19) Hence, the robability of an error occurring at the outut due to ower suly noise in the case of the inverter inut being is identical to the robability of V being greater than V m, wherein V is a random variable with a Gaussian distribution of rms value σ. Thus, the robability of an erroneous switching from 0 to 1 (e 01 ) at the outut of the cmos inverter is e 01 = 1 1 erf ( ) V m σ (0) Hence, from (0), (13) and (8) the robability of being correct in the case of ower suly noise couling becomes = erf ( ) V m σ ( ) ( ) ( ) erf V m + 1 σ 8 erf V m V m erf σ σ (1)

12 1 CREST Technical Reort, No. TR , Aug 005 V * n Aroximated V * n V in C V in R V out 1 V * V * n n V out C Figure 10. The aroximation for a cmos inverter with ower suly noise couled to its ower suly line and thermal noise couled to its outut 5.. Analytical Modeling of the Probability Parameter () of a cmos Inverter Couled with Power Suly Noise lus Thermal Noise. In this section, we consider a cmos inverter whose robabilistic behavior is induced by ower suly noise couled to its ower suly line and thermal noise couled to its outut. The cmos inverter is relaced by the simlified model shown in Figure 10 to derive the analytical model. Similar to the case of the inverter being couled only with ower suly noise, we consider the cases of V in = 0 or V in =. Referring to Figure 10, in the case that V in = 0, V gs is described by (11). As exlained in Section 5..1, V gs is a random variable having a Gaussian distribution with an rms value of σ. If V gs dros below V T, the PMOS transistor becomes off, and the outut node becomes a high imedance node. We assume that the binary value of V out is 0 or 1 with robability 1. The robability of V gs being smaller than V T was described by (1). In the case of V in = 0 and V gs > V T, the ideal switch in Figure 10 will be in osition, and the noise sources V and Vn will be additive, leading to an equivalent noise with a Gaussian distribution [13]. We note that the ower suly and thermal noise sources are derived from statistically indeendent Gaussian rocesses. The rms value of this equivalent noise is denoted by σ a and calculated as follows σ a = σ + σ () Thus, for an inverter couled with ower suly noise in conjuction with the outut-couled thermal noise, when V in = 0, the robability of 1 being treated as 0 (e 10 ) is described by ( 1 e 10 = P r( V gs V T ) 1 ( )) erf Vm + P r( V gs < V T ) 1 σa Referring to Figure 10, in the case when V in =, the PMOS transistor may become on because of the ower suly noise. In Section 5..1 we derived V m, the value of V gs above which we observe incorrect transitions at the outut when V in =. The robability of the PMOS transistor becoming on to roagate the errors due to the ower suly noise to the outut is described by P r( V gs V m ) = 1 1 erf ( ) V m σ In the case when V gs < V m, we assume that the only noise source affecting the outut is the thermal noise source. In the case when V gs > V m, the noise sources V and Vn are additive leading to an equivalent (3) (4)

13 13 CREST Technical Reort, No. TR , Aug 005 Gaussian noise source with rms value of σ a (described by ()). Then, the robability of an incorrect switching from 0 to 1 (e 01 ) is described as follows ( 1 e 01 = P r( V gs < V m ) 1 ( )) ( erf Vm 1 + P r( V gs V m ) σ 1 ( )) erf Vm σa Using (5), (3) and (8) the robability of being correct for a cmos inverter with ower suly noise couled to its ower suly line lus the thermal noise source couled to its outut becomes ( ) ( ) ( ) ( ) ( ) = erf σ Vm erf Vm σa erf Vdd σa V m erf Vm σ erf σ Vm ( ) ( ) ( ) ( ) 1 8 erf Vm σ erf Vm σa erf Vm σ erf Vdd (6) σa V m 5.3 Analytical Modeling of the E- Relationshi of a cmos Inverter In the revious two sections, we rovided analytical models characterizing the robability arameter () of a cmos inverter couled with thermal noise and/or ower suly noise. In this section, we will first rovide analytical models characterizing the (dynamic) energy consumed er one switching ste (E) of cmos inverter. Following this, we will deict the relationshi between and E Modeling the Energy Consumed by a cmos Inverter er Switching. The main comonents of dynamic energy consumtion of a digital circuit are switching energy consumtion (E sw ) and short-circuit energy consumtion (E sc ). We model the switching energy consumtion using (5) E sw = 1 CV dd (7) which describes the energy consumed to charge (from 0 to ) or discharge (from to 0) a caacitive load C. The energy consumtion of each aroximated circuit in Figures 5, 8 and 10 is described by (7). In this section, we will consider only the switching energy consumtion (E E sw ) and will use (7) to derive the E- relationshi of a cmos inverter. However, the short-circuit energy consumtion of the inverter can constitute u to 0% of dynamic energy consumtion of the inverter [1] and should also be taken into account in the analytical model. In Section 7, we will resent an imroved analytical model characterizing the E- relationshi, wherein the short-circuit energy consumtion of the cmos inverter is also accounted for in modeling E E- Relationshi for a cmos Inverter. In this section, we first resent a generalized form of the E- relationshi. Following this, we rovide the E- relationshi of a cmos inverter that is symmetric and couled with thermal noise. It is evident from (9), (1) and (6) that is a function of. It is also seen that this function is deendent on the tye of the noise couling. We denote this function by h i, where i is an arbitrary integer associated with the tye of couling. For examle, if we choose i to be 1 in the case that thermal noise is couled to the inut and i to be in the case of outut-couled thermal noise, then = h 1 ( ) = h ( ) and h 1 ( ) is h 1 ( ) = ( ) 4 erf Vm + 1 ( ) σ 4 erf Vdd V m σ (8) where V m is described by (10). From (7), the generalized E- relationshi is described as follows

14 14 CREST Technical Reort, No. TR , Aug 005 E = 1 C [ h 1 i () ] (9) where h 1 i (x) denotes the inverse of the function h i (x). If the transistors of the inverter are symmetrical (with equal threshold voltages, and satisfying the condition (µ n /µ ) = (W/L) / (W/L) n ), then the following equations describe the E- relationshi for two instances of couling: In the instance that thermal noise is couled to the inut or to the outut of a symmetric inverter, E- relationshi is E = 4Cσ [inverf ( 1)] (30) where inverf is the inverse of the error function [6]. The exression in (30) shows that E increases with and this increase in E is aroximately exonential in, since inverf (x) function can be exressed as a series summation of owers of x [6] (similar to ex(x )). Similarly, with an increasing rms value of noise for a fixed robability value, the energy consumed to roduce a bit increases. The increase in E is quadratic with resect to the increase in rms value of noise. 6. VALIDATION OF THE ANALYTICAL RESULTS To validate our analytical results, we erformed circuit simulations in HSice for cmos inverters realized in ami 0.5µm and tsmc 0.5µm rocesses. Table 1 summarizes the simulation arameters. As seen in the table, the arameters that are varied are the suly voltage ( ), rms value of the thermal noise (σ n ), and rms value of the ower suly noise (σ ). The load caacitance value (C) corresonds to a load due to a fanout of four (which is a tyical load value), leading to a value of 60fF and 8fF for ami 0.5µm and tsmc 0.5µm, resectively. In this section, we rimarily resent the analytical and simulation results for a cmos inverter realized in tsmc 0.5µm rocess. The results for an inverter realized in ami 0.5µm rocess show similar trends. Table 1. Simulation Parameters Technology ami 0.5µm tsmc 0.5µm Inverter fan-out 4 4 Load caacitance 60fF 8fF Nominal Vdd (V) 5.5 Transistor size (W/L) mos 15u/0.6u u/0.3u (W/L) nmos 6u/0.6u 0.8u/0.3u Vdd (V) σ (V) σ (V) Inut rise and fall time 0.ns 0.ns In our simulations, noise is inserted into the HSice netlists in the form of a PWL (PieceWise Linear) voltage source. The data oints of the PWL source are from a Gaussian distribution of random numbers generated by Matlab. In Figure 11, we show the rise and fall times of the noise ulse. As shown in the figure, t nr denotes the rise time of the noise ulse, t nf denotes the fall time of the noise ulse, and they are identical to each other (t nr = t nf ), and t nc denotes the length of the time during which the noise voltage level is ket constant. In addition, t sn denotes samling eriod of the noise, and is equal to the sum of the t nf (or t nr ) and t nc. In Section 5.1, we stated that noise is samled at the beginning of the switching, and held at the samled value during switching. Furthermore, the samling eriod of the noise is larger than the switching time (T s )

15 15 CREST Technical Reort, No. TR , Aug 005 Voltage t sn Time t nr t nf t nc Figure 11. The noise ulse and its rise and fall times of the inverter. We refer to this method of samling and holding the noise voltage as the noise voltage being latched. On the other hand, in the tyical way of generating a noise source for transient resonse circuit simulations [5], referring to Figure 11, t nc is identical to zero. We refer to this method of generating noise as the noise being non-latched. In this section, our results are based on the case that noise is latched. In Section 8, we will consider the case that noise is non-latched, and we will illustrate the imact of not latching the noise on the robabilistic behavior of the cmos inverter. We note that latching the noise is not the same as the digital latching. In this section, the eriod with which V out is samled, denoted t so, is equal to the noise samling eriod, t sn. In simulations, is found by calculating the ratio of the number of the correct simulation oints to the ratio of the total number of simulation oints. The correctness is identified by comaring the simulation results (for V out ) in the case when there is noise couling to the case when there is not any noise couling. Moreover, E is determined through measuring the total current drawn from the suly voltage of the inverter when the inut of the inverter is connected to a ulse signal. The last row of Table 1 shows the value of the rise and fall times of the inut ulse. Note that, an inverter also consumes short-circuit energy during a switching. In the simulations, since the total current drawn from the suly voltage is measured, the resulting energy consumtion also includes the short-circuit energy consumtion. We also note that we only measure the energy consumed by a cmos inverter during one switching ste, that is, when its outut changes (switches) from 0 to or vice versa. Later in Section 9, we will show the imact of the surious switchings resulting from noise on the energy consumtion of a cmos inverter. Below, we first resent the analytical and simulation results for the E- relationshi of a cmos inverter that is couled with thermal noise at its inut or outut. Following this, we comare the analytical and simulation results for the E- relationshi of a cmos inverter couled with ower suly noise. Then, we deict the analytical and simulation results for the E- relationshi of a cmos inverter couled with ower suly noise and thermal noise. 6.1 E- Relationshi for a cmos Inverter Couled with Thermal Noise In Figure 1, we deict the E- relationshi of cmos inverters realized using a tsmc 0.5µm and an ami 0.5µm technology, and couled with thermal noise at their oututs or inuts. The figure shows the E- relationshi estimated using HSice simulations as well as the E- relationshi resulting from the analytical

16 16 CREST Technical Reort, No. TR , Aug 005 energy er switching ste (Joules) 4.0E E-13.0E E-13 TSMC 0.5µm sim-outut-rms = 0.8V sim-inut-rms = 0.8V analytical-rms=0.8v sim-outut-rms = 0.4V sim-inut-rms = 0.4V analytical-rms=0.4v sim-outut-rms = 0.V sim-inut-rms = 0.V analytical-rms=0.v 0.0E energy er switching ste (Joules) 1.6E-1 1.E-1 8E-13 4E-13 0 AMI 0.5µm sim-outut-rms=0.8v sim-inut-rms=0.8v analytical-rms=0.8v sim-outut-rms=0.4v sim-inut-rms=0.4v analytical-rms=0.4v sim-outut-rms=0.v sim-inut-rms=0.v analytical-rms=0.v Figure 1. E- relationshi for an inverter with thermal noise couled to its inut or outut sim-inut-rms=0.v sim-outut-rms=0.v analytical-rms=0.v sim-inut-rms=0.4v sim-outut-rms=0.4v analytical-rms=0.4v sim-inut-rms=0.8v sim-outut-rms=0.8v analytical-rms=0.8v Vdd(Volts) sim-inut-rms=0. sim-outut-rms=0. analytical-rms=0. sim-inut-rms=0.4 sim-outut-rms=0.4 analytical-rms=0.4 sim-inut-rms=0.8 sim-outut-rms=0.8 analytical-rms= Vdd (Volts) Figure 13. The change in with resect to of a cmos inverter couled with thermal noise at its inut or outut model. The two arameters that we vary are the noise rms value, σ, and the oerating suly voltage,. In articular, for each value of rms value of noise, we calculate at different values of through the analytical model (described by (9)), and through circuit simulations in HSice. In the figure, sim-outut-rms denotes the simulation results in the case of the outut-couled thermal noise. Similarly, sim-inut-rms denotes the simulation results in the case of inut-couled thermal noise. We estimate the energy consumed er switching of a cmos inverter using the analytical model (described by (7)) as well as through the circuit simulations. As shown in Figure 1, given a fixed amount of available noise, the energy needed to roduce a single bit increases with. Furthermore, with increasing rms for a fixed robability value, the energy consumed to roduce a bit increases. Analytical and simulation results agree in terms of these two trends observed for the energy consumed er switching. In addition, it is seen in Figure 1 that the simulation results for the cases of inut- and outut-couled noise are very close to each other, showing the validity of the analytical model described by (9). We note that our analytical model for instances of outut-couled and inut-couled noise are the same. As seen in Figure 1, the difference between the results of the analytical model and the simulations is negligible. Since our analytical model consists of two asects, the first modeling and the second modeling E, we also investigate the accuracy of these two comonents of the analytical model searately. In Figure 13, we deict versus at different values of noise rms value. Figure 13 shows that analytical and simulation results for follow each other very closely (the difference is 1.04% in the average). Figure 14 shows the energy estimation results of the analytical model and the simulations with resect to. The difference between the

17 17 CREST Technical Reort, No. TR , Aug 005 energy er switching ste (Joules) 1.5E-1 1E-1 7.5E-13 5E-13.5E-13 analytical simulation Vdd(Volts) energy er switching ste (Joules) 4.0E E-13.0E E E+00 analytical simulation Vdd(Volts) Figure 14. Energy results for the analytical model and the simulations energy er switching ste (Joules) 1.0E E E E-14.0E-14 simle-model-rms=0.8 analytical-model-rms=0.8 simle-model-rms=0.4 analytical-model-rms=0.4 simle-model-rms=0. analytical-model-rms=0. 0.0E Figure 15. Comarison of the simle analytical model (30) with the analytical model described by (9) results of the analytical model and simulations is.8% in the average. Hence, our analytical model roduces reasonably accurate estimates for as well as E. Figure 13 also shows that for a cmos inverter couled with thermal noise at its inut, and for noise rms values of 0.V and 0.4V, the deviation of the analytically found from the found through simulations increases as decreases. For examle, for the 0.5µm inverter, when the rms value of noise is 0.V, the deviation becomes noticeable at = 0.7V and increases as decreases below 0.7V. This trend results due to the fact that, as decreases, the roagation delay of the cmos inverter increases resulting in the noise being low-ass filtered. We will revisit this issue in Section 8, where we discuss the imact of the equivalent noise bandwidth and the roagation delay of the inverter gate on the robabilistic behavior of a cmos inverter. In Section 5.3., we resented a simle exression modeling the E- relationshi of a symmetric inverter in (30). In Figure 15, we rovide a comarison of the E- relationshi (for a tsmc 0.5µm inverter) obtained using (30) with the E- relationshi obtained using (9) at different values of noise rms. In the figure, simle-model refers to the analytical model described by (30). The figure shows that the simle analytical model agrees very closely with the analytical model described by (9). The reason for the strong agreement between the two models is because that our tsmc 0.5µm inverter has a midoint voltage, V m, that is very close to /.

18 18 CREST Technical Reort, No. TR , Aug 005 Energy er switching ste (Joules) 1.4E-13 1.E-13 1E-13 8E-14 6E-14 4E-14 E-14 0 simulation-rms=0.6v analytical-rms=0.6v simulation-rms=0.4v analytical-rms=0.4v simulation-rms=0.v analytical-rms=0.v Figure 16. The E- relationshi in case of ower suly noise couling Energy er switching ste (Joules) 1.4E-13 1.E-13 1E-13 8E-14 6E-14 4E-14 E-14 thermal-rms=0.6v s-rms=0.6v thermal-rms=0.4v s-rms=0.4v thermal-rms=0.v s-rms=0.v A B E- curve in the case of the thermal noise is shifted to the left Figure 17. The comarison of the E- relationshis in the instances of ower suly noise couling and outut couling of thermal noise 6. E- Relationshi for a cmos Inverter Couled with Power Suly Noise Figure 16 shows the E- relationshi of a cmos inverter couled only with the ower suly noise. We vary the suly voltage of the inverter and the rms value of the ower suly noise couled to the inverter. Similar to the case of the thermal noise couled to the inut or the outut of the cmos inverter, given a fixed amount of available noise, the energy needed to roduce a single bit increases with. In addition, with increasing rms value of noise for a fixed robability value, the energy consumed to roduce a bit is increasing. As seen in

19 19 CREST Technical Reort, No. TR , Aug 005 energy consumed er switching ste (joules) 1.4E-13 1.E E E E E-14.0E E+00 sim-srms=0.4-rms=0.4 analytical-srms=0.4-rms=0.4 sim-srms=0.-rms=0.4 analytical-srms=0.-rms=0.4 sim-srms=0.4-rms=0. analytical-srms=0.4-rms=0. sim-srms=0.-rms=0. analytical-srms=0.-rms= E- curve is shifted to the left as RMS value of ower suly noise increases Figure 18. The E- relationshi for a cmos inverter with ower suly noise couled to its ower suly line and thermal noise couled to its outut the figure, the difference between the results of the analytical model and the simulations is negligible. Figure 17 shows a comarison of the E- relationshis of a cmos inverter in the instances of outut-couled thermal noise and ower suly noise couling. In the figure, thermal-rms denotes the rms value of the thermal noise, and s-rms denotes the rms value of the ower suly noise. The figure deicts that at a fixed value of E, outut-couled thermal noise induces a lower value of when comared to ower suly noise with the same magnitude. Hence, outut-couled thermal noise is more effective in generating a secific value of, that is the required noise rms value in the case of the outut-couled thermal noise is smaller. The higher value of in the instance of the ower suly noise couling results due to the fact that ower suly noise induces less errors when the inut voltage of the inverter is. 6.3 E- Relationshi for a cmos Inverter Couled with Power Suly Noise lus Thermal Noise Figure 18 shows the E- relationshi for a cmos inverter in the instance that it is couled with ower suly noise at its ower suly line and thermal noise at its outut. In the figure, both the rms value of thermal noise and the rms value of ower suly noise are varied. Similar to the three revious couling instances, given a fixed amount of available noise, the energy needed to roduce a single bit increases with. In addition, with increasing noise rms value for a fixed robability value, the energy consumed to roduce a bit increases. In Figure 18, from left to right, the first four curves reresent the E- relationshi of an inverter couled with ower suly noise in conjuction with outut-couled thermal noise, wherein the rms value of thermal noise is 0.4V. In the case of the next four curves in the figure, the rms value of thermal noise is 0.V. These curves deict that the E- curve is shifted to the left as the rms value of ower suly noise increases. However, the imact of varying the rms value of the ower suly noise becomes less significant as the rms value of the outut-couled thermal noise increases. For examle, when the rms value of thermal noise is 0.V, increasing the rms value of ower suly noise from 0.V to 0.4V shifts the E- curve through the distance shown by the black arrow, whereas when the rms value of thermal noise is 0.4V, the E- curve is shifted by a smaller distance shown by the gray arrow. This trend occurs because the roortion of ower suly noise decreases as the rms value of thermal noise increases. Figure 19 shows the E- relationshi of a cmos inverter couled with thermal noise of varying rms values

20 0 CREST Technical Reort, No. TR , Aug 005 Energy er switching ste (joules) 1.6E-13 1.E E E E+00 srms=0.4-rms=0.8 thermal-rms=0.8 srms=0.4-rms=0.4 thermal-rms=0.4 srms=0.4-rms=0. thermal-rms=0. E- curve is shifted to the left Figure 19. Comarison of E- relationshis for a cmos inverter for two cases: (1) inverter is couled with ower suly noise and thermal noise, () inverter is couled with only thermal noise (0.V, 0.4V, and 0.8V) at its outut and ower suly noise with rms value of 0.4V. In addition, the figure deicts the E- relationshi of the same cmos inverter when it is couled only with thermal noise. The figure shows that when ower suly noise is couled in addition to the thermal noise, the E- curve is shifted to the left. We also observe that, the distance by which the E- curve is shifted to the left increases as the rms value of the thermal noise decreases. This results from the increasing effect of the ower suly noise on. 6.4 Summary of the Results In this section, we have validated our analytical models for the E- relationshi in four cases of noise couling: (1) thermal noise couled at the inut () thermal noise couled at the outut (3) ower suly noise (4) ower suly noise in conjuction with the thermal noise couled at the outut. We have found that given a fixed amount of available noise, the energy needed to roduce a single bit increases with. The analytical model and simulation results have shown that this increase is aroximately exonential. We also observed that with increasing rms for a fixed robability value, the energy consumed to roduce a bit increases. Our analytical results and simulation results have deicted that the increase in E with increasing rms is quadratic. We have observed that our analytical models roduce accurate results for all of the four instances of couling. However, in the case of the inut-couled noise, we have observed that the analytically calculated value of is smaller than the value of found through simulations at low values of the suly voltage. The difference between the two occurs due to the increased roagation delay of the inverter at low values of. We will revisit this issue in Section 8. In our analytical models, we have only considered the switching energy comonent of the energy consumtion of the inverter. In Section 7, we will consider the short-circuit energy consumtion, since the short-circuit energy consumtion can constitute uto 0% of the dynamic energy consumtion [1].