A PROBABILISTIC POWER ESTIMATION METHOD FOR COMBINATIONAL CIRCUITS UNDER REAL GATE DELAY MODEL

Transcription

1 A PROBABILISTIC POWER ESTIMATION METHOD FOR COMBINATIONAL CIRCUITS UNDER REAL GATE DELAY MODEL G. Theodoridis, S. Theoharis, D. Soudris*, C. Goutis VLSI Design Lab, Det. of Electrical and Comuter Eng. University of Patras, 60, Greece *VLSI Design and Testing Center, Det. of Electrical and Comuter Eng. Democritus University of Thrace, 6700 Xanthi, Greece ABSTRACT Our aim is the develoment of a novel robabilistic method to estimate the ower consumtion of a combinational circuit under real gate delay model handling temoral, structural and inut attern deendencies. The chosen gate delay model allows handling both the functional and surious transitions. It is roved that the switching activity evaluation roblem assuming real gate delay model is reduced to the zero delay switching activity evaluation roblem at secific time instances. A modified Boolean function, which describes the logic behavior of a signal at any time instance, including time arameter is introduced. Moreover, a mathematical model based on Markov stochastic rocesses, which describes the temoral and satial correlation in terms of the associated zero delay based arameters is resented. Based on the mathematical model and considering the modified Boolean function, a new algorithm to evaluate the switching activity at secific time instances using Ordering Binary Decision Diagrams (OBBDs) is also resented. Comarative study of benchmark circuits demonstrates the accuracy and efficiency of the roosed method. Inde Terms. Low Power Design, Switching Activity Estimation, Power Dissiation Model, Markov Chains, Temoral and Satial Correlation, CMOS Combinational Circuits.

2 . INTRODUCTION Power dissiation is recognized as a critical arameter in modern VLSI design field. The develoment of cometitive market sectors such as wireless alications, latos, and ortable medical devices, deend on the ower consumtion as the most imortant arameter, because the growth rate of the battery technologies is not so romising. In addition, roblems such as chi overheating, electomigration and hot electrons are strongly-deended on ower dissiation [, ]. For these reasons low ower design techniques at all levels of the design flow ranging from the layout level u to architectural and system level have been develoed [,]. However, an estimation of the ower consumtion at any design level, is required. Thus simultaneously with low ower design techniques a large number of ower estimation methods have been also develoed [,3]. The ower dissiation at gate level is roortional to the switching activity of the circuit nodes, because in the current technologies the dynamic ower dissiation is by far the most dominated factor comaring with the ower consumtion coming from the short circuit and leakage current. According to their mathematical model, the ower estimation methods of the combinational circuits are categorized as robabilistic methods and statistical ones. Moreover, considering the assumed gate delay model they are also characterized as zero- and real-gate delay methods. A survey of the ower estimation methods for combinational logic circuits has been reorted in [, 3]. Assuming zero-gate delay model [4, 5] and real gate delay model [6,7,8,9], a number of robabilistic ower estimation methods have been resented. In articular, a method for calculating the switching activity of the circuit nodes, using Order Binary Decision Diagrams (OBBDs) was roosed [4]. Modeling the behavior of the logic signal as an one ste Markovian rocess the first order temoral correlation was catured. Moreover, structural correlation, which

3 is coming from the reconvergent fanout nodes, was also considered by artitioning the circuit using techniques from the chi testing field. However, the inut signals were assumed to be mutually-indeendent, making this method inaccurate for highly correlated inut streams. In [5], a robabilistic method, which catures all the tyes of correlations was resented. Secifically, modeling the logic signal as a Markovian rocess, the temoral correlation was considered, while the inut attern deendency was also catured by the concets of the satiotemoral transition correlation coefficient and the signal isotroy. Using OBDDs, the structural correlation was considered by roagating the estimated switching activities and satiotemoral coefficients through the circuit nodes. In [6], the concet of the robability waveforms to estimate the average ower dissiation was resented. The robability waveforms consist of the signal robability and the signal transition robability value. Given the robability waveforms of the rimary inuts, an algorithm to estimate the robability waveforms of the internal nodes of the circuit has been introduced. However, both the structural and inut deendencies were not taken into consideration. An etension of the robability waveforms is the tagged robabilistic simulation aroach resented in [7]. In articularly, at each node the transition robability is broken in four cases: stable to 0, stable to, erform a low to high transition ( 0 ) and a high to low ( 0 ) transition. Inertial delays, hazards, temoral correlation of the rimary inuts and structural correlations were considered by this method. However, the rimary inuts were assumed satially uncorellated, while simultaneous transitions were not considered. In [8], a symbolic simulation algorithm has been roosed using OBDDs. The structural and the first-order temoral correlation were handled but the inut attern deendency was not considered. A new method for calculating the transition robabilities by erforming symbolic olynomial simulation was roosed in [9]. It is based on the signal robability evaluation method of [], which has been etended to handle temoral correlation and arbitrary transort gate delay models. The

4 method was arameterized by a single factor, which determines the circuit levels over which the structural correlation is considered. A roagation algorithm of the estimated switching activities through the circuit nodes has also been resented. However, the inut signals were also considered mutually-indeendent making this method inaccurate. In this aer a novel robabilistic method for accurate ower estimation of a combinatorial circuit is introduced. Taking into account the temoral, structural and inut attern deendency of the circuit signals and considering simultaneous transitions, the switching activity of any logic circuit node is calculated under a real delay gate model. Since the roosed method includes all the tyes of data correlations, it can be considered as an etension of the aroach of [5]. Although the [5] can cature all the tyes of correlations, is valid only for zero delay model. In contrast, the roosed method derives accurate results because it catures all the ossible signal transitions, i.e. the functional transition and the surious transitions (or glitches). It is roved that under a roer formulation, the switching activity estimation roblem assuming real gate delay model can be transformed to a zero delay switching activity estimation roblem at secific time instances. For this reason a new Boolean function including time arameter and a roer mathematical model are established. The concets of transition robability and satiotemoral correlation coefficient, which are derived from the zero delay switching activity estimation field, are etended to estimate the switching activity under real delay model. Also, it is roved that the transition robabilities and transition correlation coefficients of the rimary inuts at any time interval can be evaluated by the zero delay transition robabilities and transition correlation coefficients. Moreover, a method for the switching activity evaluation of circuit nodes in different time instances using OBDDs is also introduced. Emloying a set of benchmark circuits, comarisons with a switch level simulation and the method of [9] rove the efficiency of the roosed method.

5 The aer is organized, as follows: in Section the roblem formulation is resented, the mathematical model is introduced in Section 3, while the switching activity evaluation algorithm is given in Section 4. The eerimental results are resented in Section 5 while the conclusions and future work are discussed in Section 6.. PROBLEM FORMULATION. The ower estimation roblem of a combinational logic circuit, under real gate delay model can be stated as: Given the gate level descrition of a combinational circuit with N inuts and M oututs and the inertial delays of its gates, and, assuming that the eriod of the alied inut vectors is greater or equal to the settling time of the circuit, estimate the average ower consumtion of the circuit for an inut vector stream through the calculation of the circuit average switching activity. The accuracy of the switching activity evaluation is strongly deended on the data correlation of the circuit signals and the assumed gate delay model. Concerning data correlation, it includes the temoral and satial correlation. By temoral correlation we mean the deendency of a signal on its revious values. The satial correlation is divided to the structural correlation, which is coming from the reconvergent fanout nodes, and the inut attern deendency coming from the sequence of the alied inut vectors. In zero delay model, a gate erform at most one transition in a clock cycle, which is called functional or useful transition. However, under real delay model the gate may erform additional transitions called surious transitions or glitches. Therefore, all tyes of signals correlations under real delay model have to be considered to estimate the ower dissiation accurately. The outut of a gate generates a glitch, if two conditions are satisfied: i) the necessary condition, which requires the difference of the transition arrival times of the inut signals to be

6 equal or greater than the inertial delay of the gate and ii) the sufficient condition, which requires the aroriate transitions of the inut signal(s) to switch the gate outut. Consequently, the time arameter lays an imortant role in the glitch generation. For that urose, a modified Boolean function including time arameter, which will describe the eact behavior of a logic signal in time domain, is needed. Maniulating this modified logic function and considering the robabilistic roerties of its variables the switching activity can be calculated accurately. Eamle: We assume a logic circuit with gate delay equals to one delay unit, d, as it shown in Figure. The logic behavior of the node f can be described in time domain as follows: f = F(,, t) = ( t d) ( t d) ( t d) Figure () The signal f may switch in two time instances, i.e. t f = d and t f = d. More secifically, the transition of the signal f at t f = d deends on the transitions of the rimary inuts and at time oints = d, = d, and t 0, while the transition of f at t t = t f = d deends on the transitions of the signals and at = t 0, t = 0, and t = d. The corresonding logic functions of f, which are derived by (), of time instances t and t are: f ( = F,, d ) = ( d ) ( d ) (0) and f = F,,d) = (0) (0) ( ), ( d resectively. From the above eamle, we infer that the time arameter lays critical role in the generation of the switching activity. Additionally, the logic behavior of signal f is described entirely by the modified logic function of eq. () at any time instance. The general form of this function is given bellow: f ( t,,,..., ~ ~ ) = f ( ( t k ),..., ( t k )) with k i = d j () n j

7 where, k i is the delay of the ath π i and d j is the delay of the jth gate, is the number of aths, ~ k = i if π k starts at inut i. This function describes the logic behavior of a signal in time domain, while in the secific time instances it is reduced to an ordinary Boolean function, where the Boolean variables are the corresonding logic values of the inut signals of these time oints. Having as starting oint eq. (), a novel mathematical model, which describes the behavior of a logic signal in terms of time should be introduced. We aim at the develoment of a new method, which reduces the ower estimation roblem considering real delay model to a zero delay roblem at certain switching time oints. For that urose, we introduce new concets and formulas, which eress arameters of real delay modeled ower estimation roblem in terms of zero delay arameters. Secifically, we rovide the suitable material for temoral correlation modelling, etending the concet of transition robability for certain time intervals. Then, it follows a set of formally-roven new formulas of the generalised transition correlation coefficients, which describe the satiotemoral correlation among different signals. 3. MATHEMATICAL MODEL. The behavior of a binary signal,, at a time oint, t, i.e. (t), is modelled as a random variable of a time homogeneous, Strict Sense Stationary, lag-one Markov stochastic rocess having two states, s, with S = { 0,} s [0]. The transition robability, kl (t), eresses the robability of a signal to erform a transition from the state k to the state l within two successive time oints t- and t. That is: kl ( t) = ( ( t ) = k ( t) = l) k, l S (3) The switching activity, E (, t), of a signal at time instance t is given by: E(, t) = 0( t) + 0( t) (4)

8 where ( ) (or ( ) ) is the transition robability of the signal to erform the transition from 0 t 0 t state 0 to (or to 0). The above stochastic rocess models the behavior of an inut signal at times t=0, t=t, t=t, e.t.c., where the inut signal erforms a transition. However, as it can be seen in eq. (), the transition robabilities kl (t) of an inut signal at multile time oints t = ± a d ( a =, ) (i.e. (0), ( d kl ), and ( d ) ), are needed. kl kl Definition. A Signal Transition Probability Vector, P (t), of a signal at a time instance t, is defined as the vector of all transition robabilities kl (t), with k, l S : P ( ( t), ( t), ( t), ( ) ) ( t) = t (5) We introduce the transition robability concet of an inut signal in time intervals (-T, 0) kk ( ll + and (0, T) as 0 ) and (0 ), resectively. It should be noticed that within these time intervals the inut signal does not erform transition according to the roblem formulation. Their corresonding values are comuted by the net lemma. + Lemma. The transition robability of an inut signal,, at a time oint { 0,0, 0 } t is eressed in terms of the transition robability at t=0 as follows: P ( t) = f ( P (0)) (6) and are comuted by: ( ) ( 0) + ( 0) k S kk 0 = kk k k ) + ( ) ( 0) + ( 0) l S ll 0 = ll l) l kl kl + ( (6a) ( (6b) ( 0 ) = (0 ) = 0 k, l S k l (6c) Proof. The roof of the above lemma is given in the Aendi I.

9 The above lag-one stochastic rocess and the one ste transition robabilities (eq. (3)) ensure that the first-order temoral correlation of a signal can be described entirely. However, the accurate the ower estimation imlies that the satial correlation among the circuit signals should be considered. Since we use a real delay gate model, the concet of Transition Correlation Coefficient, TC, [5] should be generalised for caturing the satiotemoral correlation of two signals for any two certain time instances. The TC for a zero-delay model is [5]: ( ( t ) = k ( t) = l ( t ) = m ( t) = n) TC, kl, mn = (7) ( ( t ) = k ( t) = l) ( ( t ) = m ( t) = n The deendency among three signals, and 3, is eressed by the airwise coefficients of (6) as follows:,,, 3,, 3, 3 klo, mn kl, mn ko, m lo, n TC = TC TC TC with k, l, m, n, o, { 0,} (8), kl, mn ( Definition. A Generalised Transition Correlation Coefficient, TC t, t ), between the signals and, which erform transitions from the states k to l and from m to n, at times t and t, resectively, is defined as: where k, l, m, n S. ( ( t ) = k ( t) = l ( t ) = m ( t) = n) ( ( t ) = k ( t ) = l) ( ( t ) = m ( t ) = n) TC, kl, mn( t, t) = (9) Since the roosed method is a "global" one, we have to introduce aroriate generalized TCs between any two inut signals, taking into account their satiotemoral deendency. For that urose, three time oints for any inut signal, i.e. (where 0 + / 0 - denotes the time intervals (-T,0) / (0,T)), are needed. + t = 0, t = 0, t = 0, Definition 3. The Transition Probability Coefficient Vector, TC t, t ), between two signals and at time instances t and t is defined as: (

10 ( ),,, ( t, t ) = TC ( t, t ), TC ( t, t )..., TC ( t, ) TC (0), t 00,00 00,0, According to eq. (9), the transition robability coefficients vector at t = 0 and t = 0 the siteen TCs of eq. (7). That is: TC, ( 0,0) = ( TC,..., TC ),, 00,00, contains () Lemma. The satiotemoral correlation coefficients of two inut signals and, at time + oints { 0,0, 0 } t are eressed by:, t and can be calculated by: ( ) ( t, t ) f TC ( 0,0), P ( 0), P ( 0),, TC = () TC TC,,, kk, mn TCkk, mn(0,0) kk(0) + TCk ( k), mn(0,0) ( )(0) k k (0,0) = (a) kk(0) + k( k )(0),,, ll, mn TCll, mn(0,0) ll (0) + TC( l) l, mn(0,0) ( ) (0) + l l (0,0) = (b) ll (0) + ( ) (0) l l TC,, TC (0,0) (0) (0) + ( )(0,0) (0) ( ), kkmm, kk mm TC, kk kkm m m m kkmm, ( 0,0 ) = kk(0) mm(0) + kk (0) + (0) ( )(0) + ( )(0) (0) + ( )(0) ( )(0) mm m m k k k k m m (c) TC,, TC (0,0) (0) (0) ( ) (0,0) (0) ( ), ll, nn ll nn TC, ll ll n n ll, nn ( 0,0 ) = ll (0) nn(0) + ll (0) n n + (0) ( n ) n(0) + ( l ) l(0) nn(0) + ( l ) l(0) ( n ) n(0), TC( ) (0,0) ( ) (0) (0) ( ) ( ) (0,0) ( ) (0) ( ) (0), nn + TC l l nn l l l l, n n l l n n + ll (0) nn(0) + ll (0) ( ) (0) + ( ) (0) (0) ( ) (0) ( ) (0) n n l l nn + l l n n, (d) where k, l, m, n S. Proof. The roof of the above lemma is given in the Aendi I.

11 4. SWITCHING ACTIVITY EVALUATION ALGORITHM Definition 4: We define as Valid Time Points Vector, T = ( t,...,t ) r, all the ossible transition time oints for a signal. These time oints are derived by erforming a traversal of the circuit from the rimary inuts to rimary oututs considering the delay of the gates. Consequently, the switching activity estimation roblem is reduced to the estimation of P ( t) t T. The calculation rocedure of switching activity (i.e. estimation of t ) ) is similar to the zero-delay method to [5] and consists of the following stes: kl ( i a) Construct the OBDD for any time oint ti T, b) Find the sets of all aths of the OBDD that results into the leaf node k, Π, c) Find the sets of all aths of the OBDD that results into the leaf node l, Π and d) Combine any ath of Π k with any ath of the set Π l : k l kl = v i kil i π Π k π Π k i= i< j v TC i, kili j, k jl j (3) 5. EXPERIMENTAL RESULTS The roosed ower estimation method is imlemented by ANSI C language, while its efficiency is roved by a number of ISCAS'85 benchmark multilevel circuits. For technology maing, a library of rimitive gates u to 5 rimary inuts, is used. All ower estimations are measured in ìw with 0 MHz clock frequency and 5 V ower suly. Also, a gate caacitance is assumed to be C g = 0.05 F, while a node with a fan-out F has caacitance F*C g. For comarison reasons, three categories of inut vectors: i) without satial correlation (column NO), ii) with low satial correlation (column LOW) and iii) with high satial correlation (column HIGH), are

12 chosen. For each category and circuit and for reliability reasons, 5 inut vector files of 0000 vectors are generated. These inut vector files are used both for estimation and simulation. For a signal, we define as switching activity error the quantity ' Err( ) = E ( ) E ( ) E ( ), where () is the real switched caacitance of signal eff eff eff E eff and E is the estimated one. For a combinational circuit with L signals and a secific inut ' eff ( ) vector set V j, we define as Total Power Consumtion the quantity L Power ( V j ) = Vdd f Eeff ( i ), as Total Error the quantity i ' Total Error = Power( V Power( V ) Power( V ), as Mean Error the quantity j ) j j L Mean Error ( Vj) = Err( ) N and finally as Maimum Error the quantity i= i { Err( ), Err( ),..., Err( )} Ma Error ( V j ) = ma L. Choosing K inut vector sets the above K formulas become as shown in the following: Power = Power( V j ), Total Error K = K j= K j= K ' Power( V ) Power( V ) Power( V ), which is denoted as TOTAL K, j j j= j K j= MeanError K = K j= Mean Error K, which is denoted as MEAN K, and { Mean Error ( V ),..., Mean Error ( V )} K Ma Error = ma K, which is denoted as MAX K. In our eerimental rocedure K=5. We comare the roosed method and the method [9], which to best of our knowledge is the most accurate real delay ower estimation method, with Mentor's Grahics QUICKSIM II simulator. The ower consumtion differences between each method and switch level simulator are deicted in Table and.

13 Table gives the error in ower estimation (%) of the roosed method. The average TOTAL K error is about 0.0 % for NO satial inut correlation,.4 % for LOW satial correlation, and.5 % for HIGH satial correlation. The corresonding average MEAN K error values are 0.6 %, 3.3 %, and 3.6 %, while the average MAX K errors are.3 %, 5.3 %, and 5.8 %. The inut stream with NO satial is derived by a seudo random generator, the LOW satial is derived by an LFSR and the HIGH satial by the outut of a counter. Table The increased errors for LOW and HIGH satial correlation inut streams coming from the fact that we consider only the first order transition robabilities and the transition correlation coefficient is a airwise coefficient. However, as it is shown in Table, the maimum error is about 5%, while only in one case it eceeds 0%. Hence, the modeling of the switching behavior of a signal by the first order transition robabilities and the modeling of the signals correlation by the first order airwise correlation coefficients are adequate for a gate level ower estimation. In similar manner, we may consider higher order deendencies but the comleity of the roblem is increased. Table shows the ower estimation errors of [9] for the same inut vectors and benchmarks. It can be seen that for NO satial correlation, the error values are small, whereas the average errors of LOW and HIGH satial correlation are large, i.e., 8.5 % and.6 % for TOTAL K ower, 7.5 % and 3.8 % for MEAN K ower, and u to 30 % and 40.7 % for MAX K ower, resectively. The increased errors coming from the fact that the inut attern deendencies are not considered, because the inut signals are assumed mutually indeendent. Table Emloying the roosed method and [9], the associated total ower consumtion of benchmarks circuits is shown in Table 3. It can seen that the lack of satial correlations in the rimary inuts

14 increases the ower estimation error (e.g. for HIGH correlation, the MAX error of circuit CU is 03 %) making the method of [9] inefficient in terms of accuracy for correlated inut streams. 6. CONCLUSIONS Table 3 Assuming a real gate delay model, we have roosed a novel method for the estimation of the ower dissiation of a logic circuit. The method constitutes an etension of the zero delay robabilistic method [5] and takes into account the first-order temoral and the satial correlations. A modified Boolean function, which describes the logic behavior of a signal in time domain, and etension of the basic concets of the zero delay ower estimation models have been introduced. The accuracy of the method has been roved, while the imortance of the inut attern deendencies in terms of accuracy has been shown in the analysis of the eerimental results. Since the roosed method is a global aroach, our future work is to imlement a method that roagates the rimary inut statistics and correlation coefficients through the logic network. Moreover, the roosed method could be etended to cature the ulse filtering and elimination caacitance in a chain of gates by considering a range of inertial gate delays [ d min,d ma ] and taking into account the load caacitance. In addition, the basic concets and the roosed method could be modified to take lace in the ower estimation of the sequential circuits. ACKNOWLEDGEMENTS: This work was artially suorted by LPGD roject ESPRIT IV 556 of Euroean Union. Portions rerinted, with ermission, from Proceedings of 999 IEEE International Symosium on Circuits and Systems (ISCAS), May 30-June, 999, Orlando, Florida, USA,. Vol. I 86-89, 999-IEEE.

15 REFERENCES [] J. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, 996. [] W. Nebel and J. Mermet, Low Power Design in Dee Submicron Electronics, Kluwer Academic Publishers, 997. [3] F. Najm, A Survey of Power Estimation Techniques in VLSI circuits, in IEEE Trans. on VLSI, vol., no 4, , December 995. [4] P. Schneider and U. Schlichmann, Decomosition of Boolean functions for low ower based on a new ower estimation technique, in Proc. of Int. Worksho on Low Power Design,. 3-8, Naa Valley, CA, Aril 994. [5] R. Marculescu, D. Marculescu, and M. Pedram, Efficient Power estimation for highly correlated inut streams, in Proc. of Design Automation Conference (DAC), , 995. [6] F. Najm, R. Burch, P.Yang and I. Hajj Probabilistic Simulation for Reliability Analysis of CMOS VLSI circuits, in IEEE Trans. on CAD, 9 (4) , Ar [7] C-Y. Tsui, M. Pedram, C-A. Chen and A.M Desain, Efficient Estimation of Dynamic Power Dissiation Under a Real Delay Model in Proc. of IEEE Int. Conference on CAD,. 4-8, November 993. [8] J. Monteiro, A. Ghosh, S. Devadas, K. Keutzer, and J. White, Estimation of average switching activity in combinatorial and sequential circuits, in IEEE Trans. on CAD, Vol. 6, No.,. -7, January 997. [9] J.C. Costa, J.C. Monteiro, and S. Devadas, Switching Activity Estimation using Limited Deth Reconvergent Path analysis, in Proc. of Int. Sym. On Low Power Electronics and Design (ISLPED), , Monterey CA, August 8-0, 997.

16 [0] A. Paoulis, Probabilities, Random Variables and Stochastic Processes Mc. Graw-Hill Co., 984. [] K.P.Parker and J.McCluskey, Probabilistic Treatment of General Combinational Networks, IEEE Trans. on Comuters, Vol. C4, , June 975.

17 n f Figure.

18 TOTAL K MEAN K MAX K Circuit NO LOW HIGH NO LOW HIGH NO LOW HIGH c7 0,05 0,63 0,630 0,38,040,580 0,59,704,79 Cm63 0,08 0,95 0,394 0,704 3,9 3,49,98 4,307 4,463 Cm4 0,04 0,35 0,4 0,953,768,90,74 4,4 3,7 Cm8 0,07 3,600 3,603 0,3 5,9 6,009 0,39 0,86,833 cu 0,00 0,07 0,45 0,50,3,63 0,649,58,076 decod 0,00 0,635 0,065,47 4,37 3,74 3,665 7,009 5,66 Majority 0,07 0,765,33 0,349 3,4 4,90,004 4,53 6,5 m 0,00,8 0,866,9 4,93 4,336,8 5,983 6,93 rca4 0,03 4,87 5,74 0,83 5,368 6,07 0,705 8,893 9,90 Average 0,00,394,50 0,657 3,36 3,66,350 5,37 5,85 Table.

19 MAX K MEAN K MAX K Circuit NO LOW HIGH NO LOW HIGH NO LOW HIGH c7 0,08 6,0 8,34 0,794,45 4,965,68 7,375 3,364 Cm63 0,007 5,564 7,560,79 4,534 9,934 3,067,379 9,597 Cm4 0,07,80,465,59 5,756,685,39,857 30,53 Cm8 0,08 3,7 3,0 0,550 3,9 43,3 0,965 76,959 03,3 cu 0,009,473 3,378 0,84 6,05 8,6,335 7,647 0,77 decod 0,00 7,64 9,90,6 0,535 8,694 5,95 33,5 47,048 Majority 0,03 4,638 6,89 0,687,85 7,88,3 9,68 6,46 m 0,009 5,3 7,446,465 8,893 6,889,650 9,98 4,69 rca4 0,04 0,666 8,96 0,735 5,4 34,465,49 37,947 5,379 Average 0,04 8,56,64,07 7,458 3,94,399 9,57 40,55 Table.

20 PROPOSED [9] Circuit NO LOW HIGH NO LOW HIGH c7 935, ,938 99, , ,350 04,45 cm63 330, , ,5 3309, ,3 3558,588 cm4 3444, , , , , ,05 cm8 03, , ,538 0, , ,875 cu 47,6 430,5 375,65 409,75 73,38 8,60 decod 345, , ,50 346, , ,688 maj. 048, ,5 05, , ,65 4,00 m 483,33 430,450 49, , ,63 449,83 rca4 404,43 4, ,65 404, , ,45 Table 3.

21 APPENDIX I Proof of Lemma. The stochastic rocess of an inut signal at time oint t has as one-ste robability matri the matri Q(t) where: π Q( t) = π 00 0 ( t) ( t) π π 0 ( t) ( t) (I.) with kl 0 π ( t), π ( t) = and k, l S, where each entry, π (t ), is the one-ste l kl kl conditional robability, which can be defined by: π kl kl ( t) ( t) = k, l S ( t) k (I.) It is assumed that the stochastic rocess is time homogeneous and therefore, Chaman- Kolmogorov equations are taken lace []. Thus, we obtain that: P ( t) = P( t) Q( t) (I.3) ( 0 t where, P t) = [ ( t), ( )] are the steady state robability vector at time t. The stochastic rocesses at t=0 and t=0 - is shown in the following π0 (0) π(0) 0 π00 (0 ) π (0 ) 0 π (0 ) 00 π0(0) (a) (b) Markov Chains of inut signal : (a) t=0, (b) t=0 -. The corresonding one-ste robability matrices Q(0) and the Q(0 - ) are:

22 π Q(0) = π 00 0 (0) (0) π π 0 (0) (0) (I.4) Q(0 π ) = 00 (0 0 ) π 0 (0 ) (I.5) Using eq. (I.4) and (I.5) and solving eq (I.3), it is obtained that: P ( 0) = P(0) Q(0) (I.6) 0 ( ) = (0) π (0) + (0) π (0) (I.7) ( 0 0 0) = (0) π (0) + (0) π (0) (I.8) P(0 ) = P(0 ) Q(0 ) (I.9) ( = 0 ) (0 ) π (0 ) (I.0) 0 ( = ) (0 ) π (0 ) (I.) Additionally, the stochastic rocess is SSS and thus, + ( 0 ) = (0) = (0 ) = + 0 ( 0 ) = 0 (0) = 0 (0 ) = = (I.) (I.3) (I.4) Then, from eq. (É.7), (É.8) (É.0) (É.),(É.),(É.3) and (I.4), it is concluded that: π ( 0 ) = π(0) + π0(0) π 00( 0 ) = π 00(0) + π 0(0) (I.5) (I.6) Eventually, multilying the associated left-hand and right-hand side terms of eq. (I.5) and (I.6) k with (0), it is obtained: kk ( 0 ) ) = kk (0) + k ( k (0) k S (I.7)

23 kl ( 0 ) = 0 k, l S k l (I.8) Working in similar way, we can rove for t=0 +. Proof of Lemma. We rove the formula of eq. (), TC (0,0). The remaining formulas, i.e. eq. (.), (.), (.3), (.4) and (.5) can be roved similarly. By definition [5], the TC, ll, mn for the zero delay model is: TC, kl, mn (0,0) = kl mn ( (0) (0)) kl mn ( (0)) ( (I.9) where k and l are the logic values before a transition and m and n the values after a transition of, kk, mn the signals and, resectively and k,l,m,n S. From Definition, TC (0,0) can be eressed as: TC, kk, mn (0 kk mn ( (0 ) (0)) kk mn ( (0 )) ( (0)),0) = (I.0) Alying Lemma (i.e. eq. (4)) and substituting the event (0 ) in terms of t=0 into (I.0), kk we obtain: TC, kk, mn (0,0) = kk k(k) mn ( (0) (0) ) (0)) k(k) kk mn ( ( (0)) + ( (0) ) ( (0)) (I.) kk k(k) Since the events (0) and (0) are mutually disjoint, it is obtained that: TC, kk, mn (0,0) = kk mn k( k) mn ( (0) (0)) + ( (0) (0)) k( k) kk mn ( ( (0)) + ( (0) ) ( (0)) (I.) By definition of TC [5] at t=0, and using eq. (I.9) it holds: where k, l, m, n S. kl mn kl mn ( ( 0) (0)) ( (0)) ( (0)), TC ( 0,0) = (I.3) kl, mn

24 Eventually, from eq. (I.) and (I.3) we infer that: TC kk, TC (0,0) (0) ( ) (0,0) ( )(0), kk, mn kk + TCk k, mn k k, mn(0,0) = kk (0) mn(0) + k ( k )(0) mn (0), (I.4)

25 List of Figure Cation Figure : The logic circuit with Unit Delay AND gates. List of Table Cation Table : Real ower estimation errors of the ro. method. Table : Real ower estimation errors of method [9]. Table 3: Total ower dissiation in ìw.

26 BIOGRAPHIES George Theodoridis received his Diloma in Electrical Engineering from the University of Patras, Greece, in 994. Since then, he is currently working towards to Ph.D. at Electrical Engineering, University of Patras. His research interests include low ower design, logic synthesis, comuter arithmetic, and ower estimation. Syros Theoharis received his Diloma in Comuter Engineering and Informatics from the University of Patras, Greece, in 994. Since then, he is currently working towards to Ph.D. at Electrical Engineering, University of Patras. His research interests include low ower design, multilevel logic synthesis, arallel architectures, and ower estimation. Dr. Dimitrios Soudris received his Diloma in Electrical Engineering from the University of Patras, Greece, in 987. He received the Ph.D. Degree from in Electrical Engineering, from the University of Patras in 99. He is currently working as Ass. Professor in Det. of Electrical and Comuter Engineering, Democritus University of Thrace, Greece. His research interests include arallel architectures, comuter arithmetic, vlsi signal rocessing, and low ower design. He has ublished more than 30 aers in international journals and conferences. He is a member of the IEEE and ACM. Dr. Costas Goutis was a Lecturer at School of Physics and Mathematics at the University of Athens, Greece, from 970 to 97. In 973, he was Technical Manager in the Greek P.P.T. He was Research Assistant and Research fellow in the Deartment of Electrical Engineering at the University of Strathclyde. U.K., from 976 to 979, and Lecturer in the Deartment of Electrical and Electronic Engineering at the University of Newcastle uon Tyne, U.K., from 979 to 985. Since he has been Associate Professor and Full Professor in the Deartment of Electrical and Comuter Engineering, University of Patras, Greece. His recent interests focus on VLSI Circuit Design, Low Power VLSI Design, Systems Design, Analysis and Design of Systems for Signal Processing and Telecommunications. He has ublished more than 0 aers in international journals and conferences. He has been awarded a large number of Research Contracts from ESPRIT, RACE, and National Programs.