Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation

Transcription

1 6.3 Modeling and Estimation of Full-Chi Leaage Current Considering Within-Die Correlation Khaled R. eloue, Navid Azizi, Farid N. Najm Deartment of ECE, University of Toronto,Toronto, Ontario, Canada ABSTRACT We resent an efficient technique for finding the mean and variance of the full-chi leaage of a candidate design, while considering logic-structures and both die-to-die and within-die rocess variations, and taing into account the satial correlation due to within-die variations. Our model uses a random gate concet to cature high-level characteristics of a candidate chi design, which are sufficient to determine its leaage. We show emirically that, for large gate count, the set of all chi designs that share the same high level characteristics have aroximately the same leaage, with very small error. Therefore, our model can be used as either an early or a late estimator of leaage, with high accuracy. In its simlest form, we show that full-chi leaage estimation reduces to finding the area under a scaled version of the within-die channel length auto-correlation function, which can be done in constant time. Categories and Subject Descritors B.7.2 [Integrated Circuits]: Design Aids; General Terms: Algorithms Keywords: Statistical Analysis, Leaage Power. 1. INTRODUCTION As a result of technology scaling, leaage current is becoming a major design challenge, affecting both circuit erformance and ower. Thus, estimating full-chi leaage becomes increasingly imortant. The leaage current of a circuit is not, however, simly the sum of the leaages of the devices in the circuit. Not only do logic-gate structures, such as stacing, affect the device leaage, but rocess variations mae leaage estimation statistical in nature. Full-chi leaage estimation is useful at different oints in the design flow. Towards the end of the design flow (late mode estimation), leaage estimation can be used as a final sign-off tool, and requires a comlete netlist with ossibly a circuit lacement. On the other hand, early estimation of leaage (early mode estimation) rovides the full-chi leaage given limited information about the design, which is very useful to allow for design lanning. While early wor on leaage estimation concentrated on early mode estimators, these wors [1, 2] either did not consider logic-gate structures and other transistor toologies, and/or did This wor was suorted in art by Intel Cor. and Altera Cor. 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Coyright Coyright ACM ACM /7/6 ACM /7/6...$ Mean, Standard Deviation of Process Parameters Correlation Standard ce l library Mean, Standard Deviation of Leaage Process Library Design Ful-Chi Leaage statistics Mean Standard deviation Exected number of gates Exected histogram of standard cel usage Dimensions of the layout area Figure 1: Leaage Estimation Model and the ighlevel characteristics required not consider the effect of correlation between the variations on the total leaage. More recent wor [3, 4] has taen into consideration both the effects of gate toologies and correlation. owever these methods are late mode estimators of leaage that require minimally the circuit netlist and ossibly a circuit lacement to rovide a leaage estimate, and they oerate at the level of the netlist, so they can be exensive on large circuits, with a comlexity of O( ) (some refinements are ossible to reduce this cost, but with some loss of accuracy [3]). Given the need to budget for ower constraints, there is a need for accurate early mode estimators that tae into consideration both correlation and gate toologies. As for late mode estimators, more efficient techniques are required. We resent a new model and methodology for full-chi leaage estimation, in which certain high-level characteristics of a candidate chi design are used to determine its leaage statistics with high accuracy. For late mode estimation, these characteristics can be extracted from the netlist and/or lacement. For early mode estimation, these characteristics can be simly secified as exected values based on revious design exerience or on decisions made in the floorlanning stage. Our methodology uses a concet of a random gate to cature these characteristics and considers both correlations and gate toologies. We show that these high-level characteristics are sufficient to determine the leaage statistics of a design. A bloc diagram of the system is shown in Fig. 1. Given information about (1) the rocess, (2) the standard cell library, and (3) certain high-level design characteristics, we redict the mean and standard deviation of full-chi leaage. The rocess information includes the mean and standard deviation of the underlying rocess variations, such as the variations in transistor length or threshold voltage, and information regarding the within-die satial correlation. The standard cell library information includes the leaage characteristics of the cell library under rocess variations; this information can be obtained by re-characterizing the cells in the library. Finally, some information on the candidate design is needed, including the (extracted or exected) cell usage histogram (i.e., frequency of use distribution) for cells in the li- 93

2 brary, the (extracted or exected) number of cells in the design, and the dimensions of the layout area. With this, we determine the full-chi leaage statistics (mean and variance) for the design. To carry out the estimation, we roose a model which is generic, in the sense that it is a temlate for all designs that share the same values for these high-level characteristics. We use robability theory as the vehicle to imlement this temlate, so that all designs that share the same values of these high-level characteristics will be members or instances of this robabilistic temlate model. We introduce the concet of the Random Gate (RG) which allows us to cature the characteristics of a candidate design. This allows the leaage statistics to be obtained in O(n) time, where n is the number of cells in the design, but we then also show that, for large gate counts, the statistics of the full-chi leaage can be written in integral form, allowing for the comutational comlexity of our estimator to become O(1) time. 1 The ey oint, the thesis of this wor, is that large designs that share the same high-level characteristics will have aroximately the same leaage statistics and, by leveraging this roerty, our estimation engine rovides accurate and efficient estimation, either early or late in the design flow. 2. MODELING Variations normally have two comonents: a Die-to-Die (D2D) comonent, and a Within-Die (WID) comonent. The D2D comonent is a variation between different instances of the die and is shared by all devices on the same die. The WID comonent of variation, however, causes different devices on the same die to have different rocess arameters; the WID variations have some correlation across the die. D2D and WID variations are considered to be (statistically) indeendent, so that the total variance of a rocess arameter, such as transistor length, when both sources of variation are considered, can be written as σ 2 = σdd 2 + σ2 wd where σdd 2 is the variance of the D2D variation and σ2 wd is the variance of the WID variation. To model the WID satial correlation between variations in transistor characteristics, we assume the existence of a satial correlation function [5] that deends on the distance between the two transistors. Given the D2D and WID arameter variances, and the WID correlation, one can easily determine the total correlation between arameter variations (due to D2D and WID effects) by a simle normalization. 2.1 Cell Modeling While the distribution of the underlying rocess arameters can be obtained from the foundry, the leaage distributions of each cell can not be immediately obtained. Since each cell has a different toology, with different transistor stacs, the leaage in each cell is affected differently by the underlying variations in the transistor length and threshold voltage. Furthermore the cell s inuts also affect the leaage distribution of each cell. Leaage current is determined rimarily by transistor, not interconnect, arameters. Of the many transistor arameters, the truly relevant ones are channel-length (L) and threshold voltage (V t), due to the exonential deendence of leaage current on these two arameters. Threshold voltage variations are mainly due to two effects: random doant fluctuations in the channel and the V t roll-off effect whereby V t varies in resonse to variations in L. For this wor, when we refer to V t variations, we secifically refer to the effect of random doant fluctuations. We lum the effect of V t roll-off on leaage into the L variations, because the two are directly related. This allows us to mae the simle statement that V t variations are urely random (indeendent) across the die [6], while L variations are not [3] (they include some within-die correlation). This aroach is in line with the modern treatment of leaage in ublished wor [2]. Since V t variations are indeendent, while L variations are not, it follows immediately that, for full-chi leaage estimation, while V t variations may be relevant for finding the mean of the total leaage, they are definitely not relevant for finding the variance 1 When used as a late mode estimator, there will be some additional cost to extract the cell usage histogram from the netlist, but that also can be constant-time, or linear-time in the worst case. of the total leaage. The reason for this is simle: the variance of the sum of n indeendent random variables is nσ 2, while the variance of the sum of n highly correlated random variables is σ 2. Thus, for large chis (large n), the variance of chi leaage due to V t variations is negligible comared to that due to L variations. This too is in line with the modern ublished wor on leaage [2]. Thus, for leaage variance estimation, we can focus on L alone. As for the effect of V t variations on the mean leaage, that can be easily determined through a multilicative term that deends on the variance of V t, which is derived from the mean of the log-normal distribution, similar to [8]. As this is standard textboo material, it will not be covered here. To model the distribution of the leaage of each cell, we use two methods which have different levels of comutational comlexity and accuracy. The first method uses a Monte-Carlo (MC) analysis to obtain the leaage statistics of each cell. While this technique needs extensive simulations, it does give us some confidence in the resulting distributions. The second method, an analytical aroach, uses a limited samling of the leaage of the cell, and then fits the leaage of the cell into a functional form, from which we comute the mean and variance of the distribution. These two methods are discussed below, and we then discuss correlation and circuit state deendency Monte-Carlo Technique We use a commercial 9nm CMOS technology, along with its associated standard cell library of which we use 62 cells which include the Static Random Access Memory (SRAM) cell, various fli flos and a range of different logic cells. For each cell and inut combination, we erform a MC analysis to determine the mean (µ) and standard deviation (σ) of the cell s leaage. The MC analysis is done assuming all the variations in the transistor channel length within the cell are comletely correlated, which is reasonable in ractice given that the transistors in each cell are very close together Analytical Technique Rao et al. introduced [2] a mathematical model to exress the leaage current, X, of a given cell as a function of channel length, L, to be X = ae bl+cl2 and showed that a fitted model can accurately model the leaage of different toologies including individual transistors and transistor stacs. In our wor, after we fit each cell s leaage into the same functional form, we use the trilet (a, b, c) to determine the mean and variance of the underlying leaage distribution exactly. The derivation, which is not shown due to sace restrictions, results in: µ X = M Y (1) (1) σ 2 X = M Y(2) µ 2 X (2) where M Y (t) is the moment-generating function of Y = ln X which can be shown to be: M Y (t) = (1 2K 1 t) 1 2 e K 2 2 K 1 t 1 2K 1 t +K 3t (3) by using the moment generating function of the Non-Central Chi-square distribution where K 1, K 2 and K 3 are simle functions of the regression arameters (a, b, c) and the mean µ and standard deviation σ of the length, as follows: K 1 = c σ 2 K 2 = 1 σ K 3 = ln a + bµ + c µ 2 c b 2c + µ 2 b + µ (4) 2c To chec the accuracy of the analytical model in determining the mean and standard deviation of cell s leaage, we comare the results obtained from the analytic model to the results obtained through MC analysis for all 62 cells with all inut combinations. For the mean, the analytical method is quite close to the MC results; there is less than a 2% error for all gates, and the average absolute error is.44%. For the standard deviation, the average absolute error is 3.1%, and the maximum error is about 1%. (5) 94

3 Leaage Correlation SPICE MC Analytical Y=X Length Correlation Figure 2: Correlation in length vs in leaage for different gates Mean Leaage Exected Frequency of Cell Usage Examle 1 Examle 2 Examle 3 The error in the mean and standard deviation is not a result of the mathematical derivation, but due to the leaage curve not being exactly maed to the functional form ae bl+cl2. Thus, there is a trade-off between comutational comlexity and accuracy; if MC analysis is erformed on all gates, then the distribution models for all gates will have high accuracy; on the other hand, using the functional form requires minimal simulation time Leaage Correlation As mentioned, we assume the existence of a satial correlation function which gives the correlation between rocess arameters as a function of the distance searating two locations, but which does not rovide the correlation between the leaages of two cells at these locations. Using the regressed trilets, (a, b, c), we have develoed an analytical method that determines the leaage correlation between any air of gates laced at two arbitrary locations on the die given the correlation in their channel lengths. In other words, we have determined a maing ρ m,n(l i, l j ) = f m,n (ρ L (l i, l j )) where ρ L (l i, l j ) is the channel length correlation between two locations l i and l j, f m,n( ) is the derived maing for gates m and n and ρ m,n(l i, l j ) is the leaage correlation for gates m and n laced at locations l i and l j resectively. The details of this maing are not shown for lac of sace, but Fig. 2 shows the results of the leaage correlation given a length correlation for both the MC analysis and the analytical technique for a single air of gates; note that the analytical technique shows a good match to the MC results. Also the leaage correlation is near the y = x line, at which leaage correlation equals channel length correlation. We have erformed the analysis for all airs of gates, and shown that the analytical maing rovides accurate results in all cases. The set of maings f m,n( ) for different gates are slightly different but they all closely follow the y = x line. We will use this observation that the leaage correlation is close to the length correlation in the case where MC analysis is used to obtain the cell leaage statistics since we do not have the (a, b, c) trilet to obtain the leaage correlation exactly Inut Combinations The signal robability (robability that a logic signal is 1) certainly has an effect on leaage. This effect is quite strong for single logic gates, causing a sread of 1X in some cases. owever, for large circuits, the imact of signal robability is significantly diminished due to averaging of their effects (law of large numbers). To study this effect, we have swet the signal robabilities from to 1 and have found, as shown in Fig. 3, that the effect on large circuit leaage is not ronounced and is also deendent on the frequency by which various cells are emloyed in the design. The figure shows the leaage mean, and similar behavior has been found for the leaage variance. For a ractical solution aroach, one has the otion of simly setting the signal robabilities at some ball-ar mid-level value, such as.5. A better aroach, which we emloy, is to first characterize every cell for all its inut states; then, based on this re-characterized data, and for the given frequency of use distribution for cells, find the signal robability setting which maximizes the mean leaage, effectively finding the maximum of a lot such as Fig. 3. Emirically, we find that this setting turns to be very good for finding the maximum leaage mean for the candidate design, as well as its maximum leaage variance. This aroach gives a conservative estimate, in the face of uncertainty about eventual signal robabilities Probability of signals being '1' Figure 3: Effects of signal robability 1 2 W 1 2 m -1 m W Figure 4: Abstract organization of die 2.2 Full-Chi model What determines the leaage of a large circuit? We will demonstrate emirically that certain high-level characteristics of a candidate design are sufficient to determine its leaage. In a librarybased standard-cell design environment, these characteristics are: 1) the cell library (characterized for leaage), 2) the (actual or exected) frequency of usage for cells in the library, 3) the (actual or exected) number of cells in the design, and 4) the dimensions of the layout area. In order to carry out the leaage estimation, we roose a model for the candidate chi design which is generic, in the sense that it is a temlate for all designs that share the same values for these high-level characteristics. We use robability theory as the vehicle to construct this temlate, so that all designs that share the same values of these high-level characteristics will be members or instances of this robabilistic temlate model. After develoing our leaage redictor based on this model, we will then show that the leaages of all instances of secific designs which are members of this model converge towards the redicted leaage value as the circuit size increases; Fig. 6 offers a a snea review of this convergence Model Definition and Suitability Formally, our full-chi model is a rectangular array of a number (n) of identical sites, as shown in Fig. 4, where every site is occuied by a robabilistic abstraction which we call a random gate (RG), and such that the dimensions of the array are equal to the dimensions of the layout area of the candidate design, and that the number of sites n is equal to the number of cells in the design. But what is a RG? Simly ut, a RG is similar to a Random Variable (RV); however, unlie a RV which assumes real numbers as outcomes or instances, the instances of a RG are gates from the standard-cell library, with robabilities identical to those in the frequency of use distribution. In other words, the RG discrete robability distribution is identical to the frequency of cell usage of the design. This full-chi array model is a suitable robabilistic reresentation of all designs having the high-level characteristics highlighted earlier. On one hand, its dimensions and gate count match the dimensions of the layout and the number of cells in the candidate design. On the other hand, the frequency of cell usage of the design is also matched by the way the RG discrete robability distribution is defined. ence, if an instance of the full-chi model is defined to be n RG instances at every site in the array, then the frequency of cell usage for that full-chi model instance will be identical to the frequency of cell usage of the candidate design, for large n. Therefore, the full-chi model is a robabilistic reresentation of a set of designs with the same high-level characteristics, and those designs are in fact instances of our model. Using this fact, we will use the full-chi model to estimate the leaage of the candidate design. One ossible reaction to this roosal is that all sites in the fullchi model are of identical size while obviously cells in the library are of different sizes. Another comment is that the array seems to leave no room for interconnect routing. Both these issues do not resent a roblem. In fact, the size of a site is really the size of the layout area, divided by the number of cells, thus it is the average size of a cell and the interconnect that may be associated with it. Thus, all that is catured by the notion of a RG site is the idea that the leaage due to one cell would on average be sread out or allocated to the layout area of a single site. 95

4 2.2.2 Leaage Statistics of a Random Gate As stated earlier, the RG is simly a gate iced at random from the library, according to a discrete robability distribution which is identical to the frequency of gate usage. In order to erform full-chi leaage estimation based on our model, we need to construct and mathematically define the leaage statistics of the RG. Let I be an RV that taes as values the tye of a gate iced from the library at random to be used in the design. This means that I ɛ {1, 2,..., }, where is the total number of gates in the library, and that the distribution of I is identical to the frequency of gate usage. Let α i be the frequency of usage of gate i. Then: P{I = i} = α i i = 1, 2,..., and i=1 Let X I be an RV that reresents the leaage of a gate iced according to the distribution of I. Then by definition, X I is the leaage of the RG. Consequently, X I is defined on two robability saces; the sace of X due to channel length variations, and the sace of I due to the choice of gate tye. Note that for an arbitrary realization of say I = i, X I will be equal to X i, that is the RV that reresents the leaage of gate of tye i. Recall that the statistics of X i, i.e., its mean µ i and standard deviation σ i, have already been determined during re-characterization for all gates i in the library. We can determine the mean leaage µ XI of the RG as follows: µ XI =E[X I ]=E I [E X [X I I=i]]=E I [E X [X i ]]= i=1 α i µ i (7) α i = 1 (6) where E X [ ] and E I [ ] are the exected values over the saces of X and I, resectively. To determine the variance σx 2 of X I I, we start by determining its second moment E X I 2 as: E[X I2 ]=E I[E X[X I 2 I=i]]=E I[E X[X 2 i ]]= i=1 α i (σ 2 i +µ2 i ) (8) Given the second moment and the mean, the variance can be trivially determined as E X I 2 µ 2 X I Random Gate Leaage Correlation In addition to the RG leaage statistics defined in the revious section, we need to construct and define the RG leaage correlation. Recall that X I is defined as the leaage of a random gate iced from the library according to the distribution of I, and laced at some location on the die. Let X I (l i ) and X I (l j ) be the leaages of the two RGs at two arbitrary locations l i and l j. It is imortant to understand that X I (l i ) and X I (l j ) are identically distributed, and any correlation among these RVs is only due to the correlation over the sace of rocess variations and not over the sace of gate selection. Let C XI (l i, l j ) be the covariance of X I (l i ) and X I (l j ), which is defined as C XI (l i, l j ) = E [X I (l i ) X I (l j )] µ 2 X I. It can be shown, using conditional exectation, that this covariance is given by: C XI (l i,l j )= m=1 n=1 αm αn Cm,n(l i,l j ) (9) where C m,n(l i, l j ) is the covariance of the leaage of two gates of tyes m and n, when laced at locations l i and l j, resectively, i.e., X m(l i ) and X n(l j ). Note that the covariance of the leaage of the random gate X I is the exected value over I of the covariances of all airs of gate tyes. This result is somewhat intuitive since the random gate is an abstraction that embodies all gates in the library. Starting from (9), we can normalize C m,n(l i, l j ) by the standard deviations of gates m and n to get their leaage correlation ρ m,n. Then, we use the analytical maing f m,n( ) from Sectio.1.3 to relate the leaage correlation ρ m,n to channel length correlation ρ L, as follows: C XI (l i,l j ) = m=1 n=1 αm αn [ρm,n(l i,l j )σ m σ n] = m=1 n=1 αm αn σm σn fm,n(ρ L(l i,l j )) (1) Let F (ρ L (l i, l j )) be equal to the final exression in (1) above, and notice that this equation assumes that l i and l j are different. When they are the same, C XI (l i, l j ) is just the variance σ 2 X I. Thus: C XI (l i,l j )= F (ρ L (l i, l j )) for l i l j σ 2 X I for l i = l j (11) By enforcing this correlation structure on our RG array, we ensure that instances of this array have the same correlation structure as the candidate design. 3. FULL-CIP LEAKAGE ESTIMATION For a secific laced design, based on a re-characterized cell library, one can determine the full-chi leaage statistics using techniques from standard robability theory [7] for finding the sum of a number of correlated RVs (each RV corresonds to the leaage of one cell instance). This would be an O( ) aroach, which can be exensive for large circuits (some refinements are ossible to reduce this cost, but with some loss of accuracy [3]). Throughout this aer, we will refer to the leaage obtained from such an O( ) aroach as the true leaage of a given design. Aart from the issue of comutational cost, such an aroach is available only later in the design flow once a netlist and lacement are available; it is useful only as a final chec, and not as a relude to corrective action. In this section, we will first show how we can determine the full-chi leaage statistics in linear time, O(n), and then show how this can be imroved to obtain the statistics in constant time, O(1). Imortantly, we will also show that, for large gate counts, the statistics of any secific design that shares the same high-level characteristics under consideration converge to the values redicted by our model. 3.1 Linear-time method Let I T be an RV that reresents the leaage of our full-chi model, i.e., of the array of n RGs. This means that: n I T = X I (l i ) (12) i=1 where l i is the location of the i th random gate. We are interested in determining the statistics of I T, namely its mean µ IT and variance σi 2. The mean of I T T is equal to: n n µ IT =E[I T ]= i=1 E[X I (l i )]= i=1 E[X I ]=n µ XI (13) The variance of I T can be easily determined using a result from robability theory that the variance of a sum of correlated RVs is equal to the sum of airwise covariances [7]. In other words: n n σi 2 T = C XI (l a, l b ) (14) a=1 b=1 Note that the above double summation accounts also for the cases where l a = l b, for which the covariance is essentially the variance. Using the fact that any covariance can be written in terms of the correlation, C XI (l a, l b ) = ρ XI (l a, l b )σx 2, we can I write the total leaage variance in its final form: n n σi 2 T = σx 2 I ρ XI (l a, l b ) (15) a=1 b=1 where the variance of the full-chi leaage is a function of the variance of the random gate and the extent of leaage correlation across the chi. At this oint, we have determined the mean of the total leaage (in constant time), and have shown that the comutation of the variance of the total leaage requires a double summation over the number of gates on the chi. This O( ) comlexity is not ractically accetable, esecially nowing that n can be extremely large, on the order of millions. By taing into account the shae of the die and the sole deendence of the leaage correlation on the distance between different locations, we are able to cut down the comlexity of comuting the total leaage variance to O(n), as follows. Let the RG array consist of rows and m columns, where the total number of gates, n, is equal to the roduct m, as shown in Fig. 4. Each location or site on the grid can be reresented by a air (r, s) where r is the horizontal index taing values r = 1,..., m and s is the vertical index taing values s = 1,...,. Also, assume that the height and width W of 96

5 j d12 Figure 5: Number of occurrences of a certain distance vector Table 1: % Error in full-chi Standard Deviation for ISCAS85 circuits comared to the RG estimates mi c499 c1355 c432 c198 c88 c267 c5315 c7552 c %.41% 1.14%.36%.74%.52%.23%.34% 1.38% the array are nown. Let and W be the height and width of the site where every gate will be laced. Given the above arameters, the centre to centre distance d ij between any two sites (r 1, s 1 ) and (r 2, s 2 ) can be easily determined to be d ij = (i W ) 2 +(j ) 2 where i is defined as the algebraic difference in horizontal indices, i.e., (r 2 r 1 ), and j is defined as the algebraic difference in vertical indices, i.e., (s 2 s 1 ). Note that i =, ±1,..., ±(m 1) and j =, ±1,..., ±( 1). Now recall the total leaage variance defined in (15) where the double summation covers all ossible airs of locations, and each location is a site on the grid defined by two indices. Since the correlation deends only on the distance d ij between the airs of locations, we can simlify the above exression greatly by erforming the sum over the different distances rather than the airs of locations. To do that, however, we need to determine the number of times each distance d ij occurs. This is relatively easy for a rectangular m grid, as can be seen in Fig. 5, where the number of times a distance d ij occurs along the width of the die is m i and along the height of the die is j. Using these two value, the number of occurrences n ij of d ij can be determined to be the following: m n ij = (m i ) ( j ) (16) Since the leaage correlation between any two given locations deends only on the distance between these locations, we will exlicitly highlight this fact, ρ XI (l a, l b ) = ρ XI (d ij ) where i and j in the above equation are the algebraic differences in the horizontal and vertical indices of l a and l b. Starting from (15), we will transform the quadratic summation that runs over all airs of locations, into a summation that runs over the set of ossible distances induced by the rectangular shae of the grid. This set will be covered if all the algebraic differences i and j are covered. After accounting for the number of times each algebraic difference occurs, n ij, we get the following exression for the total leaage variance: = σ 2 X I m i= m j= (m i ) ( j ) ρ XI (d ij ) (17) where the double summation runs at most O( m) = O(n) times. This summation is linear in circuit size. Note that the exression in (17) is an exact transformation of (15) without any aroximations Validation Two tyes of validation tests were run, by first considering randomly generated circuits, as a way to mae conclusions about the set of all circuits of a given size, and then by considering secific benchmar circuits. In the first set of exeriments, a large number of circuits were randomly generated so as to match a frequency of cell usage that was secified a riori. The circuits were then laced and routed, and their true leaage statistics (mean and variance) were found. % Difference 1.% 7.5% 5.% 2.5%.% 1-2.5% % -7.5% -1.% -12.5% Maximum Positive Difference in the Mean Maximum Positive Difference in the Standard Deviation Maximum Negative Difference in the Mean Maximum Negative Difference in the Standard Deviation Number of Gates Figure 6: Errors in the estimation of mean and standard deviation of full-chi leaage Fig. 6 shows the maximum ositive and negative difference between the means and standard deviations of the leaages of these circuits comared to the estimates rovided by our model. It can be seen that as the number of gates in the circuits increases, the difference aroaches zero; at a circuit size of 11,236 gates, the maximum difference is 2.2%. This small amount of error indicates that the set of all chi designs that share the same high level characteristics have aroximately the same full chi leaage statistics and thus these high-level characteristics are sufficient to determine chi leaage. This first set of exeriments serves to justify the statement that this aroach is useful as an early estimator of full-chi leaage. In the second set of exeriments, we show how the model can be used as a late estimator of leaage for real (laced and routed) circuits. In this test, we have extracted the relevant high-level characteristics from each ISCAS85 circuit, namely the number of gates used, the histogram of cells used, and the dimensions of the layout; then with these values, we have used our model to estimate the leaage statistics of every circuit. Table 1 lists the errors in the full-chi leaage standard deviation, for all ISCAS85 circuits, between our model and the true leaage of these circuits. The errors are very small (notice, however, that these do not include any cell leaage modeling errors, which were discussed earlier in sectio.1). We do not show the errors in the mean leaage because they are truly negligible Simlified Correlation Assumtion In Sectio.1 we noted that the cell leaage statistics (i.e., the mean and standard deviation of leaage) can be obtained in two ways; either (1) a MC analysis would be done or (2) the cell s leaage would be fitted into a functional form to get three fitting arameters (a, b, c). Using these arameters, the leaage mean and standard deviation were analytically obtained. The fitted arameters also allowed us to determine the leaage correlation between any air of gates, ρ m,n, given the channel length correlation ρ L. Using the maing, f m,n( ), the RG leaage correlation was determined in (1). If we, however, choose to obtain the leaage statistics of each cell through MC analysis, we would not be able to use f m,n( ) to determine the leaage correlation between airs of cells because the correlation maing deends on the fitting arameters which are not available in MC mode. Without this maing, the RG leaage correlation cannot be determined. The solution to this roblem lies in Fig. 2, where we have noted that the leaage correlation of any air of cells is aroximately equal to the correlation in the channel length of these cells. In other words, ρ m,n ρ L, m, n. With this simlified correlation assumtion, (1) can be used to determine the RG leaage correlation. To determine the amount of error introduced by this assumtion, we have comared the difference between the standard deviation when assuming ρ m,n = ρ L comared to the analytical aroach, i.e., when using the true f m,n( ) maing. Regardless of whether we assume solely WID variations or have both WID and D2D variations, the ercentage error is below 2.8%. 3.2 Constant-time method In this section, we show how, for large values of n, we can aroximate the linear summation in (17) by an integral to obtain the statistics of full-chi leaage in constant time. 97

6 D Integration in Rectangular Coordinates Starting from (17), let x i = i W and y j = j, and by multilying out W and we obtain: = σ 2 X I W m i= m j= (W x i ) ( y j ) ρ XI (d ij ) (18) where W = m W, =, and d ij = x 2 i +y2 j. By using a double integral to aroximate the double summation over discrete values, we obtain: σ 2 X I ( W ) 2 W x= W y= (W x ) ( y ) ρ XI x 2 +y 2 dy dx (19) Let the area of a RG site be A site = W and the area of the die be A = na site. Note that the function being integrated is even, so that we can write: W (W x) ( y) ρ XI x 2 +y 2 dy dx (2) The exression in (2) aroximates the full-chi leaage variance for large values of n. Since the number of gates on the chi is tyically in the order of millions, the aroximation is valid in most cases. What is interesting about this exression is that it only requires the comutation of an integral, which can be erformed in constant-time using a good numerical integration routine; the leaage variance comutation does not deend on the number of gates n, it is O(1) D Integration in Polar Coordinates To mae our comutation even more efficient, under certain conditions we can transform the double integral in (2) into a single integral in olar coordinates. First we write an exact maing of (2) in double-integral form using olar coordinates: π/2 D(θ) (W r cos θ) ( r sin θ) ρ XI (r) r dr dθ (21) where D(θ) is the distance from the origin to the boundary of the rectangular integration domain, which is less than the largest distance on the array. If the distance at which the WID correlation function reaches is less than the minimum of the height or width of the array, then the double integral in (21) can be written as a single integral. To derive this single integral, let us for the moment assume that there are no D2D variations and that ρ XI becomes zero at a distance D max. If D max is less than min(w, ) then (2) can be written as: Dmax π/2 (W r cos θ) ( r sin θ) ρ XI (r) r dθ dr (22) Since the correlation function does not deend on θ, we can further simlify the above exression by searating the integrals: Dmax ρ XI (r) r π/2 (W r cos θ) ( r sin θ) dθ dr (23) The exression in the bracets can be analytically integrated and results in the following exression: g(r) =.5r 2 (W + )r + π 2 W (24) which leads to the final exression for full-chi leaage variance: 4 σ 2 X I Dmax ρ XI (r) r g(r)dr (25) When also considering D2D variations, recall from Sectio that the correlation never reaches zero, and thus the single integral technique does not immediately aly. owever, if we divide u the correlation function ρ XI (r) into a constant ortion, ρ C, and a ortion that does go to at D max, ρ X I (r) = ρ XI (r) ρ C, then the single integral can be written as: 4 σ 2 X I Dmax ρ X I (r) r g(r)dr + σx 2 I ρ C (26) % Error 1.% 1.% 1.%.1%.1% 1.E+ 1.E+2 1.E+4 1.E+6 1.E+8 1.E+1 Num Cells Figure 7: % Error between numerical integration and linear time algorithm Validation The value of the standard deviation of the full-chi leaage obtained from the numerical integration (2) was comared to the value obtained from the O(n) aroach resented in Section 3.1. As can be seen in Fig. 7, for circuits that have more than ten thousand gates there is less than.1% error between the numerical integration and that of the linear-time algorithm. For circuits with a small number of gates (<1) the % error is more than 1%; this is due to the granularity of the gates being a significant roortion of the total area of the design causing the integral to be less accurate than the true sum. For larger designs, the area of the logic gates comared to the area of the design aroaches zero, allowing the numerical integration to rovide good results, with less than.1% error. Given that the O(n) time algorithm taes less than one second for circuits with less than 1 gates, one can use the O(n) time algorithm in those cases, and use the numerical integration for circuits with a much larger number of gates. 4. CONCLUSION We resented a robabilistic full-chi model that can be used to estimate, in constant-time, the leaage statistics of candidate designs either at an early or a late stage, while considering withindie correlations. We roosed and verified that certain high-level characteristics of a candidate chi design are sufficient to determine its leaage. These high-level characteristics, shown in Fig. 1, include information about the rocess, the standard-cell library, and the design in question. We showed that, for large gate count, the set of all chi designs that share the same high level characteristics have aroximately the same full-chi leaage statistics, with very small error. We cature this set by a full-chi model based on Random Gates (RGs). 5. REFERENCES [1] S. Narendra, V. De, D. Antoniadis, and A. Chandraasan. Full-chi sub-threshold leaage ower rediction model of sub-.18µm CMOS. ISLPED, 22. [2] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester. 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