Statistical Timing Analysis Based on a Timing Yield Model

Transcription

1 2.4 Statistical Timing Analysis Based on a Timing Yield Model Farid. ajm Deartment o ECE University o Toronto Toronto, Ontario, Canada oel Menees Strategic CAD Lab. Intel Cororation Hillsboro, Oregon, USA ABSTRACT Starting rom amodel o the within-die systematic variations using rincial comonents analysis, a model is roosed or estimation o the arametric yield, and is then alied to estimation o the timing yield. Key eatures o these models are that they are easy to comute, they include a owerul model o withindie correlation, and they are ull-chi models in the sense that they can be alied with ease to circuits with millions o comonents. As such, these models rovide a way to do statistical timing analysis without the need or detailed statistical analysis o every ath in the design. Categories and Subject Descritors B.7 [Integrated Circuits]: Design Aids General Terms Algorithms, Design, Theory Keywords Statistical timing analysis, timing yield, rincial comonents. ITRODUCTIO The yield o an integrated circuit (IC) is a comlex unction oanumberoactorsrelatedtobothdesignandmanuacturing. Beyond issues o design centering [, 2], which ocuses mainly on tuning the manuacturing rocess, yield is also aected by circuit design. As art o circuit timing veriication, one has to leave enough margin so that circuit delay variations do not aect yield too adversely. We will ocus on this art o the overall yield roblem, reerred to as timing yield or circuit-limited yield [3, 4]. Traditionally, this has been taken care o by using the right worstcase ile [5] as art o timing or erormance veriication (tyically, during static timing analysis). The worst-case iles seciy the values o transistor arameters or various rocess corners, including the nominal and various extremes o device behavior. A circuit is deemed to have assed the timing test i it meets the erormance constraints or all worst-case iles belonging to that rocess. However, this aroach is becoming less easible today, esecially or high-erormance chis. For one thing, it can be too conservative and does not rovide the user with any quantitative eedback on the robustness o the design [5] it is a ass/ail aroach. In addition, this traditional aroach cannot handle within-die statistical variations [4] (mismatch between devices on Permission to make digital or hard coies o all or art o this work or ersonal or classroom use is granted without ee rovided that coies are not made or distributed or roit or commercial advantage and that coies bear this notice and the ull citation on the irst age. To coy otherwise, to reublish, to ost on servers or to redistribute to lists, requires rior seciic ermission and/or a ee. DAC 24, June 7, 24, San Diego, Caliornia, USA. Coyright 24 ACM /4/6...$5.. the same chi) which have become imortant in dee sub-micron rocesses [3]. Statistical techniques oer a better alternative aroach statistical transistor modeling techniques [6, 5] have been used or quite some time. Recently, due to the increased imortance o within-die variations, there has been an increased interest in tackling the timing yield roblem by emloying statistical techniques as art o the circuit timing analysis ste [4, 3, 7,, 9]. The aim is to extend traditional static timing analysis so that it takes into account statistical delay variations. Within-die variations are o two tyes: systematic and statistical. The systematic tye are due to satial location o a certain eature on the die and due to the context o that eature in terms o the layout atterns around and above it. Techniques have been roosed [] or taking into account this tye o variations. However, statistical within-die variations have not been adequately addressed. A key contribution o this aer is to take within-die statistical correlations into account. To be sure, some rior work has been done on this. In a number o cases [4, 9,, 2], it has been assumed that within-die variations are totally uncorrelated (so that ath yields are multilied to give the chi yield), an assumtion which is not true in ractice. In order to avoid making this assumtion, one needs to exress the correlations between within-die arameter variations with a model that can be easily built rom rocess data. This oint is key, and is hard to do - there are no ublished models, or instance, or how exactly the variations are correlated across the die as a unction, say, o the distance between comonents. A model o correlations in terms o distance is mentioned and used in [3], but no details or data are given it is not clear what shae the model should take nor how one would build it rom rocess data. In [], even though statistical within-die variations are not taken into account, a suggestion is made at the end as to how one may include them and take care o correlation by enorcing correlation between eatures that are in the same region o the layout. This theme was urther develoed recently where use was made o rincial comonents analysis [4] or a quad-tree artitioning [5] to exress a region-wise satial correlation among within-die variations. Here too, it is not clear how one would identiy these regions and how the model would be built rom rocess data. Finally, since these methods deend on lacement inormation, these tyes o timing analysis become inal sign-o tools and are unusable during circuit design. We roose an aroach to take within-die statistical correlations into account with a model that can be easily be built rom rocess data, and which can be alied re-lacement. 2. PROPOSED APPROACH In our aroach, we cature the within-die correlations using rincial comonents analysis (PCA). This is not, by itsel, necessarily an imrovement over rior art because, as with revious methods, the coeicients o the PCA would have to be evaluated somehow rom rocess data, and would deend on osition in the layout. However, with this model in hand, we then develo an aroach to estimate a on the timing yield which which does not require knowledge o the individual PCA coeicients, but requires only the order o the PCA (the number o terms). While estimating detailed correlation unctions is hard to do rom rocess data, estimating only the order o the PCA would seem to be much easier, and we will suggest ways in which this may be done. Since layout inormation is not required, this a- 46

2 roach becomes alicable to the re-layout hase, during circuit design and otimiation. Previously roosed techniques or statistical static timing analysis change the static timing low so that one is roagating distributions o delay, instead o simly delay. Even though there may be ways o doing this eiciently, this does reresent a signiicant change o methodology! For one thing, statistical cell models [6] would need to be built i one is to use a cell-level or block-level low. In contrast, our aroach does not roagate distributions. Instead, the result o our aroach is a selection o a device ile setting with which to run traditional static timing analysis, which is somewhere within the extremes o device behavior. For examle, while the nominal device ile may call or a setting o L (or channel length variations) and the worst-case ile may call or a setting o L +3 L, our aroach aims to redict the value k such that i the setting o L k L was used or all devices, and i the circuit timing is veriied using traditional static timing analysis, then the circuit would give the desired timing yield. As a result, our aroach reserves existing static timing methodology and only assumes the existence o statistical transistor models, which have been standard or some time. We will do this by working with a generic critical ath concet, in the style o [3], and examining the statistical roerties o large ensembles o such aths. Due to the tyically huge number o critical aths on chi, the law o large numbers [7] will come into lay, and we will show that the actual number o aths dros out o the yield equation. We will be let with a yield exression that deends only on the various comonents o the variances (these will be exlained below) and on the device ile setting. For a minimum desired yield, we will work backwards to ind the required settings o device arameters. 3. PARAMETER MODEL For a given circuit element or layout eature i, let its coordinates on the die be (x i,y i )andletx(i), be a ero-mean Gaussian random variable (RV) that denotes the variation o a certain arameter o this element rom its nominal (mean) value. Thus, or examle, X(i) may reresent channel length variations o transistor i. Correlation between values o X(i) at dierent locations on the die may be exressed by means o an autocorrelation unction, but this is not a ractical aroach. Instead, it is standard ractice [] to exress the correlation by irst breaking u the variations into die-to-die and within-die comonents, as ollows: X(i) X dd + X wd (i) () Thedie-to-diecomonentX dd is an indeendent ero-mean Gaussian RV that takes the same value or all instances o this element on a given die, irresective o location. The within-die comonent X wd (i) is a ero-mean Gaussian which can take dierent values or dierent instances o that element on the same die. This leads to the ollowing relationshi between the variances: 2 (i) dd wd (i) (2) Then, the within-die comonent is urther broken down into two comonents, a systematic comonent and a random comonent: X wd (i) X wds (x i,y i )+X (3) where, or each i, the random comonent X isanindeendent ero-mean Gaussian. otice that the use o the term systematic here is somewhat dierent than the mention that was made o it in the introduction. In the introduction, we distinguished between systematic and statistical variations. In this case, the systematic comonent o the variations is statistical. Unortunately, this same term is used in the literature to denote two dierent things. Throughout the rest o the aer, the term systematic will denote statistical variations such as X wds (x i,y i ). The systematic comonent X wds (x i,y i ) contains an exlicit deendence on location because it is usually taken to reresent the extent o correlation across the die, and correlation is usually deendent on relative location. A similar relationshi ollows or the variances: wd 2 (i) 2 wds (x i,y i )+wdr 2 (i) (4) One way to exress the systematic comonent o the within-die variations is to use a rincial comonents analysis (PCA) [9] and write: X X wds (i) a ij Z j (5) where Z j are indeendent standard normal RVs (Gaussians with ero mean and unity variance) and where the coeicients a ij are such that: X wds 2 (x i,y i ) a 2 ij (6) The RVs Z j corresond to underlying indeendent unobservable actors. The value o and the coeicients a ij reresent the extent o correlation across the die. For examle, i, then the within-die satial correlation coeicient is, there is erect correlation a single underlying RV Z determines the value o the systematic comonent o X wd all over the die. A > allows or less than erect correlation. We will adot the PCA exansion (5) as our correlation model or the within-die comonent. At irst glance, this model aears hard to use because it seems to deend on knowledge o the values o all the a ij arameters. These coeicients deend on layout and, in any case, it is not clear how one would comute them rom rocess data. A brute-orce PCA exansion o the millions o instances o a arameter on a chi would be imractical. However, it will be shown in the ollowing sections that one can estimate a on the yield without having to know the values o the a ij arameters. Instead, it will be suicient to know: ) the order () o the PCA exansion, and 2) the ranges (max and min) o the variance terms given above. In the aer, the crucial ste in the analysis is in the transition rom (27) to (2), where an exression or yield that deends on all the a ij terms is transormed (using Cauchy s inequality) to one that deends only on the sum o all the a 2 ij terms, which is easily available as the variance (6). An imortant question, however, is how is to be estimated. We can name three ways in which this may be done. First, based on knowledge o the rocess, it may be ossible to simly identiy a number o underlying indeendent actors that are resonsible or the systematic variations, such as seciic equiment or rocess stes. Second, one may associate each Z j with a certain satial location on the die, such as was done recently in [4]. Thus, i the chi area is artitioned into, say, our quadrants, and i one has some sense about distances over which the autocorrelation unctions die down, one may be able to make an estimation o. Third, and this may be the most ractical aroach, we can measure yield or a certain arameter, rom rocess data, and then use the ormulas to be derived below or arametric yield to work backwards to comute a value o. 4. PARAMETRIC YIELD MODEL With the random arameter model given above, we now deine the arametric yield or arameter X as: Y (x) P{X(i) x, i, 2,...,n} (7) where n is the number o instances o this arameter on chi. Here, X(i) isageneric arameter that may reresent transistor channel length variations, threshold voltage variations, etc. In act, X(i) isany statistical quantity on chi that may be characteried by the arameter model introduced in section 3. When X(i) is a simle arameter, such as channel length, then arametric yield is the robability that all device lengths on the die are less than some threshold x. We will later on below show how ath delay can itsel be viewed as a arameter with its own trilet o variances (dd 2, 2 wds, 2 wdr ) that we will relate to the underlying transistor arameter variances. This will allows us to exress timing yield based on a arametric yield model. Thus, the material in this section, although ocused on arametric yield, will actually be directly useul or comuting timing yield. ote also that, although we are exressing yield as a unction o an uerbound constraint on the value o the arameter, our work can be extended to cover and/or interval constraints. Since X dd is an indeendent ero-mean Gaussian with variance dd 2,thenZ X dd / dd is an indeendent standard normal RV (mean, variance ), and the exression or Y (x) can be exanded as: Y (x) P{ dd Z + X wds (x i,y i )+X x, i} () We now recall a result rom basic robability theory that will be used reeatedly in the aer. Let A be an arbitrary event, and X be an RV with a robability density unction (d) (x). Then (see [7], g. 5) we have: P{A} P{A X x}(x)dx (9) 46

3 This result is simly an extension to the continuous case o the simle act that P{A} P{A B} P{B} + P{A B} P{B}, where B is another event. Alying (9) to (), and denoting by φ( ) the d o the standard normal distribution, gives: + Z Y (x) P{X wds (x i,y i )+X x dd, i}φ()d () Let X wd max(x wds (x i,y i )+X ) and denote its cumulative distribution unction (cd) by Y wd (a) P{X wd a}, then: i Y (x) P{X wd x dd } φ()d() Y wd (x dd )φ()d () which means that: Y (x) E Y wd (x dd Z ) (2) where E[ ] is the mean or exected value oerator. The bulk o the eort will now be directed at comuting the cd Y wd (a). We irst consider the secial case searately, beore covering the general case. 4. Secial Case In this case, X wds (x i,y i ) wds (x i,y i )Z, where Z is an indeendent standard normal. Thereore: Y wd (a) P{ wds (x i,y i )Z + X a, i} ny P{X a wds (x i,y i )} φ()d (3) wherewehaveagainmadeuseo(9)andotheactthatx are indeendent. Since X is a ero-mean Gaussian with variance wdr 2 (i), then: ny wds (x i,y i ) Y wd (a) Φ φ()d (4) " ny E Φ wds # (x i,y i )Z (5) where Φ( ) is the cd o the standard normal. Let wds min ( wds(x i,y i )) and wds max ( wds(x i,y i )). Since Φ( ) i i is monotonically increasing, then (4) leads to the : Z ny wds Y wd (a) Φ φ()d (6) ny wds + Φ φ()d (7) Let wdr min ( wdr(i)) and wdr max ( wdr(i)), and consider the ossible ranges o values o a. I a, then (6) is i i minimied at wdr and (7) is broken into two integrals, one o which is minimied at wdr and the other at wdr,sothat: Z Y wd (a) Φ n wds φ()d wdr Z a/wds + Φ n wds φ()d Z wdr + + Φ n wds φ()d () a/ wds wdr and i a then a similar analysis leads to: Z a/wds Y wd (a) Φ n wds φ()d wdr Z + Φ n wds φ()d a/ wds wdr + Φ n wds φ()d (9) wdr I these s on Y wd (a) are used in (2) then the result would be a Y (x) on the yield: Y (x) Y (x). These bounds are exected to be tight i the dierences ( wds wds ) and ( wdr wdr ) are small. With a simle change o variables, as will be illustrated below, Y (x) can be comuted by numerical integration. I a yield o, say, better than 9% is desired, then one can set Y (x).9 and work backwards to get the value o the threshold x. 4.. Illustration For illustration uroses, it is instructive to consider the simliied secial case when dd wds (x i,y i ), i. In this case, it becomes ossible to get exact solutions to (2), instead o s, as ollows. Starting rom (5), we get: i Y wd (a) E hφ n a Z (2) and, combining this with (2) (to see why it is valid to combine the two in this way, see o [7]) leads to: Φ n (x/) Z Z Y (x) E (2) In order to comute this, we use the deinition o the exected value oerator (as an integral) and with a change o variables o u Φ( )andv Φ( ), we arrive at: Z Z Y (x) Φ n x Φ (u) Φ (v) dudv (22) Plots o this arametric yield or dierent values o n are shown in Fig.. otice that yield decreases or larger n, as exected. 4.2 The General Case P Here X wds (x i,y i ) a ij Z j,where a 2 ij 2 wds (x i,y i ), so that: + Z Y wd (a) P + Z X : ny P a ij Z j + X a, i 9 (23) P i (a)φ( ) φ( )d d (24) wherewehavemadeuseo(9)anumberotimes() andothe act that X are indeendent, and where: 9 P i (a) P : X wdr(i) a a ij j (25) We know rom basic robability theory that, i X is an RV and a a 2 are two real numbers, then P{X a } P{X a 2 }. In the roblem at hand, we have: X v X ut X a ij ji a ij j a i 2 ij j 2 (26) where the 2nd inequality ollows rom Cauchy s inequality [7]. Thereore: P i (a) P : (a X wdr(i)) P : (a X wdr(i)) P vut X a 2 ij X which, using a 2 ij 2 wds (x i,y i ), leads to: vut X 9 X a ij j 9 vut X j 2 vut X P i (a) P : X wdr(i) a wds (x i,y i ) j 2 qp B Φ@ a wds(x i,y i ) 2 j 9 (27) (2) C A (29) 462

4 Parametric Yield n e3 n e6 n e x Figure : Parametric yield. The transition rom (27) to (2) is a key ste and is undamental to our contribution. A yield exression based on (27) would be very hard to use in ractice because it requires knowledge o the individual a ij coeicients. As reviously mentioned, it is not clear how one would obtain these coeicients, which anyway are unctions o layout, rom the rocess data. However, estimation o the based on (2) would be quite easible because it deends only on knowledge o the variance. It is recisely this ste in the analysis that allows us to make yield estimation based on a generic critical ath and without requiring layout inormation. Plugging (29) into (24) gives: 2 qp Y wd 6Y (a) E 4 n B Φ@ a wds(x i,y i ) 3 Z2 j C A qp 6Y E 4 n B Φ@ a 3 wds Z2 j C A 7 5 (3) qp where the 2nd inequality is true because Z 2 j, and where wds, as beore, is the largest wds (x i,y P i ). Let Q bean indeendent ositive RV such that Q 2 Z2 j,thenq2 has the chi-square (χ 2 ) distribution with degrees o reedom [7]. Thereore, we can relace the above right-hand-side by: Y wd (a) E Z ny Φ " ny # Φ wds Q (3) a wds q χ 2 (q)dq (32) where χ 2 ( ) is the d o the χ 2 distribution with degrees o reedom. As was done in the case, a case-analysis based on the sign o a gives our inal result. I a then: Y wd (a) Z a 2 / 2 wds Z + a 2 / 2 wds a Φ n wds q χ 2 (q)dq wdr a Φ n wds q χ 2 (q)dq (33) wdr where, as beore, wdr and wdr are the largest and smallest, resectively. I a, then similarly: Z a Y wd (a) Φ n wds q χ 2 (q)dq wdr (34) 4.2. Illustration Consider again the secial case where dd wds (x i,y i ) Y wd (a) E hφ n a i Q (35), i. Then (3) leads to: and, combining this with (2), leads to: Y (x) Y (x) E Φ n ((x/) Z Q ) (36) Plots o this arametric yield are given in Fig., or various values o and n. otice that a larger has the same eect as a larger n more things can go wrong and the yield is lower. 4.3 Bounded Variations otice that, in the above exressions or yield, the yield decreases or larger n. One would somewhat exect this, but it is surrising to note that the yield aroaches ero as n goes to ininity, or any combination o values o the three variances. This may also be seen in the above lots in Fig.. Even i the threshold is set at, there is still some arametric yield loss. This is somewhat non-hysical, and arises due to the act that we have assumed that the distribution o X is normal recall that the normal distribution extends to ± in both directions. In reality, one would exect rocess variations to be bounded by some uer and s. I a device somewhere deviates by large amounts, like 9 or, then chances are there is a serious roblem with that die, and that it would be lost due to other reasons, other than timing yield that is. Thereore, it is a good idea to limit the sread the cd o X to some multile o in order to avoid these non-hysical eects at large n. In this section, thereore, we will use a truncated normal distribution or X. For clarity o resentation, we will restrict the analysis to the illustrative secial case introduced above wherein dd wds (x i,y i ), i. The analysis can be extended to the general case. Suose, thereore, that X is bounded by ±k, andletφ t(x) reresent the cd o the truncated standard normal, which is or x k and or x>k. We can lug Φ t( ) instead o Φ( ) (orx ) into the above equations and lot the resulting yield integrals, as shown in Fig. 2. In this case the yield loss at higher n values is limited so that the e6 and e lots in each grou are indistinguishable. This is to be exected, because the tail o the distribution has been cut o, and it is rimarily the tail that causes the yield loss at very large n. When working with a truncated normal, it is noteworthy that we can derive s on the yield that are indeendent o n. The derivations are not shown, or brevity, but lead to the ollowing results. For the secial case when,wehave: Y (x) Y (x) E Φ((x/) k Z ) (37) A lot o this yield is shown in Fig. 2, in the grou. The is very tight, and is indistinguishable on the lot rom the e6 and e curves in that grou. In the general case o, we can show: 2 Y (x) E U((x/) k Z ) χ 2 ((x/) k Z ) (3) where U(x) isorx andorx. Some lots o this yield are shown in Fig. 2. As beore, the is very good, and is indistinguishable on the lot rom the e6 and e curves in each grou. 5. TIMIG YIELD MODEL In dee sub-micron CMOS, rocess-induced delay variations are due mainly to variations in the MOSFET threshold voltage (V t) and eective channel length (L e). Due to short-channel eects, V t may deend on L e (the so-called V t roll-o eect), so that V t and L e are not indeendent variables. We cature this by assuming that V t can be exressed as the sum o a term that deends on L e and another indeendent term, so that, as RVs, we can exress V t and L e o transistor i as ollows: L e(i) E [L e(i)] + L(i) V t(i) E [V t(i)] + (L(i)) + V (i) (39) where E[ ] is the mean (exected value) oerator. We are interested in the RVs L(i) andv (i),whichareassumedtobeindeendent o each other. We assume these RVs to be ero-mean Gaussians and break them u in the usual manner as: L(i) L dd + L wds (x i,y i )+L V (i) V dd + V wds (x i,y i )+V (4) 463

5 Parametric Yield k , n e3, n e6, n e 2, n e3 2, n e6 2, n e 4, n e3 4, n e6 4, n e 6, n e3 6, n e6 6, n e x Figure 2: Parametric yield or k 3. (O course, here V dd is the die-to-die comonent o V (i), and not the suly voltage.) We assume that the variances o L(i) and V (i), as well as the variance o their comonents, are known rom the technology iles: L 2 (i) 2 dd,l + 2 wds,l (x i,y i )+wdr,l 2 (i) V 2 (i) 2 dd,v + 2 wds,v (x i,y i )+wdr,v 2 (i) (4) 5. Gate Delay We assume that, or a given chi design in a given technology, one can deine a nominal reresentative logic gate, with aroriate outut loading and inut sloe. For reasons that will become clear below, this gate should be tyical o gates on critical aths in this technology. Due to the nonlinearity o the relationshi between gate delay and transistor arameters, the mean value o gate delay does not necessarily coincide with its nominal value (the value corresonding to the case when L(i) and V (i) ). Furthermore, the distribution o gate delay would not necessarily be Gaussian. Simle exeriments with HSPICE, however, reveal that this nonlinearity is not strong, at least not in.3µm CMOS. Thereore, we will ignore these comlications or now, and simly assume that gate delay is a Gaussian with mean equal to its nominal value. For all the transistors within a logic gate, we assume that their channel length variations are catured with a single RV L(i) and their threshold voltage variations are catured with a single RV V (i). Having ignored the nonlinearity between gate delay variations and the V t and L e variations, then i D(i) is the deviation o the delay o logic gate i rom it s mean (nominal) delay, we have: D(i) αl(i)+βv (i) (42) where α and β are sensitivity arameters, with suitable units, that one can easily obtain rom circuit simulation o a reresentative logic gate. otice that, in general, α > and β >. (For a seciic industrial.3µm rocess, we have ound that or a minimum-sied inverter, α.57s/nm and β 7.3s/V.) As a result, we can exress the statistical variations in delay o gate i as: D(i) D dd + D wds (x i,y i )+D (43) so that D dd αl dd + βv dd, D wds (x i,y i ) αl wds (x i,y i )+ βv wds (x i,y i ), and D αl +βv. This leads to dd,d 2 α2 dd,l 2 + β2 dd,v 2, 2 wds,d (x i,y i )α 2 wds,l 2 (x i,y i )+ β 2 wds,v 2 (x i,y i ), and wdr,d 2 (i) α2 wdr,l 2 (i) +β2 wdr,v 2 (i). These equations rovide a way in which the statistical model o gate delay (i.e., its three variances) can be comuted rom the underlying statistical model o transistor arameters. 5.2 Path Delay Consider a ath o logic stages (gates). Variations in ath delay are due to variations in the delays o both the gates and the interconnect. For simlicity o resentation, we will ocus on the gate delay variations only. Interconnect delays can be handled in a similar way. Having assumed that nominal gate delay coincides with mean gate delay, the same ollows or aths. Let D (j) denote the deviation o the P delay o ath j rom its mean (nominal) value. Since D (j) D(i), then: D (j) D dd + X D wds (x i,y i )+ The gates on a ath exist at various dierent locations. We will make the simliying assumtion that as ar as hysical location on the die, or uroses o comuting the within-die-systematic comonent, all gates on ath j share the same nominal coordinates (x j,y j ), so that: D (j) D dd + D wds (x j,y j )+ X X D (44) D (45) This is motivated by the exectation that gates on a critical ath should be nearby on the die, and dierences between their osition-deendent within-die-systematic variations should be minor. Based on the indeendence relations between the terms in the above, we have dd,d dd,d, 2 wds,d (x j,y j ) 2 wds,d 2 (x j,y j ), and i ˆ wdr,d 2 (j) is the average P value o 2 wdr,d (i) over all gates on this ath, then wdr,d 2 (j) 2 wdr,d (i) ˆ wdr,d 2 (j). As or ˆ2 wdr,d (j), we may aroximate it using the average value o wdr,d 2 (i) over the whole die, which we denote by ˆ wdr,d 2,sothat: wdr,d 2 (j) ˆ wdr,d 2 (46) With this, we have a ull statistical model o ath delay, so that we can treat it as a arameter and we can talk about its yield, as was done or the generic arameter X(i) in sections 4 and Timing Yield The timing success o an integrated circuit deends on a number o actors, including max delay violations, min delay violations, clock skew violations, etc. In this work, we ocus on max delay constraints and consider a circuit to ass the timing test i its longest (critical) ath delays are below some threshold (our work can be extended to cover other timing concerns). We let be the number o stages (gates) on a ath that would be reresentative o these critical aths, and we consider that the chi contains a (tyically large) number o disjoint (non-intersecting) critical aths o stages (gates) each, so that our exression or the chi timing yield becomes: Y (τ) P{D (j) τ, j} Y (τ) (47) where Y ( ) is the exression or yield ound above, in sections 4 and 4.3. Since the aths being considered are disjoint, then any correlations between their delays would be due only to correlations in the rocess variations, and not to the sharing o circuit comonent. I Y is the desired yield, then the techniques o sections 4 and 4.3 eectively rovide the inverse unction to comute τ or any desired Y: τ Y (Y) (4) where Y ( ) deends on the variances o D, which can be comuted using the exressions or ath and gate variances given above, rom underlying transistor level variances. This τ is the timing margin o an -gate ath, or the desired seciied yield Y. Thereore, in order to get the desired yield, the circuit should be designed to ass the timing constraints when D (j) τ, or all j. Thereore, we set D(i) τ/, and based on (42) we require: τ αl(i)+βv (i), i (49) This gives the range o ossible settings o L(i) andv (i) required to achieve a timing deviation o τ on -gate aths. I the circuit asses under these conditions, then the desired yield would be achieved. To simliy matters, suose we want the L(i) andv (i) settings to be the same multile o their individual s, i.e., let: L(i) L (i) V (i) δ, V (i) i (5) otice that this is easible (and δ>) because both α and β have the same sign (ositive). This leads to: Y (Y)/ δ (5) α L (i)+β V (i) This δ eectively deines the worst-case ile or which the circuit should be tested (simulated, or checked) or timing constraint violations, so as to guarantee that the timing yield is at least Y. 464

6 Timing Yield τ Figure 3: Timing yield lots, or k 3and APPLICATIO TO STATIC TIMIG We will now illustrate how the above timing yield model allows us to choose a setting or the transistor arameters so that a desired yield is achieved i the circuit asses traditional static timing analysis. For clarity, let all transistor-level variances be equal: dd,l 2 2 wds,l (x i,y i ) wdr,l 2 (i) 2 L /3, i, and dd,v 2 2 wds,v (x i,y i ) wdr,v 2 (i) 2 V /3, i. At the gate level, this leads to dd,d 2 α 2 L 2 + β2 V 2 /3, 2 wds,d (x i,y i ) α 2 L 2 + β2 V 2 /3, and 2 wdr,d (i) α 2 L 2 + β2 V 2 /3. Thereore, D 2 α 2 L 2 + β2 V 2. At the ath level, we have 2 dd,d D 2 2 /3, wds,d 2 (x j,y j )D 2 2 /3, and wdr,d 2 (j) 2 D /3, where the last equation is notable or the absence o the square actor. I we let 2 2 D 2 /3, then dd,d wds,d and wdr,d /, where the last exression is notable or the resence o the square root term. With this, the equations or timing yield become as ollows. In case,wehave: Z Y (τ) Φ (τ/) (k/ ) Φ (u) du (52) and in the general case we have: Φ((τ/) (k/ Z )) Y (τ) χ 2 [(τ/) (k/ ) Φ (u)] 2 du (53) Plots o Y (τ) or a ew values o are shown in Fig. 3, or k 3and 9. One can use this tye o igure as ollows. I 6 and we want 9% yield (i.e., Y.9), then it is clear rom the igure that we need τ 5, which leads to: 5 δ 3 qα 2 L 2 + β2 V 2 (54) α L + β V Let r (α L )/(β V ) then: 5 δ 3 +r 2 (55) +r I, or examle, r, then: δ (56) so that the circuit would need to be simulated (and its timing checked) with all its transistors L e and V t set at their +2 oints. otice that, since α and β deend on transistor siing, then (55) rovides a way in which δ can be controlled by circuit otimiation and/or rocess tuning. 7. COCLUSIO A method or statistical timing analysis has been develoed, based on a timing yield model. The model is a ull-chi model in that it can be alied with ease to large chis, beore layout. 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