Energy-aware optimisation for run-time reconfiguration

Transcription

1 Energy-aware otimisation for run-time reconfiguration Tobias Becker and Wayne Luk Deartment of Comuting Imerial College London, UK eter Y. K. Cheung Deartment of Electrical and Electronic Engineering Imerial College London, UK Abstract Run-time reconfiguration has been shown to roduce ower and energy efficient designs. However, it is imortant to take into account the energy overhead of the reconfiguration rocess itself. This aer resents an analytical model that covers the effects of ower consumtion and configuration seed of the reconfiguration rocess. Based on this model, a method is introduced that establishes the otimal degree of arallelism for designs suorting artial run-time reconfiguration. Our energy-aware aroach is illustrated by otimising designs for software-defined radio: a reconfigurable FIR filter is shown to be u to 49% more energy efficient and u to 87% more area efficient than a non-reconfigurable design. I. INTRODUCTION Energy efficiency is a crucial asect in battery-based mobile alications to maximise the battery life. Energy and ower efficiency is also imortant in systems that are connected to the grid. Lower ower leads to less heat, lower comlexity of ower sulies and cooling systems, and reduced energy and system costs. Reconfigurable devices such as FGAs are a romising technology to imlement fast evolving alications such as mobile communication. Raid develoment of communication standards with ever increasing bandwidth and comlexity requires alternatives to traditional aroaches relying on ASICs and DSs. The reconfigurability of FGAs can also be exloited to imrove ower consumtion. A circuit secialised to a certain condition can be more efficient than a general-urose design. Reconfiguration can be used to udate the circuit when the condition changes. However, the device will also consume ower during reconfiguration which can influence the overall efficiency. In this aer we study how ower consumtion during reconfiguration influences the overall efficiency of a reconfigurable alication in terms of its energy er comutation. Our key contributions are: A simle device-indeendent model based on alication, device and imlementation arameters that allows us to analyse the energy efficiency of a design. An analysis of how reconfiguration and the degree of arallelism in the design influence the energy efficiency. A method of design sace exloration to quickly identify an imlementation with maximum energy efficiency. A case study demonstrating our aroach. The rest of the aer is organised as follows. Section II resents the background and related research. Section III resents our model, the analysis of energy efficiency deending on reconfiguration and arallelism in the imlementation and our strategy for design sace exloration. Section IV exlains ractical asects of ower estimation and measurements. Section V demonstrates how our otimisation can be erformed on an examle, showing a reconfigurable FIR filter. Section VI concludes the aer. II. BACKGROUND FGAs allow fast alication develoment and ostdeloyment ugradeability, but their flexibility comes at the cost of area and ower overheads comared to ASICs. An FGA can be between 17 and 32 times less area efficient and between 7 and 14 times less ower efficient than an ASIC manufactured in the same technology [1]. FGA vendors continue to address ower challenges through rocess technology and architectural imrovements. Devices secifically otimised for low-ower oeration can show significant reductions in active and standby ower [2]. The reconfigurability of FGAs can be exloited to create secialised designs that imrove erformance, reduce area and reduce ower. It has been shown that run-time reconfiguration can imrove the functional density of a design [3]. The reconfigurable design becomes more efficient, the more data are rocessed between reconfigurations. Reconfigurable hardware can be emloyed in high-erformance comuting where comute-intensive tasks are offloaded into reconfigurable modules [4]. The reconfiguration overhead has to be carefully balanced against the hardware seed-u in order to archive good overall erformance. The erformance of a reconfigurable design can also be imroved by exloring the degree of arallelism in the imlementation [5]. The reconfigurability of FGAs makes them a articularly comelling architecture to realise software-defined radio alications [6]. There is extensive research on reconfigurable signal rocessing comonents: results include a reconfigurable FIR filter with 4% area reduction including a framework for fast run-time generation of new configurations [7] and a reconfigurable matched filter for UMTS with imroved configuration seed [8]. In another aroach, the reconfiguration time of an FIR filter is imroved by reducing the amount of logic that needs to be reconfigured [9].

2 A ower-otimised Viterbi decoder has been develoed that is reconfigured deending on the signal-to-noise ratio [1]. However, the ower associated with the reconfiguration rocess is not secifically addressed. The ower during the configuration rocess has been measured in a Xilinx Virtex-E FGA [11]. ower tends to ram u during initial device reconfiguration but remains fairly constant during run-time reconfiguration. It has also been shown that clock-aware lacement strategies can lead to ower reductions [12]. An imortant asect for the overall efficiency of a design is how reconfiguration overheads relate to imrovements made in a reconfigurable design. We can judge the overall efficiency of a design by the total amount of energy required for a certain comutation including reconfiguration. In the following we develo an energy-aware analysis that shows when a reconfigurable alication becomes more energy efficient than a standard one. Our aroach, insired by revious work [5], includes the exloration of arallelism for further energy otimisations in the reconfigurable design. This method is orthogonal to other low-ower otimisations based on device architecture or rocess technology. III. ENERGY OTIMISATION There are many alications that can benefit from reconfiguration and there are different oortunities of how reconfigurability can be exloited. We can classify the following scenarios: 1. re-deloyment. The reconfigurability of the device is used for fast rototying and develoment. It is ossible to make changes late into the design rocess. 2. In-field ugrade. A configuration roviding new features or bug-fixes is loaded into the device. In this case the device is usually rebooted. 3. Infrequent reconfiguration. The design uses run-time reconfiguration occasionally to adat to a new rocessing environment. In this case, the reconfiguration overhead is usually insignificant and may be hidden by the alication. A reconfigurable Viterbi decoder that adats to the signal-tonoise ratio is an examle of infrequent reconfiguration [1]. 4. Frequent reconfiguration. The design uses run-time reconfiguration frequently as art of the alication. The influence of the reconfiguration overhead on erformance and energy efficiency is significant and needs to be considered. Reconfigurable high-erformance comuting is an examle involving frequent reconfiguration [4]. The last scenario is the most challenging because reconfiguration overheads can have a significant imact. In the following we analyse how the energy efficiency can be imroved in such a scenario. We use several alication, imlementation and device arameters for our energy otimisation. Alication arameters are: Number of ackets or data items n that are rocessed between reconfigurations Number of rocessing stes s in the algorithm A reconfigurable imlementation is characterised by the following arameters: Area requirement of the imlementation A Amount of arallelism in the imlementation rocessing time t for one acket or datum Reconfiguration time t r ower consumed during rocessing Comutation ower c, a comonent of ower overhead o, a comonent of ower consumed during reconfiguration r Finally we use the following device arameters: Data throughut of the configuration interface φ config Configuration size er resource or unit of area Θ We consider two energy otimisation aroaches. In the first, we analyse the energy overhead of reconfiguration and identify when a reconfigurable design becomes more energy efficient than a non-reconfigurable one. In the second aroach we analyse how the degree of arallelism influences the energy efficiency. A. Energy efficiency in reconfigurable designs The energy required to rocess n data items in a nonreconfigurable imlementation is given by equation 2. Note that even a non-reconfigurable design might require a arameter reload between rocessing data sets. This can have an influence on its energy consumtion. E total = E + E load (1) = t n + load t load (2) The energy normalised er datum is given in equation 3. For ractical data set sizes n, it is often ossible to neglect the energy influence of the arameter reload. E total,n = t + load t load t (3) n For a reconfigurable design, the energy to rocess n data items is given as follows: E total = E + E r (4) = t n + r t r (5) The reconfiguration time t r can be calculated based on the area requirement A of a design: t r = Θ A φ config (6) Θ is a device secific constant and secifies the number of bytes required to configure a articular device resource. φ config is the configuration data rate and deends on the configuration interface and the configuration controller. We can normalise equation 5 to n: E total,n = t + r Θ A φ config n (7)

3 A reconfigurable design often has the benefit of consuming less rocessing ower and having higher erformance, i.e. lower t. A reconfigurable design is also smaller than a non-reconfigurable version. In order to be more energy efficient than the non-reconfigurable design, the savings in E must be larger than the overhead in reconfiguration energy E r. To kee E r low, it is imortant to reconfigure the smallest ossible area A with the highest available configuration seed φ config. Configuring between larger datasets n also increases the efficiency. B. Exloring arallelism We now consider how arallelism in the imlementation of a run-time reconfigurable design can influence its energy efficiency. Many algorithms can be scaled between a small and slow serial imlementation and a large and fast arallel imlementation. revious work demonstrates that the degree of arallelism can be used to otimise the erformance of a reconfigurable design [5]. We now erform a similar analysis for energy. The uer three diagrams in figure 1 illustrate three different temoral and satial maings of an algorithm with four stes, and the imlication on rocessing time, reconfiguration time and area. One rocessing element is characterised by t,e, the basic rocessing time er rocessing element, and t r,e, the basic reconfiguration time er rocessing element. The rocessing time t for one data item in an algorithm with s stes and an imlementation with arallelism is: t = t,e s arallelism seeds u rocessing of data but slows down reconfiguration. This is because a arallel imlementation will require more area than a sequential one, and reconfiguration time is directly roortional to area. The reconfiguration time t r of an imlementation with rocessing elements is therefore: (8) t r = t r,e (9) We now analyse the ower and energy consumtion in a reconfigurable design. Instead of static and dynamic ower, we consider ower comonents that scale with and comonents that remain constant. We consider rocessing ower to be a combination of comutation ower c and ower overhead o. We assume that each rocessing element incurs a certain comutation ower c,e. The comutation ower c is hence directly roortional to : c = c,e (1) The comutation energy E c for rocessing n data items is: E c = c,e t n = c,e t,e s n (11) The energy associated with comutation is indeendent of and is constant for an algorithm with given s and n. During rocessing, we will also find a ower overhead o that is not directly associated with comutation. This overhead may be static ower only. However, there can be further elements to this ower overhead e.g. the ower consumtion of auxiliary circuits such as clock managers. This ower comonent is constant and does not scale with. The energy overhead E o encountered during the rocessing of n data items is inversely roortional to : E o = o t n = o t,e s n (12) Finally, we have to consider the ower and energy consumed during the reconfiguration rocess. We assume that reconfiguration ower r is constant. For r we do not have to consider the ower overhead searately. Reconfiguration energy simly scales with reconfiguration time regardless of the distribution of its comonents. The reconfiguration energy E r grows with reconfiguration time t r, and is therefore roortional to : E r = r t r = r t r,e (13) The total energy for rocessing n data items is therefore: E total = E + E r = E c + E o + E r (14) = c,e t,e s n + o t,e s n + r t r,e (15) The total energy normalised to n is: E total,n = c,e t,e s + o t,e s + r tr,e n (16) Figure 2 shows the normalised energy er datum over for the arameters s = 128, n = 1,, t,e /t r,e = and o / r =.5. A variation of either n or t,e /t r,e with the factor a leads to different otima. Larger datasets or higher rocessing time to reconfiguration time ratios (faster reconfiguration) ush the otimum towards more arallel imlementations. Smaller data sets or slower reconfiguration shift the otimum to a more serial solution. In order to find the otimal degree of arallelism that minimises the energy er datum, we calculate the artial derivative of equation 16 with resect to : E total,n = o t,e s 2 + r t r,e n (17) To find the minimum we set equation 17 to and solve for : o t,e s n ot = (18) r t r,e

4 t t = 4 = 2 = 1 t t r,e t,e t,e A, t r A, t r A, t r c,e c t r,e c c o t t r r t r r o o t t r t t t r t Figure 1. Different temoral and satial maings of an algorithm with s = 4. The uer diagrams show rocessing time, reconfiguration time and area. The lower diagrams show the influence of on ower for n = 1. We have to minimise the energy reresented by the grey rectangles. The result ot is usually a real number which is not a feasible value to secify arallelism. One should choose a value which divides s and is close to ot. If 1, then a fully serial imlementation is the most efficient and for s, a fully arallel imlementation is the most efficient. This otimisation is indeendent of comutation ower c. It balances the energy associated with the ower overhead o and the energy associated with reconfiguration ower r. Grahically this corresonds to reducing the combined area of the grey rectangles in figure 1. The area of the white rectangles is constant. C. Otimisation stes In the revious section we describe how a variation in the degree of arallelism of the imlementation can be used to otimise a design for energy. This effect may be observed in many designs that require several similar rocessing stes E a=.1 a=.1 a=1 a=1 a=1 Figure 2. Normalised energy er datum for arameter variations of dataset size n, or the rocessing to configuration time ratio t,e/t r,e. such as multily-accumulate oerations in digital filters, butterfly oerations in FFTs or substitution boxes in encrytion. When develoing several imlementations with varying degrees of arallelism, design arameters may not scale exactly as assumed reviously. For examle, some designs may incur an area overhead for serial imlementations while in other cases, arallelising a design may cause an area overhead. It is ossible to erform an otimisation by simly building and measuring designs for all ossible variations of. However, this will require a long time. Instead, we can use equation 18 to quickly exlore the design sace based on arameters derived from just one imlementation. Even if arameters do scale not exactly as assumed, our exloration will still indicate where the otimum can be found. After determining ot using equation 18, we imlement a new design with a ractical value close to ot. We then measure its arameters and check the resulting energy efficiency. If the design is less efficient than redicted, has to be moved closer to the value of the original imlementation. If the design is more efficient, then can be moved further out. Our exloration can be summarised by the following 8 stes: 1) Derive s and n from alication. 2) Obtain Φ config and Θ for target device. 3) Imlement one design and determine t, A, r and. 4) Calculate t r, t,e and t r,e using equations 6, 8 and 9. 5) Find ot from equation 18 and determine a ractical value for. 6) Build design for. 7) Verify if design matches redicted arameters. 8) If necessary refine result by moving u or down.

5 If a design scales well, then the above method will find the otimum right away. If arameters vary, a reiteration of stes 6 and 7 may be necessary. This is still considerably less effort than building all ossible design variations. IV. OWER MEASUREMENTS Our otimisations can be erformed based on ower estimation tools or ower measurements. ower estimation tools offer a fast and simle way of determining the ower consumtion of a design, but may be limited in accuracy. ower estimation tools usually also lack suort for reconfiguration ower. ower measurements are more accurate but require a target board with ower measurement facilities as well as adequate measuring equiment. rocessing ower may be calculated with reasonable accuracy using ower estimation tools. With ower estimation tools it is also straightforward to identify comutation ower c and the ower overhead o caused by static ower and additional non-reconfigurable circuits. For ower measurements, o can be determined by building a design with all comonents that are not affected by reconfiguration and measuring its ower consumtion. This design should include clock managers running at their targeted clock rate. Xilinx ower estimation tools currently do not suort ower estimation for artial reconfiguration. Reconfiguration ower r has therefore be measured on the board. FGA ower measurements can be obtained by measuring the current in the device suly rails. However, wiring a multimeter directly into the suly rails may not be a suitable measurement technique. FGAs are sensitive to core voltage variations. For examle, Xilinx Virtex-5 FGAs have to stay within 5 mv of the secified core suly voltage of 1 V. The voltage dro over the internal shunt resistor in a multimeter can easily exceed this limit if higher currents are drawn. Instead it is referable to insert a recision current sense resistor with a small enough resistance into the suly rail and measure the voltage dro over the resistor. All our exeriments are imlemented on the Xilinx ML55 board and ower results are based on FGA core current measurements. The ML55 board does not rovide core current measurement facilities as a standard feature. The board was therefore modified by inserting a recision current sense resistor between the voltage regulator and the FGA core suly rails. We measure the voltage dro across the resistor with a digital storage oscilloscoe. V. CASE STUDY In software-defined radio we can identify many comonents that can benefit from reconfiguration. Examles are FIR filters, FFTs, correlators, the CORDIC algorithm and error correction such as Viterbi or Turbo codes. These basic blocks are used in different communication standards with varying arameters [13] and may require reconfiguration. These comonents also offer the oortunity to exlore the degree of arallelism in their imlementation. We demonstrate our otimisations on the examle of a reconfigurable FIR filter. FIR filters are used in many stages of a radio receiver or transmitter and may require some form of modification. Examles of filter modifications are coefficient reloading to change the filtered frequency band, or temlate reloading in a matched filter. A flexible filter can be imlemented as a non-reconfigurable filter that rovides additional circuitry to reload arameters into the design. As an alternative, the filter can be reconfigurable where each instance is secific and otimised to one set of arameters. A filter modification is then carried out through run-time reconfiguration. In the following, we first analyse the energy efficiency of a reconfigurable filter and comare with a nonreconfigurable counterart. In the second art of our case study, we exlore how the degree of arallelism can be used to further imrove energy efficiency. We erform our analysis on the examle of an 8-ta FIR filter that has to rocess 1, 16-bit samles between arameter udates. Our exeriments are conducted on the Xilinx ML55 board which contains a Virtex-5 XC5VLX5T FGA. Virtex-5 FGAs contain an internal configuration access ort (ICA) which can rovide a maximum configuration throughut of φ config = 4MB/s. ICA can be used in the HWICA core [14] in combination with a Micro- Blaze softcore rocessor to control reconfiguration. When using this core, we measure a configuration throughut of only 5M B/s. However, Claus et.al. recently resented an imroved ICA controller that rovides a throughut of 3M B/s [15]. In Virtex-5 FGAs, the configuration size er unit of area is Θ CLB = 295.2bytes/CLB or Θ LUT = 36.9bytes/LUT [16]. A. Comaring reconfigurable and non-reconfigurable designs We imlement our 8-ta FIR filter in a reconfigurable and a non-reconfigurable version. The filters are designed in VHDL and synthesised with Xilinx XST 11 synthesis tools using IEEE arithmetic libraries. The non-reconfigurable filter rovides a ort to reload filter coefficients. Coefficients are loaded into a register chain and a reload requires 8 clock cycles. The reconfigurable filter contains hardcoded coefficients. The synthesis tools use this to create otimised fixed-coefficient multiliers. We imlement one reconfigurable version of the design with an embedded configuration controller based on a MicroBlaze rocessor and the HWICA core. This system creates an overhead in terms of logic utilisation and ower. We also create a second version of the reconfigurable design based on an external configuration controller. No logic and ower overhead is added to the design. Even though an external controller will add some general overhead to the system, it could still be a lot more efficient than a MircoBlaze-based rocessor system. This scenario can be considered the best case in energy efficiency.

6 LUTs f max t [ns] [W ] E [µj] r[w ] t r[µs] E r[µj] E total [µj] reconfigurable, MB, φ config = 5MB/s reconfigurable, MB, φ config = 3MB/s reconfigurable, ext, φ config = 5MB/s reconfigurable, ext, φ config = 3MB/s non-reconfigurable, 8 cycle coeff reload note 1: total size of design including MicroBlaze, only 9452 LUTs are reconfigured note 2: f max alies to FIR, not MicroBlaze note 3: coefficient reload instead of reconfiguration Table I COMARISON OF A NON-RECONFIGURABLE DESIGN WITH RECONFIGURABLE DESIGNS USING AN INTERNAL MICROBLAZE CONFIGURATION CONTROLLER (MB) AND AN EXTERNAL CONFIGURATION CONTROLLER (EXT). ALSO SHOWN ARE FAST AND SLOW CONFIGURATION SEEDS. Table I shows the arameters of our three designs. The MicroBlaze-based reconfigurable design requires less than half of the logic resources than the non-reconfigurable version. The MicroBlaze system also requires some BRAM resources which are not shown in this comarison. The reconfigurable design with external reconfiguration requires 64% less logic resources than the non-reconfigurable design. The maximum clock frequency also increases from 1 MHz to 182 MHz. The rocessing ower is reduced by 6% for the MicroBlaze-based design and by 64% for the design with external reconfiguration. Area and ower savings and the erformance increase can be exlained given the fact that more efficient fixed-coefficient multiliers are used in the reconfigurable design. These imrovements lead to significant reductions in the rocessing energy. However, reconfiguration can incur an energy enalty that may offset the imrovements in rocessing energy. Table I shows the total energy to rocess 1, samles in our reconfigurable designs for two different reconfiguration seeds. The slow seed of 5M B/s corresonds to what can be achieved with an unotimised HWICA core, and the fast seed of 3M B/s corresonds to what has been demonstrated in [15]. The results show that slow configuration leads to significant energy enalties that make the reconfigurable designs less efficient than the non-reconfigurable ones. Even the MircoBlaze design with fast reconfiguration is less efficient than the design without reconfiguration. However, the design with external reconfiguration is 19% more energy efficient. Figure 3 shows the normalised energy efficiency of our designs over a range of data set sizes. For large data sets, all reconfigurable designs aroach an energy of 6.8nJ/samle. This is 5 times more efficient than the non-reconfigurable design with 34.3nJ/samle. However, slow reconfiguration seeds as well as energy overheads caused by the reconfiguration controller lead to fast deterioration of energy efficiency for smaller data sets. To obtain imrovements in energy efficiency through reconfiguration, it is imortant to develo reconfiguration mechanisms with high seed and low ower overhead. B. Exloring arallelism We now demonstrate how our design exloration method can be used to further otimise the design. As ste 1, we determine the alication arameters as s = 8 and n = 1,. For Viretx-5 with fast reconfiguration, we obtain φ config = 3MB/s and Θ LUT = 36.9bytes/LUT (ste 2). We use the reconfigurable design with external configuration as initial imlementation. This design is fully arallel, i.e. = 8. The ower overhead o = 35mW is measured on a configured device with clock managers running but without any FIR logic, and t, A and r are obtained from table I (ste 3). As ste 4, we calculate the rocessing time er element as t,e = 5.49ns using equation 8, and the reconfiguration time er element as t r,e = 14.5µs using equation 6 and 9. Using equation 18 we can calculate ot = 24.1 (ste 5). We choose = 2 as a ractical value. According to equation 16, we redict the energy for this design to be 17.8nJ/samle. We now build a design for = 2 and obtain its arameters (ste 6). Table II shows circuit size, maximum clock rate, time and energy arameters for designs with ranging from 8 down to 5. This is for illustration uroses; not all E [nj/samle] E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 n non-reconf reconf, fast, ext reconf, fast, MB reconf, slow, ext reconf,slow, MB Figure 3. Energy efficiency over dataset size n for MicroBlaze (MB) and external (ext) reconfiguration and with various configuration seeds.

7 VHDL design CoreGen design LUTs f max t,e t r,e E,n E r,n E total,n LUTs f max t,e t r,e E,n E r,n E total,n [mw ] [ns] [µs] [nj] [nj] [nj] [mw ] [ns] [µs] [nj] [nj] [nj] Table II VHDL AND COERGEN IMLEMENTATIONS OF THE RECONFIGURABLE FIR FILTER FOR VARIOUS AND A DATASET SIZE OF n = 1,. E [nj/samle] E total,n E,n E r,n LUTs area E [nj/samle] E total,n E,n E r,n LUTs area Figure 4. Energy efficiency and area for different levels of arallelism in VHDL imlementation. Figure 5. Energy efficiency and area for different levels of arallelism in CoreGen imlementation. of these designs would be built when using our method. A breakdown of the energy comonents and circuit size is also illustrated in figure 4. For = 2, we find that E total,n = 37.2nJ/samle (ste 7). This is worse than exected and can be exlained with the fact that the clock frequency dros and that circuit size does not scale as well as exected. As ste 8, we move back closer to the original value and try = 4. For this value we do find an otimum. The design uses 26.5nJ/samle which is 5% less than the fully arallel design and 23% less than the original nonreconfigurable design. The design with = 4 requires 6278 LUTs which is 34% less than the fully arallel design and 76% less than the original non-reconfigurable design. We now reimlement the same reconfigurable filter with Xilinx CoreGen. Filters are imlemented using distributed arithmetic and fixed coefficients. arallelism cannot be directly secified in CoreGen, but it can be imlied by setting clock rates and data rates accordingly. We first build a fully arallel version of the design and erform our otimisation again from ste 3. Table II shows that the fully arallel version requires more area and ower and is less energy efficient than the comarable VHDL imlementation. The ower overhead for this design is measured as o = 356mW and we calculate t,e = 3.33ns and t r,e = 18.5µs. All other arameters are identical to the revious case. Using E [nj/samle] n=1 n=1, n=1, n=1, Figure 6. Energy efficiency for different levels of arallelism and various data set sizes n in CoreGen imlementation. equation 18, we calculate ot = A ractical value for is 16. However, CoreGen can only efficiently generate designs where arallelism is reduced by owers of 2. We therefore choose the closest ractical value = 2. Using equation 16 we calculate the energy for this design to be 16.7nJ/samle. The real energy according to table II is 17.7nJ/samle which is close to what we exect. The design with = 2 is indeed the otimal design and requires 47% less energy than the fully arallel CoreGen design and

8 49% less energy than the original non-reconfigurable design. The design with = 2 has a size of 3321 LUTs which is 72% less than the fully arallel CoreGen version, and 87% less than the original design. Table II shows that the CoreGen design scales better than the revious VHDL imlementation. The clock rate remains constant and the circuit size scales roortionally to. This causes the CoreGen design to become more efficient than the VHDL version as is reduced. A breakdown of the energy efficiency is illustrated in figure 5. The revious analysis considers a fixed dataset size of n = 1,. Figure 6 shows the efficiency of the CoreGen design when the dataset size varies. For a dataset size of 1, a fully serial imlementation is the best choice for a reconfigurable design. However, in our case this is 15% less energy efficient than the non-reconfigurable design. Larger dataset sizes ush the otimum to fully arallel imlementations which are all more energy efficient than the non-reconfigurable design. VI. CONCLUSION We analyse the energy efficiency of reconfigurable and non-reconfigurable designs including the overhead caused by reconfiguration. Our analysis is based on a simle analytical model that allows us to evaluate the energy efficiency based on a set of alication, device and imlementation arameters. Using our model we can erform a fast design-sace exloration to identify the most efficient imlementation without building and measuring all design variations. We conduct a case study of a reconfigurable FIR filter and show that fast reconfiguration seeds and low-ower reconfiguration are essential to making reconfigurable designs beneficial. We also evaluate how changing the degree of arallelism in the imlementation can influence the overall energy efficiency. A CoreGen imlementation scales exactly as assumed in our model, and our model is also useful for a VDHL imlementation that scales less well. A refinement of the results leads us to the otimal solution. Current and future work includes studying the effect of this otimisation on a wide range of alications, as well as automating our energy-aware aroach. ACKNOWLEDGEMENTS The suort of Xilinx, UK ESRC and F7 HiEAC is gratefully acknowledged. REFERENCES [1] I. Kuon and J. J Rose, Measuring the ga between FGAs and ASICs, IEEE Transactions on Comuter-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, , Feb. 27. [2] T. Tuan, A. Rahman, S. Das, S. Trimberger, and S. Kao, A 9-nm low-ower FGA for battery-owered alications, IEEE Transactions on Comuter-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, , Feb. 27. [3] M. Wirthlin and B. Hutchings, Imroving functional density using run-time circuit reconfiguration, IEEE Transactions on VLSI Systems, vol. 6, no. 2, , [4] E. El-Araby, I. Gonzalez, and T. El-Ghazawi, Exloiting artial runtime reconfiguration for high-erformance reconfigurable comuting, ACM Transactions Reconfigurable Technology and Systems, vol. 1, no. 4,. 1 23, 29. [5] T. Becker, W. Luk, and. Y. K. Cheung, arametric design for reconfigurable software-defined radio, in ARC 9: roceedings of the 5th international worksho on Reconfigurable Comuting. Sringer, 29, [6] M. Cummings and S. Haruyama, FGA in the software radio, Communications Magazine, vol. 37, no. 2, , Feb [7] K. Bruneel, F. Abouelella, and D. Stroobandt, Automatically maing alications to a self-reconfiguring latform, in Design, Automation and Test in Euroe. IEEE, 29, [8] I. Kennedy, A dynamically reconfigured UMTS multichannel comlex code matched filter, in Field-rogrammable Technology. IEEE, 25, [9] A. H. Gholamiour, H. Eslami, A. Eltawil, and F. Kurdahi, Size-reconfiguration delay tradeoffs for a class of DS blocks in multi-mode communication systems, in Field- rogrammable Custom Comuting Machines, Annual IEEE Symosium on. IEEE Comuter Society, 29, [1] R. Tessier, S. Swaminathan, R. Ramaswamy, D. Goeckel, and W. Burleson, A reconfigurable, ower-efficient adative Viterbi decoder, IEEE Transactions on VLSI Systems, vol. 13, no. 4, , 25. [11] J. Becker, M. Hübner, and M. Ullmann, ower estimation and ower measurement of Xilinx Virtex FGAs: trade-offs and limitations, in 16th Symosium on Integrated Circuits and Systems Design, SBCCI 23. IEEE Comuter Society, 23, [12] J. Lamoureux and S. J. E. Wilton, On the trade-off between ower and flexibility of FGA clock networks, ACM Transactions Reconfigurable Technology and Systems, vol. 1, no. 3,. 1 33, 28. [13] W. Tuttlebee, Software Defined Radio: Enabling Technologies. Wiley, 22. [14] Xilinx Logic Core: OB HWICA, Xilinx Inc., July 26. [15] C. Claus, B. Zhang, W. Stechele, L. Braun, M. Hübner, and J. Becker, A multi-latform controller allowing for maximum dynamic artial reconfiguration throughut, in Field rogrammable Logic and Alications. IEEE, 28, [16] Virtex-5 Configuration Guide v2.1, Xilinx Inc., October 26.