Synthesis of Moore FSM with Expanded Coding Space

Transcription

1 Volume 3 Issue, January 24 Synthesis of oore FS with Exanded Coding Sace Olena Hebda, Larysa Titarenko Institute of Comuter Engineering and Electronics University of Zielona Góra Zielona Góra, Poland OShaoval {at} weituzzgoral Abstract The roosed method is targeted on reduction of hardware amount in logic circuit of oore finite-state machine imlemented with rogrammable logic arrays (PLA) The method is based on using more than minimal amount of variables in codes of FS internal states The method includes two stages of state encoding The second stage is connected with recoding of states inside each class of seudoequivalent states An examle is given for roosed method alication Keywords- oore FS, grah-scheme of algorithm, seudoequivalent states, PLA, logic circuit I INTRODUCTION A control unit is a very imortant block of any digital system The model of oore finite state machine (FS) [8] is often used during the digital control systems realization [, 5] One of the imortant roblems of FS synthesis is the decrease of chi sace occuied by FS logic circuit Solution of this roblem allows decreasing the ower consumtion and increasing the clock rate oreover it could hel the develoing industry, for examle in Polish Lubuskie Province, because in this case the manufacturers will be able to roduce much more cometitive roducts The methods of solution of this roblem deend strongly on logic elements used for imlementing the FS logic circuit [2, 8] In this article we discuss the case when rogrammable logic arrays (PLA) are used for imlementing oore FS logic circuit The PLAs were introduced in 97s, they were a very oular base for the logic design [2] As it is mentioned in [3], successful comutation structures return back at the next round of the technological siral Now the return of PLA basis can be observed in the hybrid FPGAs [7], as well as in CoolRunner CPLD by Xilinx [22] Also, the PLAs are very oular in the modern sublitograhic technology [] In the nanoelectronics, these devices are named nano-plas Nowadays, extensive research is conducted in the fields connected with nano-plas [3, 6] In the case of alication-secified integrated circuits (ASIC) [2], the combinational logic is very often imlemented using so called matrix structures where the rincile of distributed logic is used [4] Two matrix structures combined together form a PLA [] So, the PLA basis is still oular in the logic design It means that new design methods should be develoed for area reduction of PLA-based control units In this article, a new design method is roosed targeting the area reduction of PLA-based oore FS s logic circuit In this article a control algorithm to be imlemented is reresented by a grah-scheme of algorithm (GSA) [] The roosed method can be viewed as a develoment of the method [6] II PRELIINARIES AND RELATED WORK Let oore FS be reresented by the structure table (ST) with columns []: a m, K a m, a s, K a s, X h, h, h Here a m is the initial state of FS; K a m is the code of state a m A have caacity R log 2, to code the states the internal variables from the set T T,,T R are used; a s, K a s are the state of transition and its code resectively; X h is the inut, which determines the transition a m, as, and it is equal to conjunction of some elements (or their comlements) of a set of inut variables X x,,x L ; h is the set of inut memory functions for fli-flos of FS memory, which are equal to to change the content of the memory from K a m to K a s, h,, R ; h, H is the number of transition In the column a m a collection of outut variables Y q is written These outut variables are generated in the state a m A ( Yq Y y,, y N, q,, Q ) This table is used to form the following system of functions T,X T Y Y The systems () (2) determine an FS logical circuit In the case of PLA-based oore FS, the logic circuit includes wwwijcitcom 3

2 Volume 3 Issue, January 24 two PLAs: a Core PLA (CPLA) and an Outut PLA (OPLA)In this model, CPLA imlements the system (), a register RG kees state codes, OPLA imlements the system (2) The roblem of FS synthesis with PLAs was thoroughly investigated in 7s [9] Two main directions of design were discussed The first of them was the minimization of a number of standard PLA chis imlementing an FS circuit [4] The second grou of methods targeted the minimization of the COS VLSI area occuied by an FS logic circuit [2] To solve the first roblem, the algorithms of state assignment were used [9, 2], as well as different methods of decomosition [3] To solve the second roblem, the encoding of inut and outut variables were used [2] Nowadays, the last grou of methods is used in otimizing the nano-pla designs [3] Their aroach leads to the Six atrix (S) imlementation of ealy FS discussed in [3] The same aroach can be used for the case of oore FS The systems () (2) can be imlemented using only two matrices The first of them (AND-matrix) imlements the roduct terms of the systems The second matrix (OR-matrix) imlements the functions But this solution leads to the FS circuits with the highest ossible area The six matrix solution [3] leads to the rather slow FS circuits So, in this article we discuss the Four atrix (F) imlementation of a oore FS This model is shown in Fig It can be treated as a comromise between the economical but slow S model and the fast but redundant two matrices model Let us denote the F model of oore FS as an FS U Let us analyze the comonents of matrix circuit shown in Fig A conjunctive matrix T imlements the system of terms F { F,,FH } ; a disjunctive matrix T 2 imlements system (); a conjunctive matrix T 3 imlements terms A m m,, corresonding to FS states; a disjunctive matrix T 4 imlements system (2) The register RG kees state codes; it is controlled by ulses Start (clearing) and Clock (changing content deending on functions ) The matrices T and T 2 determine the CPLA, whereas the matrices T 3 and T 4 determine the OPLA Unfortunately, as a rule, oore FS has more states then an equivalent ealy FS [] It leads to the fact that the number H is much more than the number of rows H of ST for an equivalent ealy FS Let be the number of states of equivalent ealy FS and R is defined as Then the following relations are true for ractical cases: H H ; R log R 2 The hardware amount is determined for the matrix circuits as a chi area occuied by an FS s circuit [2] Comlexity of each matrix is defined by the area S T i of a chi demanded for its imlementation ( i, 4 ) In theoretical articles this area is defined in conventional units [2] The following estimations can be obtained for FS U : S( ) 2( L R )H ; S( 3 ) 2R ; S( S( 4 2 ) HR; ) N The area S U that is occuied by logic circuit of FS U is defined as a sum of the areas (5) Because of relations (4), the chi area occuied by the circuit of oore FS always exceeds this value for an equivalent ealy FS There are a lot of methods targeting hardware reduction of oore FS circuit [2, 8] But they deal with either CPLD or FPGA chis Because of it, they cannot be directly used in the case of PLA-based oore FS Taking it into account, we roose new method targeting PLA-based oore FS The roosed method can be viewed as a develoment of the method [6] One of oore FS features is existence of seudoequivalent states [5], which are the states with the same transitions by the effect of the same inuts [] There are two main otimization methods [5] based on the existence of seudoequivalent states: method of otimal state assignment and method of transformation of the states codes Let us find the classes of seudoequivalent states B i ( i, I ) for a given set A These classes define a artition A B,, B I for the set A Let us oint out that I [5] ethod of otimal state assignment Let us construct the following system of equations for some oore FS: i B C A i, I m im m R log 2 Figure atrix circuit of oore FS U In (), the Boolean variable C im if a m B i Let us execute the state assignment for a given FS In the case of the otimal state assignment, the system (6) has exactly I roduct terms It is ossible if the following statement is true for each class B i A: the codes K a m belong to a single generalized interval of R -dimensional Boolean sace It leads to oore FS U 2 The structures of both U and U 2 are the same But in U 2 the matrix T roduces only H H2 H terms wwwijcitcom 32

3 Volume 3 Issue, January 24 However, such an encoding that leads to H2 H is not always ossible [] The well-known algorithm JEDI [5] can be used for the otimal state assignment ethod of transformation of the states codes The classes B i A are encoded by the binary codes K B i with R B log 2 I bits The variables r are used for such an encoding, where RB Next system of functions is formed T The system (7) secifies the law of transformation of the codes K a m into the codes K B i The structure table is transformed in such a way that the states am B i are relaced by the classes Bi A in the column of resent state Such an aroach allows to decrease the number of rows of ST to H, whereas the number of feedback variables is reduced to R B R This aroach leads to a oore FS U 3 with a code transformer (CT) The number of transitions of the oore FS U 3 is equal to H The drawback of U 3 is the existence of a block of the code transformer that consumes additional resources of a chi III THE BASIC IDEA OF A PROPOSED ETHOD Let us execute the state assignment in the following way If am B i, then the codes K a m include the codes K B i It means that the codes K B i are reresented by some variables T r T', where T' T It results in oore FS U 4 whose structure is the same as the structure of oore FS U (Fig ) The roosed aroach guarantees the reduction of the number of terms in the system u to H It leads to reducing area of matrix T, as well as the number of inuts for matrix T2 T2 Unfortunately, this aroach does not ermit the terms reduction in system (2) Let us reresent the coding sace as a Karnaugh ma having I K columns, where I 2 K R B Let Bi i and B max(,, I ), then the ma should have O 2 K R R log 2 B If condition (9) is true, then the states for any class Bi A are laced in the same column of the ma and the code K( B i ) is determined by the values of variables marking this column If the following condition R B R R takes lace, then the exansion of encoding sace occurs The value of condition true: R can be decreased if the following is I K I In this case u to ( I K I ) classes B i can be laced in adjacent cells of the ma Let us discuss the following examle with the artition П A { B,, B 5 },where B { a }, B 2 { a 2,a 3,a 4,a 5,a 6 }, B3 { a7,a8,a9,a }, B4 { a,a2,a3,a4,a5 }, B5 { a6,a7 } Now, there is R B 3, B 5 and R 3 Therefore, it is enough R B R 6 variables to encode the states But the ma includes I K 8 columns and condition (2) is true Obviously, those classes Bi A having the maximum number of states should be transformed Let us 2 reresent the class B 2 as B 2 { a2,, a5 } and B2 { a6 }, 2 whereas the class B 4 as B 4 { a,, a4 } and B4 { a5 } Now there are B 4, R 2 and variables T,, T5 are used for state encoding (Fig 2) As follows from Fig 2, there is one code for each class Bi A, namely: K( B ) *, K( B2 ) *, K ( B 3 ), K( B 4 ) *, K( B 5 ) * In this case there is R B R 5, so there is no code sace exansion T T 2 T 3 T 4 T 5 a a 2 a 6 a 7 a a 5 a 6 * * a 3 * a 8 a 2 * a 7 * * a 4 * a 9 a 3 * * * * a 5 * a a 4 * * * Figure 2 The codes of states for oore FS U 4 rows, where wwwijcitcom 33

4 Volume 3 Issue, January 24 IV PROPOSED DESIGN ETHOD The roosed design method includes the following stes: Constructing the marked GSA and the set of states A 2 Construction of the artition A 3 Primary state assignment 4 Secondary state assignment 5 Construction of the transformed structure table 6 Imlementation of FS matrix circuit Let us discuss some stes of the roosed method Primary state assignment This ste is connected with finding values of I K and O K Here the ossibility of decreasing R under keeing R B is analyzed This ste is reduced to the lacement of states am B i inside the columns of Karnaugh ma having the size IK O K It allows finding the set T' T and codes K B i Secondary state assignment This ste is connected with otimizing system (2) Let us reresent equations of system (2) as the following ones: y n V CnmAm n, N m In (3) the symbol C nm stands for the Boolean variable equal to if the outut variable y n Y is generated in the state a m A States am B i are rearranged in the column K( B i ) to decrease the number of terms in system (3) The don t care cells of the ma are used for this otimization Construction of transformed structure table This table is constructed using the system of generalized formulae of transitions [], which is the following one: H Bi V ih XhAs hc i, I In (4), the Boolean variable C ih, if the term X h A s belongs to the system of transitions for the class Bi A This system is constructed using initial GSA The transformed structure table includes the columns B i, K( B i ), a S, K( a S ), X k, k, h The rows of this table corresond to the terms F h F : RB l Fh ( T ri r )* Xh r h, H In (5), the first art is determined by the code K( B i ) from the row h, whereas the value of l ri {,,*} is the value of code bit r; T r Tr,Tr Tr, Tr, where r,rb The terms (5) belong to functions D r H h rh * h D r Ф, where: V C F r,r B R In (6), the Boolean variable C, iff the row h contains function D r Ф ( h, H ) Imlementation of FS matrix circuit Let us analyze the matrices from the circuit shown in Fig The matrix T imlements terms (5); it has I 2( L RB ) inuts and O H oututs The matrix T 2 imlements functions (6); it has I2 H inuts and O2 R B R The matrix T 3 imlements terms (3); it has I 3 inuts and O 3 oututs deending on outcome of the secondary encoding stage ( I3 2 ( RB R ),O3 ) If some functions y n Y are reresented by a single term, then they are formed directly by the matrix T 3 It decreases the number of inuts for T 4 from N to The lower bound corresonds to the situation when all outut variables are formed by the matrix T 3 In the general case the matrix T 4 has I4 inuts and O4 N oututs Therefore we can find for matrices T and T 2 : rh S( T ) 2( L RB )H; S( T ) ( R R )H 2 B In the worst case the area of matrices T 3 and T 4 is defined as S( T3 ) 2( RB R S( T ) N 4 ) ; Thus the roosed aroach guarantees reduction of area that occuied by matrices T and T 2 due to equality of terms in the system of inut memory functions of oore FS to the equivalent ealy FS The area of matrices T 3 and T 4 can be otimized due to secondary state encoding It can be done using "don't care cells" of Karnaugh ma wwwijcitcom 34

5 Volume 3 Issue, January 24 V ANALYSIS OF THE PROPOSED ETHOD Hardware amount for imlementation of oore FS logic circuit deend on characteristics of GSA such as number of condition vertices, outut variables and other Let us use the robabilistic aroach suggested by [] and develoed in [7] There are three key oints in such an aroach: The use of a class of flow charts instead of a articular flow chart This class is characterized by the arameters and 2 Let Q be the number of vertices in GSA ; Q be the number of oerator vertices in GSA ; Q 2 be the number of conditional vertices in GSA Q Q 2 (res 2 ) is the robability of the event that a articular node of the flow chart is an oerational (res conditional) one 2 The use of matrix realization for the circuit of the control unit [2] instead of the standard VLSI In this case we can determine a hardware amount as the volume of matrices for a given circuit of the control unit 3 The use of relative characteristic instead of absolute one Let us study of the relation S(Ui ) S(U j ), where S(Ui, j ) is the volume of matrices for the imlementation of the circuit of the control unit U i, j Let us use the results of [2, 7], where estimation of the main FS arameters are exressed as function of GSA features and some coefficients: H Q H Q Q ; L ( 3 3 ; ; )Q 4 Here Q is the number of COV, 3 Q Q { ; 2}, Q L { ; 2} 4 2 Let us analyze method of otimal state encoding The area of U 2 is defined as S(U2 ) S( T ) S( T2 ) S( T3 ) S( T4 ) kh Here k, 2; ; 8, 3R 2L 2R N is efficient factor of otimal state encoding method [5] Using equations (9) we can find SU 2 f,q,3,4,n,k Final equation is lengthy and low-informative for readers therefore we don t show it here In the same way we can find SU 4 f,q,3,4,n, 5, where 5 is a factor of distribution states inside classes of seudoequivalent states ( B will ossess a minimal ossible value if 5 ) Figure 3 Comarison of model U 2 and U 4 The analyses of different GSA shows that Q,, and N Let N 2 ; 5; Let us research function S(U4 ) S(U2 ) Some results of investigation are shown in Fig 3 (, 2, 3, ; 4 ; N 2 ; 5, 6 ) Our investigations show that oore FS U 4 always offers gains in the area comared with oore FS U 2 This gain goes u with increasing the number of the vertices of the initial GSA The best results (u to 4424%) are achieved for flow charts with the number of vertices 5 Q However efficiency of method decreases by 2 8 % with rising values of arameters N,, 5 VI CONCLUSION The roosed method of exansion of encoding sace targets on decrease in the chi sace occuied by the matrix circuit of oore FS This aroach guarantees the decrease for the number of terms in the system of inut memory functions of oore FS u to this value of the equivalent ealy FS It allows decreasing for the chi sace used for imlementing the outut variables But to imrove the outcome of this aroach, it is necessary to work out an efficient method of the secondary state assignment The results of our investigations show that the roosed method is more effective for GSA with number of vertices more than 5 However gain is slightly decreased with rising numbers of outut variables, arameters and 5 The further direction of our research is connected with alication of roosed methods for the cases when FS logic circuits are imlemented using such standard elements as CPLD and FPGA The co-author Olena Hebda is a scholar within Submeasure 822 Regional Innovation Strategies, easure 82 Transfer of knowledge, Priority VIII Regional human resources for the economy Human Caital Oerational Programme cofinanced by Euroean Social Fund and state budget wwwijcitcom 35

6 Volume 3 Issue, January 24 REFERENCES [] S Baranov, Logic and system design of digital systems, Tallinn: TUT Press, 28 [2] SBaranov, Logic synthesis for control automata, Norwell, A, USA: Kluwer Academic Publishers, 994 [3] S Baranov, I Levin, O Koren, Karovski Designing fault tolerant FS by nano-pla, in Proceedings of the 5th IEEE International On- Line Testing Symosium; 29, Sembra-Lisbon, Portugal, [4] A Barkalov, D Das Otimization of logic circuit of microrogrammed ealy automaton on PLA, Automatic Control and Comuter Sciences; vol 25, No 3, 9 94, 99 [5] A Barkalov, L Titarenko, Logic synthesis for FS-based control units Lecture notes in electrical engineering Berlin: Sringer Verlag Heidelberg, 29, no 53 [6] A Barkalov, L Titarenko, O Hebda atrix imlementation ofoore FS with exansion of coding sace, easurement, Automation and onitoring,vol 56, No 7, , 2 [7] A Barkalov, Synthesis of Control Units on Programmable Logic Devices DNTU, Donetsk, 22, in Russian [8] G Deicheli, Synthesis and otimization of digital circuits NY: cgraw-hill, 994 [9] G Deicheli, R Brayton, A Sangiovanni-Vincentelli Otimal state assignment for finite state machines, IEEE Trans on CAD, vol 4, , 985 [] G Novikov About one aroach for finite state machines research, Contr Syst ach, No 2, 7 75, 974 (in Russian) [] A D Hon, Wilson Nanowire-based sublithograhic rogrammable logic arrays, International Journal of ACS, vol 7, No 4, , 27 [2] D Kania, RCzerwiski Area and seed oriented synthesis of FS for PAL-based CPLDs, icrorocessors and icrosystems, vol 36, No, 45 6, 22 [3] I Levin Decomosition design of automata based on PLA with memory, Automatic Control and Comuter Sciences, vol 2, No 2, 6 68, 986 [4] Z Navabi, Embedded core design with FPGA, NY: cgraw-hill, 997 [5] E Sentovich, K Singh, L Lavagno, C oon, R urgai, A Saldanh, H Savoj, P Stehan, R Brayton, A Sangiovanni-Vincentelli, SIS: a system for sequential circuit synthesis, in Proc of International Conference on Comuter Design ( ICCD 92), Cambridge, A, USA, , 992 [6] A Shrestha, ATakaota, S Tayu, S Ueno On two roblems of nano- PLA design, IEEE Trans on Informatics and Systems, vol E94, No, 25 4, 2 [7] S Singh, R Singh, Bhatia Performance evaluation of hybrid reconfigurable comuting architecture over symmetrical FPGAs, International Journal of Embedded Systems & Alications, vol 2, No 3, 7-6, 22 [8] I Skliarova, V Sklyarov, A Sudnitson, Design of FPGA-based circuits using hierarchical finite state machines, Tallinn: TUT Press, 28 [9] V Sklyarov, Synthesis of automata with matrix VLSIs, insk: Nauka i Technika, 984, (in Russian) [2] Smith, Alication secific integrated circuits, Boston: Addison- Wesley, 997 [2] T Villa, A Sangiovanni-Vincentelli NOVA: state assignment of finite state machines for otimal two-level logic imlementation, IEEE Trans on CAD,vol 9, No 9, , 99 [22] XILINX Website of the Xilinx Cororation;22 htt://wwwxilinxcom wwwijcitcom 36