Single Event Upset Behavior of CMOS Static RAM cells Kjell O. Jeppson, Udo Lieneweg and Martin G. Buehler

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1 Single Event Uset Behavior of MOS Static RAM cells Kjell O. Jeson, Udo Lieneweg and Martin G. Buehler Abstract An imroved state-sace analysis of the MOS static RAM cell is resented. Introducing the concet of the dividing line, the critical charge for heavy-ioninduced uset of memory cells can be calculated considering symmetrical as well as asymmetrical caacitive loads. From the critical charge, the usetrate er bit-day for static RAMs can be estimated. Introduction To redict the heavy-ion-induced uset rate of static random access memory (SRAM) cells, Buehler and Allen [] develoed an analytical method based on state-sace analysis []. ell usets are eventually caused if the hole-electron airs generated along the track of an alha article hitting the memory cell, are collected by the reverse-biased n-junction of an outut node. A 5 MeV alha article generates, aroximately, an estimated one million holeelectron airs corresonding to a charge of 0.6. If this charge is collected by the reverse-biased njunction of an outut node, this node will be charged or discharged deending on its state. If the current ulse during the alha hit is short comared to the resonse time of the cell, the node set and release aroach [] can be used. In this aroach, the outut node voltage is set by the alha hit, whereafter the released cell is analyzed to see if the alha hit causes an uset or not. For 5-MeV alha articles, the node set and release aroach is justified by the fact that, even if the current ulse is best aroximated by a decaying exonential with a time constant of ns [3], most of the charges are collected within 00 s [4]. In this aer, an imroved analysis of the static RAM-cell in the release mode is resented which yields better understanding of the RAM cell behavior and more accurate exressions of the critical uset charge. The analysis is based on the cell behavior close to the meta-stable state rather than on emirical observations of the initial sloes of the node voltage curves. Kjell O. Jeson is with halmers University of Technology, Deartment of Solid-State Electronics, Gothenburg, Sweden. Udo Lieneweg and Martin G. Buehler are wih the enter for Sace Microelectronics Technology, Jet Proulsion Laboratory, alifornia Institute of Technology, Pasadena, A 909, USA. State-sace analysis The core of a MOS static RAM cell is the bistable latch, or fli-flo, consisting of two cross-couled inverters as shown in Fig.. The two couling nodes, N and N, have effective caacitances to ground, and, resectively, and a mutual caacitance m. The state of the fli-flo is described by the two node voltages, V and V. The bistable fli-flo has three steady states: the one-state (0, V DD ), the zero-state (V DD ), 0) and the unstable state (V M,V M ), ususally known as the metastable state. The dynamic behaviour of the fli-flo is described by the current equations of the two nodes, i.e.: dv dv dv i m dt dt dt. () dv dv dv i m dt dt dt. () where i and i are the currents flowing into the two nodes N and N. The two equations closing the system are governed by Kirchhoffs current law and gives i i i. (3) n i i i. (4) n Fig.. Two cross-couled inverters are used to design a bistable fli-flo. Revised 07 June 9, 993

2 where i (V,V ) and i (V,V ) are the currents through the two P-channel transistors and i n (V,V ) and i n (V,V ) are the currents through the two N- channel transistors, resectively. The three steady state solutions of the system are given by i i i, (5) n 0 n 0 i i i. (6) where the two equations reresent the transfer curves of the two inverters as shown in Fig.. If the fli-flo, for any reason such as an alha article hit, is uset from its steady states, the return-trajectory from any given state, (V 0,V 0 ), to one of the steady states has to be derived numerically. This is because of the comlicated nonlinear voltage deendence of the transistor and caacitor models, which results in non-linear differential equations, and which generally cannot be solved analytically. The most convenient way to solve the roblem is to use a circuit simulator such as SPIE. A tyical examle of the results of such simulations is shown in Fig. 3. Equations () and () give directly the velocity in state sace, dv dv v, dt dt. if the dc current-voltage characteristic of the latch, i (V,V ), i (V,V ), and the node caacitances are known. In Fig. 4 the two velocity comonents are shown lotted in the V,V -state lane, while Fig. 5 shows the corresonding vector field reresentation. As illustrated in Fig. 4 each velocity comonent is zero along the corresonding transfer curve (as long as the mutual caacitance can be neglected). For the steady state solutions both velocity comonents are zero. From the velocity vector field the sloe, dv /dv, is known analytically in any oint along each of the return trajectories as shown in Fig. 3. The velocity vector field also allows a grahical construction of the return trajectories by following the directions given by the vectors as illustrated in Fig. 5. Note that the return trajectories will always cross the static transfer curve characterized by i =0 horizontally, and the other static transfer curve (characterized by i =0) vertically [5]. Of articular interest with resect to single event usets are the two trajectories leading to the metastable oint. These two trajectories divide the state-lane into two halves and will serve as a searatrix [6] or dividing line during the alha article hit. If this dividing line is crossed during the hit, the cell will be uset and change its state during the following release mode, otherwise it will return to the same state as before. The next section will give an analytical exression for the dividing line as a guide for the RAM designer. Fig.. The static transfer curves of the two inverters in a fli-flo are illustrated in the (V,V ) state lane. Fig. 3. SPIE-simulated return- trajcetories to one of thte stable states from an arbitrary oint (V 0,V 0 ), in the (V,V ) state lane. June 9, 993

3 Fig. 4. Phase-sace diagrams for the velocities dv /dt (left) and dv /dt (right). caacitance m, and the outut conductances of the transistors, we obtain from Eqs () and (), gmn gm V VM mn m M dv dv g g V V. (7) where g mn and g m are the transconductances in the metastable oint (V m,v m ) of the n- and -channel transistors, resectively. Assuming a linear relationshi between V and V along the dividing line, V V K( V V. (8) M M ) Fig. 5. The velocity vector field in the (V,V ) state lane for / =0.5 and n / =3.3. Also shown is one of the ossible return trajectories and the two halves of the searatrice ending in the metastable oint. Analytical Descrition of the Dividing Line To derive analytical exressions for the dividing line, simlified transistor models must be used. Simulations using different transistor models suggest that the trajectories leading to the metastable state, i.e. the dividing line, can be aroximated by a straight line with very good accuracy. To derive an exression for the sloe of this line, transistor currents i and i are linearized around the metastable oint. Assuming identical inverters (excet for their caacitive loads), and neglecting the mutual where K = dv /dv, we obtain K. (9) This result suggests that the RAM cell enters the metastable state along a straight line with sloe /, and leaves it along another straight line with sloe - /. The dividing line is therefore given by V V ( V V ). (0) M Simulations show that this equation for the dividing line is a very good aroximation of the simulated behavior. To examine closer the tification of assuming a constant transconductance in the saturation region, let us use a modified Shockley transistor model i n k n ( VGS VTN ) n M. () 3 June 9, 993

4 where k n is the transistor gain factor, V TN the threshold voltage and n the Taylor series exansion coefficient of the bulk charge (in standard textbook equations, usually n =0). In this model, the transistor is saturated for V DS >V DSAT =(V GS -V TN )/(+ n ). The linear region drain current is given by in kn ( VGS VTN ) VDS n V DS. () Using similar equations for the -channel tmnsistor, we can write the two node currents as n i V ( V VDD VTP ) ( V VTN ), (3) and n i V ( V VDD VTP ) ( V VTN ). (4) where for a -tye transistor =k /(+ ). For the secial case when n = =, we obtain a constant transconductance, g g g ( V V V ), (5) m mn m DD TP TN for the region where all four transistors are saturated. Hence, for this region shown shaded in Fig. 6 the linear equation given by Eq. (0) is an exact solution for the dividing line. For the more general case when n, we obtain from Eqs () and () neglecting m dv dv i V i V. (6) Searating variables, we obtain after integration V V V V V V V V V V V V Fig. 6. All four transistors are saturated in the shadowed area. n = =0.3, V TN =-V TN =V DD /5. The reviously obtained straight line solution for the case of n = given by Eq. (0) is simly a secial case of the general solution in Eq. (7). A lot of the dividing line for the case of n / =3.3 is shown in Fig. 7 using / as the arameter ( / =, 0.7, 0.5, 0.5 and 0.). As indicated by Fig. 7, the dividing line is very close to a straight line also for n. As an examle, the second order deviation in V for V =V DD ) is less than 5% for n / =3.3 and / >0.. For = it is exactly a straight line. omarisons to SPIE simulations show that the solution of Eq. (7) can be extended with small errors also into regions of the state lane where one transistor is linear if the current through this transistor is small comared to the current through the other transistor of the same inverter VDD TP n V TN VDD TP M n V M TN V V V V DD TP n TN DD TP M n M TN, where the metastable oint (V M,V M ) is given by V V V xv x with x /. DD TP TN M n (8) In Fig. 6 the region when Eq. (7) is valid is shaded. This region is defined by the following border line equations 6. VVTN V VDD VTP V VTN V VDD VTP For the examle V Vshown in Fig. 7, where, n / V= 3.3, V, V V V V, V V V V transistor n P becomes linear along the dividing n line when / However, the error is negligible For the V VTN VDD VTP VM ( VM VTN ) 3 VDD VTP VTN ( V VM ). 4 June 9, 993 (7) For the examle shown in Fig. 7 where n / =3.3, transistor P becomes linear along the dividing line when / However, the error is negligible as long as as i is less than one tenth of i n (which is true for / 0.07). DD DD TN DD TP TN DD TP For n =, Eq. (7) yields (V - V M ) = (V - V M ), an equation from which Eq. (0) was obtained. In regions outside the shaded area where one of the transistors (for instance P ) is turned OFF, the dividing line only slightly deviates from a straight line as shown by the following equation obtained from Eq. (7)

5 For the limiting case of very small / caacitance ratios, the dividing line becomes a horizontal line through the metastable state. The return track from the metastable state to one of the stable states then coincides with the static transfer curve (obtained for i =0). For very large / caacitance ratios the limiting dividing line is a vertical line through the metastable state. The return track from the metastable state to one of the stable states now coincides with the other static transfer curve (i =0). See Aendix. Fig. 7. The dividing line for n / =3.3 with arameter / =, 0.7, 0.5, 0.5 and 0.. ritical harge Exressions To calculate the uset-rate of a static RAM in sace, Buehler and Allen used the Petersen equation [7] which assumes a 0-ercent worst case differential cosmic-ray sectrum. According to the Petersen equation, the uset rate (in usets er bit-day) for a heavy-ion hit on a q-tye reverse-biased n-junction of node i is given by equation X 0 qi Ri 50 AJ qi. (6) Q qi where AJ qi is the area of the reverse-biased njunction of node i (in m ), X qi is the carrier collection deth of the same junction (in m), and Q qi is the critical charge (in ). The critical charge for a heavy-ion-induced uset can be calculated for each reverse-biased n-junction of the RAM cell using the results from the revious analysis. For / the critical charges for a hit of inverter is calculated as follows. With the RAM cell being in the zero-state, V =0 and the drain of transistor P is reverse-biased. The critical voltage, V, for a P heavy-ion hit is obtained from the dividing line at V =V DD, []. In the one-state, V =V DD and the drain of transistor N is reverse-biased. The critical voltage, V n, for an N heavy-ion hit is obtained from the dividing line at V =0 []. Therefore, the critical voltages can he obtained from the straight line equation (0) as V VM VDD VM. (0) and n M M V V V. () resectively. The exression for V of Eq. (0) can be comared to the exression derived by Buehler and Allen. They based their analysis on the emirical observation that dv dv V. () V DD at (V DD,V ) in the state-lane. After some aroximations their derivation yielded V V V V. (3) TN DD TN Here, it can be seen that while their exression for V only deends on the threshold voltage of the n- channel transistors, the new exression in Eq. (0) deends on the switching voltage of the inverter. Thereby, the influences of both the - and n-channel transistors are considered. From the critical voltages, V and V n, Buehler and Allen [] defined the corresonding critical charges for memory uset by a P- and N-hit as and Q V. (4) n DD n Q V V. (5) resectively. The critical charge is the minimum charge needed for memory uset, assuming that the charge is collected so raidly that the voltage on the other node does not change. This is true for most memory 5 June 9, 993

6 cells since they, tyically, have a slow resonse time (>500 s) and most of the charge is collected within 00 s as shown by [4]. However, if charge is lost during the alha hit more charge must be collected to uset the cell. To simulate the cell during the alha hit, one must be concerned with the detailed nature of the current ulse. For 5 MeV alha articles, the current ulse can be aroximated by a decaying exonential with a time constant of ns [3]. However, in most cases, as in the simulated cases shown in Fig. 8, a simle square-wave current ulse is a good enough first-order aroximation [8]. The corresonding set and release trajectories simulated for five different current sources are shown in Fig. 9. Fig. 8. The relative critical charge for memory uset versus the relative current ulse (normalized to the transistor saturation current). Fig. 9. The set and release trajectories for five different current ulses during the alha hit. The current ulse is normalized to the transistor saturation current. The critical charges for a hit of inverter can be calculated similarly, at least for caacitively symmetric RAM cells or when / >l. In order to estimate the critical charges for N or P hits when / <l, one has to know how the dividing line continues into the regions where V <0 and V >V DD. Due to the forward biasing of the drain diodes N or P, resectively, large restoring currents i develo, bending the dividing line almost horizontal outside the frame of Fig. 7. onsequently, the dividing line will be imossible to reach by N or P hits, i. e. Q n and Q become very large and the corresonding uset rates can be neglected. Acknowledgements This roject was initiated by Dr Martin Buehler while on sabbatical leave at halmers University of Technology from Jet Proulsion Laboratory (JPL), alifornia Institute of Technology. The Swedish National Board for Technical Develoment (STU) is greatfully acknowledged for its financial suort. The JPL art of this roject was carried out at its enter for Sace Micro-electronics Technology and was sonsored by the National Aeronautics and Sace Administration (NASA) and the U.S. Deartment of Defense (DoD). Finally, the authors would like to thank Professor Olof Engström for many stimulating discussions and Dr Sven hristenson, halmers, and Brent Blaes, JPL, for their great efforts in generating many of the figures. References [] M. Buehler and R. Allen, An Analytical Method for Predicting MOS SRAM Usets with Alication to Asymmetrical Memory ells, IEEE Transactions on Nuclear Science, NS-33, (986) [] R.. Jaeger and R. M. Fox, Analytic Exressions for the ritical harge in MOS Static RAM ells, IEEE Transactions on Nuclear Science, NS-30, (983) [3] R. J. McPartland, ircuit Simulations of Alha-Particle-Induced Soft Errors in MOS Dynamic RAM s, IEEE Journal of Solid-State ircuits, S-6, (98) [4]. M. Hsieh, P.. Murley and R. R. O Brien, Dynamics of harge ollection from Alha- Particle Tracks in Integrated ircuits, in Proceedings of 0th Annual International Reliability Symosium. Orlando, FL, 38-4 (98) 6 June 9, 993

7 [5] L. A. Glasser and D. W. Dobberuhl, The Design and Analysis of VLSI ircuits, ha 5 (Fig. 5.38), Reading, MA, USA: Addison- Wesley, (985) [6] D. K. Arrowsmith and. M. Place, Ordinary Differential Equations, London, New York: haman and Hall (98) [7] E. L. Petersen, J, B. Langworthy and S. E. Diehl, Suggested Single Event- Uset Figure of Merit, IEEE Transaction on Nuclear Science, NS-30, (983) [8] Y. Idei, N. Homma, H. Narnbu and Y. Sakurai, Soft-Error haracteristics in Biolar Memory ells with Small ritical harge, IEEE Transactions on Electron Devices, ED-38, (99) 7 June 9, 993

8 APPENDIX Generally, Eqs () and () can be rewritten as where dv i i. (A) dt dv i i (A) dt m. (A3) m. (A4) m m. (A5) m Using the following linear aroximation of the transistor currents, i g ( V V ) g ( V V ). (A6) m m 0 m i g ( V V ) g ( V V ). (A7) m m 0 m where g m =g mn +g m is the sum of the n- and -channel transconductances in the metastable oint (V M,V M ) and g o = g on + g o is the the sum of the outut conductances, we obtain where M M dv a V V b V V dv a V V b V V a b M m o m o M, (A8) g g g g a (A9) g g g g b. (A0) o m o m Assuming a linear relationshi between V and V along the dividing line, i.e. m m V V K V V, (A) we obtain the sloe b a b a b K a a 4 a a a. (A) If the mutual caacitance can be neglected comared to the load caacitances, the exression for the sloe reduces to, (A3) K c c where g o c. gm As exected, this exression reduces further to K=± / while assuming g o =0. Assuming g o 0 and letting, we obtain from Eq. (A3) 0 K go. (A4) g m which confirms an incoming horizontal line to the metastable state and an outgoing line with a sloe given by the recirocal gain of the inverter. Similarly, letting, we obtain K g m. (A5) go which confirms an incoming vertical line to the metastable state and an outgoing line with a sloe given by the gain of the inverter. Finally, if the mutual caacitances cannot be neglected, we obtain assuming g o =0. K. (A6) 8 June 9, 993